From: John Feeney <jfeeney@redhat.com>
Date: Fri, 3 Sep 2010 17:59:28 -0400
Subject: [net] tg3: disable PME bit during resume
Message-id: <4C813780.1090900@redhat.com>
Patchwork-id: 28123
O-Subject: [RHEL5.6 PATCH] Disable PME bit during resume in tg3
Bugzilla: 598530
RH-Acked-by: Andy Gospodarek <gospo@redhat.com>
RH-Acked-by: David S. Miller <davem@redhat.com>
RH-Acked-by: Stefan Assmann <sassmann@redhat.com>

bz598530
https://bugzilla.redhat.com/bugzilla/show_bug.cgi?id=598530
PCI PME# is not disabled by tg3 after resume

Description of problem:
The tg3 module sets the PME enable bit of the PCI PM Status/Control register,
0x4C, during module initialization. But this bit is not cleared after the
device resumes to D0 state.

Solution:
Upstream calls a series of pci power state functions, pci_enable_wake(),
pci_set_power_state(), to provide for the management of this bit, but none
of these calls are in RHEL5. After discussion with Matthew Garrett about
the feasibility of backporting these functions, it was determined that
it was not. Hence, this patch provided simply disables the bit in tg3.

Upstream commit: n/a

Brew:
Successfully built in Brew for all architectures (task_2733067).

Testing:
I have tested suspend/resume with the patch successfully. I will
ask the reporter to test and provide feedback when available.

Acks would be appreciated. Thanks.

Signed-off-by: Jarod Wilson <jarod@redhat.com>

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index c2023ec..feaa01f 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -2187,6 +2187,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
 	switch (state) {
 	case PCI_D0:
 		power_control |= 0;
+		power_control &= ~PCI_PM_CTRL_PME_ENABLE;
 		pci_write_config_word(tp->pdev,
 				      pm + PCI_PM_CTRL,
 				      power_control);