From a3bcf40eaf85196a3fae215502def544fb8780fe Mon Sep 17 00:00:00 2001 From: Eduardo Habkost <ehabkost@redhat.com> Date: Fri, 2 Oct 2009 14:15:29 -0300 Subject: [PATCH 06/10] set CPUID bits to present cores and threads topology RH-Author: Gleb Natapov <gleb@redhat.com> Message-id: <1253608839-4319-7-git-send-email-gleb@redhat.com> Patchwork-id: 3484 O-Subject: [PATCH 6/7] set CPUID bits to present cores and threads topology Bugzilla: 508040 RH-Acked-by: Mark McLoughlin <markmc@redhat.com> RH-Acked-by: Markus Armbruster <armbru@redhat.com> RH-Acked-by: Juan Quintela <quintela@redhat.com> Controlled by the enhanced -smp option set the CPUID bits to present the guest the desired topology. This is vendor specific, but (with the exception of the CMP_LEGACY bit) not conflicting, so we set all bits everytime. There is no real multithreading support for AMD CPUs, so report cores instead. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Gleb Natapov <gleb@redhat.com> --- qemu/target-i386/helper.c | 28 +++++++++++++++++++++++++--- 1 files changed, 25 insertions(+), 3 deletions(-) Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- qemu/target-i386/helper.c | 28 +++++++++++++++++++++++++--- 1 files changed, 25 insertions(+), 3 deletions(-) diff --git a/qemu/target-i386/helper.c b/qemu/target-i386/helper.c index ab1fcc8..64b5642 100644 --- a/qemu/target-i386/helper.c +++ b/qemu/target-i386/helper.c @@ -1452,6 +1452,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ *ecx = env->cpuid_ext_features; *edx = env->cpuid_features; + if (env->nr_cores * env->nr_threads > 1) { + *ebx |= (env->nr_cores * env->nr_threads) << 16; + *edx |= 1 << 28; /* HTT bit */ + } /* "Hypervisor present" bit required for Microsoft SVVP */ if (kvm_enabled()) @@ -1466,21 +1470,29 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, break; case 4: /* cache info: needed for Core compatibility */ + if (env->nr_cores > 1) { + *eax = (env->nr_cores - 1) << 26; + } else { + *eax = 0; + } switch (*ecx) { case 0: /* L1 dcache info */ - *eax = 0x0000121; + *eax |= 0x0000121; *ebx = 0x1c0003f; *ecx = 0x000003f; *edx = 0x0000001; break; case 1: /* L1 icache info */ - *eax = 0x0000122; + *eax |= 0x0000122; *ebx = 0x1c0003f; *ecx = 0x000003f; *edx = 0x0000001; break; case 2: /* L2 cache info */ - *eax = 0x0000143; + *eax |= 0x0000143; + if (env->nr_threads > 1) { + *eax |= (env->nr_threads - 1) << 14; + } *ebx = 0x3c0003f; *ecx = 0x0000fff; *edx = 0x0000001; @@ -1534,6 +1546,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, *ecx = env->cpuid_ext3_features; *edx = env->cpuid_ext2_features; + if (env->nr_cores * env->nr_threads > 1 && + env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && + env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && + env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) { + *ecx |= 1 << 1; /* CmpLegacy bit */ + } + if (kvm_enabled()) { uint32_t h_eax, h_edx; @@ -1606,6 +1625,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, *ebx = 0; *ecx = 0; *edx = 0; + if (env->nr_cores * env->nr_threads > 1) { + *ecx |= (env->nr_cores * env->nr_threads) - 1; + } break; case 0x8000000A: *eax = 0x00000001; /* SVM Revision */ -- 1.6.3.rc4.29.g8146