From 6e64837323e3ae2975e57e8e9d4cc99f07566622 Mon Sep 17 00:00:00 2001
From: Naphtali Sprei <nsprei@redhat.com>
Date: Thu, 16 Jul 2009 11:34:17 +0300
Subject: [PATCH 1/3] fix for bug #507942 : bad macaddr of e1000 in Windows 2003 server with original Microsoft driver

Minor comment change (to last sent patch) and fixed WS issue of the patch.

The sequence of reading from eeprom is "offset by one" moved because of a false detection
of a clock cycle after an eeprom reset. Keeping the last clock value after a reset keeps it in sync.

Signed-off-by: Naphtali Sprei <nsprei@redhat.com>
Message-ID: <4A5EE609.3090104@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Bugzilla: 507942
Acked-by: Juan Quintela <quintela@redhat.com>
Acked-by: Luiz Capitulino <lcapitulino@redhat.com>
Acked-by: Eduardo Habkost <ehabkost@redhat.com>
---
 qemu/hw/e1000.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/qemu/hw/e1000.c b/qemu/hw/e1000.c
index d12e14f..48b5d84 100644
--- a/qemu/hw/e1000.c
+++ b/qemu/hw/e1000.c
@@ -263,6 +263,9 @@ set_eecd(E1000State *s, int index, uint32_t val)
     }
     if (!(val & E1000_EECD_CS)) {		// rising, no CS (EEPROM reset)
         memset(&s->eecd_state, 0, sizeof s->eecd_state);
+        // restore old_eecd's E1000_EECD_SK (known to be on)
+        // to avoid false detection of a clock edge
+        s->eecd_state.old_eecd = E1000_EECD_SK;
         return;
     }
     s->eecd_state.val_in <<= 1;
-- 
1.6.3.rc4.29.g8146