From: ddugger@redhat.com <ddugger@redhat.com>
Date: Tue, 21 Apr 2009 13:01:30 -0600
Subject: [xen] pci: fix definition of PCI_PM_CTRL_NO_SOFT_RESET
Message-id: 200904211901.n3LJ1UJw028393@sobek.n0ano.com
O-Subject: [RHEL5.4 PATCH 3/6 V2] BZ496873: xen, pci: Fix the definition of PCI_PM_CTRL_NO_SOFT_RESET.
Bugzilla: 496873
RH-Acked-by: Gerd Hoffmann <kraxel@redhat.com>
RH-Acked-by: Chris Lalancette <clalance@redhat.com>
RH-Acked-by: Rik van Riel <riel@redhat.com>
RH-Acked-by: Gerd Hoffmann <kraxel@redhat.com>
RH-Acked-by: Justin M. Forbes <jforbes@redhat.com>

Minor correcton to use the correct define value

Upstream Status: Accepted
from xen-unstable.hg:
  HG changeset patch
  User Keir Fraser <keir.fraser@citrix.com>
  Date 1235991666 0
  Node ID 4dac26349877cbca0bc727286d4ddaeb190dff4b
  Parent  c9e9602cc080daef0c25869cdec21b4e323fd6dd

Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
Signed-off-by: Gerd Hoffman <kraxel@redhat.com>
Signed-off-by: Don Dugger <donald.d.dugger@intel.com>

Yet Another Resend - resolve the conflicting BZs between the Subject line
(correct) and the message body (incorrect).

diff --git a/include/asm-ia64/linux/pci_regs.h b/include/asm-ia64/linux/pci_regs.h
index c321316..c05dc22 100644
--- a/include/asm-ia64/linux/pci_regs.h
+++ b/include/asm-ia64/linux/pci_regs.h
@@ -229,7 +229,7 @@
 #define  PCI_PM_CAP_PME_D3cold	0x8000	/* PME# from D3 (cold) */
 #define PCI_PM_CTRL		4	/* PM control and status register */
 #define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
-#define  PCI_PM_CTRL_NO_SOFT_RESET	0x0004	/* No reset for D3hot->D0 */
+#define  PCI_PM_CTRL_NO_SOFT_RESET	0x0008	/* No reset for D3hot->D0 */
 #define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
 #define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
 #define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
diff --git a/include/xen/pci_regs.h b/include/xen/pci_regs.h
index c1914a8..361554c 100644
--- a/include/xen/pci_regs.h
+++ b/include/xen/pci_regs.h
@@ -233,7 +233,7 @@
 #define  PCI_PM_CAP_PME_D3cold	0x8000	/* PME# from D3 (cold) */
 #define PCI_PM_CTRL		4	/* PM control and status register */
 #define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
-#define  PCI_PM_CTRL_NO_SOFT_RESET	0x0004	/* No reset for D3hot->D0 */
+#define  PCI_PM_CTRL_NO_SOFT_RESET	0x0008	/* No reset for D3hot->D0 */
 #define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
 #define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
 #define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */