From: Bhavna Sarathy <bnagendr@redhat.com>
Date: Wed, 21 Oct 2009 20:18:53 -0400
Subject: [x86] fix L1 cache by adding missing break
Message-id: <20091021202115.22207.3847.sendpatchset@localhost.localdomain>
Patchwork-id: 21152
O-Subject: [RHEL5.5 PATCH 2/2] Fix L1 cache by adding missing break statement
Bugzilla: 526770
RH-Acked-by: Pete Zaitcev <zaitcev@redhat.com>

Resolves BZ 526770

This is minor fix that prevents L1 contents from tacking on L2 cache contents.
Basically a missing break.  Tested on Dinar systems.

diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c
index 9b2b307..c9b9a22 100644
--- a/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -208,6 +208,7 @@ static void __cpuinit amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
 		line_size = l1->line_size;
 		lines_per_tag = l1->lines_per_tag;
 		size_in_kb = l1->size_in_kb;
+		break;
 	case 2:
 		if (!l2.val)
 			return;