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distrib > Mageia > 8 > armv7hl > media > core-backports-src > by-pkgid > 18e5a698abeca51c4b160a43cd401c92 > files > 29

kernel-5.19.3-1.mga8.src.rpm

From ffe49b797c019830878f81ef280f41336d05437a Mon Sep 17 00:00:00 2001
From: Thomas Backlund <tmb@mageia.org>
Date: Sat, 20 Aug 2022 13:05:27 +0300
Subject: [PATCH] Revert "drm/amdgpu/display: Prepare for new interfaces"

This reverts commit a820190204aef0739aa3a067d00273d117f9367c.

Reported on stable@ to cause audio to stop working.

Signed-off-by: Thomas Backlund <tmb@mageia.org>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 -
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 17 +-----
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 52 ++++++++-----------
 drivers/gpu/drm/amd/display/dc/dc.h           |  1 -
 .../display/dc/dce110/dce110_hw_sequencer.c   | 23 ++------
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 13 ++---
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |  4 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   |  5 --
 .../amd/display/dc/inc/hw_sequencer_private.h |  2 -
 10 files changed, 38 insertions(+), 83 deletions(-)

diff -Nurp linux-5.19.orig/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c linux-5.19/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
--- linux-5.19.orig/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c	2022-08-20 13:43:13.133168965 +0300
+++ linux-5.19/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c	2022-08-20 13:44:50.099168789 +0300
@@ -1563,8 +1563,6 @@ static int amdgpu_dm_init(struct amdgpu_
 		DRM_INFO("Seamless boot condition check passed\n");
 	}
 
-	init_data.flags.enable_mipi_converter_optimization = true;
-
 	INIT_LIST_HEAD(&adev->dm.da_list);
 
 	retrieve_dmi_info(&adev->dm);
diff -Nurp linux-5.19.orig/drivers/gpu/drm/amd/display/dc/core/dc_link.c linux-5.19/drivers/gpu/drm/amd/display/dc/core/dc_link.c
--- linux-5.19.orig/drivers/gpu/drm/amd/display/dc/core/dc_link.c	2022-08-20 13:43:13.133168965 +0300
+++ linux-5.19/drivers/gpu/drm/amd/display/dc/core/dc_link.c	2022-08-20 13:44:50.099168789 +0300
@@ -235,8 +235,7 @@ bool dc_link_detect_sink(struct dc_link
 
 	if (link->connector_signal == SIGNAL_TYPE_EDP) {
 		/*in case it is not on*/
-		if (!link->dc->config.edp_no_power_sequencing)
-			link->dc->hwss.edp_power_control(link, true);
+		link->dc->hwss.edp_power_control(link, true);
 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 	}
 
@@ -1017,7 +1016,6 @@ static bool detect_link_and_local_sink(s
 	bool same_edid = false;
 	enum dc_edid_status edid_status;
 	struct dc_context *dc_ctx = link->ctx;
-	struct dc *dc = dc_ctx->dc;
 	struct dc_sink *sink = NULL;
 	struct dc_sink *prev_sink = NULL;
 	struct dpcd_caps prev_dpcd_caps;
@@ -1097,16 +1095,6 @@ static bool detect_link_and_local_sink(s
 
 			detect_edp_sink_caps(link);
 			read_current_link_settings_on_detect(link);
-
-			/* Disable power sequence on MIPI panel + converter
-			 */
-			if (dc->config.enable_mipi_converter_optimization &&
-				dc_ctx->dce_version == DCN_VERSION_3_01 &&
-				link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
-				memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
-					sizeof(link->dpcd_caps.branch_dev_name)) == 0)
-				dc->config.edp_no_power_sequencing = true;
-
 			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 			sink_caps.signal = SIGNAL_TYPE_EDP;
 			break;
@@ -2005,8 +1993,7 @@ static enum dc_status enable_link_dp(str
 
 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
 		/*in case it is not on*/
-		if (!link->dc->config.edp_no_power_sequencing)
-			link->dc->hwss.edp_power_control(link, true);
+		link->dc->hwss.edp_power_control(link, true);
 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 	}
 
diff -Nurp linux-5.19.orig/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c linux-5.19/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
--- linux-5.19.orig/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c	2022-08-20 13:43:13.134168965 +0300
+++ linux-5.19/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c	2022-08-20 13:44:50.100168789 +0300
@@ -2074,8 +2074,7 @@ static enum link_training_result dp_perf
 	uint32_t wait_time = 0;
 	union lane_align_status_updated dpcd_lane_status_updated = {0};
 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
-	enum dc_status status = DC_OK;
-	enum link_training_result result = LINK_TRAINING_SUCCESS;
+	enum link_training_result status = LINK_TRAINING_SUCCESS;
 	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 
 	/* Transmit 128b/132b_TPS1 over Main-Link */
@@ -2100,24 +2099,22 @@ static enum link_training_result dp_perf
 			lt_settings->pattern_for_eq, DPRX);
 
 	/* poll for channel EQ done */
-	while (result == LINK_TRAINING_SUCCESS) {
+	while (status == LINK_TRAINING_SUCCESS) {
 		dp_wait_for_training_aux_rd_interval(link, aux_rd_interval);
 		wait_time += aux_rd_interval;
-		status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+		dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
 				&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
 		dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
 			lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
 		dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
-		if (status != DC_OK) {
-			result = LINK_TRAINING_ABORT;
-		} else if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count,
+		if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count,
 				dpcd_lane_status)) {
 			/* pass */
 			break;
 		} else if (loop_count >= lt_settings->eq_loop_count_limit) {
-			result = DP_128b_132b_MAX_LOOP_COUNT_REACHED;
+			status = DP_128b_132b_MAX_LOOP_COUNT_REACHED;
 		} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
-			result = DP_128b_132b_LT_FAILED;
+			status = DP_128b_132b_LT_FAILED;
 		} else {
 			dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
 			dpcd_set_lane_settings(link, lt_settings, DPRX);
@@ -2126,26 +2123,24 @@ static enum link_training_result dp_perf
 	}
 
 	/* poll for EQ interlane align done */
-	while (result == LINK_TRAINING_SUCCESS) {
-		if (status != DC_OK) {
-			result = LINK_TRAINING_ABORT;
-		} else if (dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) {
+	while (status == LINK_TRAINING_SUCCESS) {
+		if (dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) {
 			/* pass */
 			break;
 		} else if (wait_time >= lt_settings->eq_wait_time_limit) {
-			result = DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT;
+			status = DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT;
 		} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
-			result = DP_128b_132b_LT_FAILED;
+			status = DP_128b_132b_LT_FAILED;
 		} else {
 			dp_wait_for_training_aux_rd_interval(link,
 					lt_settings->eq_pattern_time);
 			wait_time += lt_settings->eq_pattern_time;
-			status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+			dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
 					&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
 		}
 	}
 
-	return result;
+	return status;
 }
 
 static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
@@ -2154,8 +2149,7 @@ static enum link_training_result dp_perf
 		struct link_training_settings *lt_settings)
 {
 	/* Assumption: assume hardware has transmitted eq pattern */
-	enum dc_status status = DC_OK;
-	enum link_training_result result = LINK_TRAINING_SUCCESS;
+	enum link_training_result status = LINK_TRAINING_SUCCESS;
 	union lane_align_status_updated dpcd_lane_status_updated = {0};
 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
 	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
@@ -2165,26 +2159,24 @@ static enum link_training_result dp_perf
 	dpcd_set_training_pattern(link, lt_settings->pattern_for_cds);
 
 	/* poll for CDS interlane align done and symbol lock */
-	while (result  == LINK_TRAINING_SUCCESS) {
+	while (status == LINK_TRAINING_SUCCESS) {
 		dp_wait_for_training_aux_rd_interval(link,
 				lt_settings->cds_pattern_time);
 		wait_time += lt_settings->cds_pattern_time;
-		status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+		dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
 						&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
-		if (status != DC_OK) {
-			result = LINK_TRAINING_ABORT;
-		} else if (dp_is_symbol_locked(lt_settings->link_settings.lane_count, dpcd_lane_status) &&
+		if (dp_is_symbol_locked(lt_settings->link_settings.lane_count, dpcd_lane_status) &&
 				dpcd_lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b) {
 			/* pass */
 			break;
 		} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
-			result = DP_128b_132b_LT_FAILED;
+			status = DP_128b_132b_LT_FAILED;
 		} else if (wait_time >= lt_settings->cds_wait_time_limit) {
-			result = DP_128b_132b_CDS_DONE_TIMEOUT;
+			status = DP_128b_132b_CDS_DONE_TIMEOUT;
 		}
 	}
 
-	return result;
+	return status;
 }
 
 static enum link_training_result dp_perform_8b_10b_link_training(
@@ -7107,8 +7099,7 @@ void dp_enable_link_phy(
 	unsigned int i;
 
 	if (link->connector_signal == SIGNAL_TYPE_EDP) {
-		if (!link->dc->config.edp_no_power_sequencing)
-			link->dc->hwss.edp_power_control(link, true);
+		link->dc->hwss.edp_power_control(link, true);
 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 	}
 
@@ -7235,8 +7226,7 @@ void dp_disable_link_phy(struct dc_link
 			link->dc->hwss.edp_backlight_control(link, false);
 		if (link_hwss->ext.disable_dp_link_output)
 			link_hwss->ext.disable_dp_link_output(link, link_res, signal);
-		if (!link->dc->config.edp_no_power_sequencing)
-			link->dc->hwss.edp_power_control(link, false);
+		link->dc->hwss.edp_power_control(link, false);
 	} else {
 		if (dmcu != NULL && dmcu->funcs->lock_phy)
 			dmcu->funcs->lock_phy(dmcu);
diff -Nurp linux-5.19.orig/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c linux-5.19/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
--- linux-5.19.orig/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c	2022-08-20 13:43:13.135168965 +0300
+++ linux-5.19/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c	2022-08-20 13:44:50.101168789 +0300
@@ -1245,18 +1245,8 @@ void dce110_blank_stream(struct pipe_ctx
 			 * has changed or they enter protection state and hang.
 			 */
 			msleep(60);
-		} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
-			if (!link->dc->config.edp_no_power_sequencing) {
-				/*
-				 * Sometimes, DP receiver chip power-controlled externally by an
-				 * Embedded Controller could be treated and used as eDP,
-				 * if it drives mobile display. In this case,
-				 * we shouldn't be doing power-sequencing, hence we can skip
-				 * waiting for T9-ready.
-				 */
-				edp_receiver_ready_T9(link);
-			}
-		}
+		} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
+			edp_receiver_ready_T9(link);
 	}
 
 }
@@ -2171,18 +2161,15 @@ static void dce110_setup_audio_dto(
 			build_audio_output(context, pipe_ctx, &audio_output);
 
 			if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
-				struct dtbclk_dto_params dto_params = {0};
+				/* disable audio DTBCLK DTO */
+				dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
+					dc->res_pool->dccg, 0);
 
 				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
 						pipe_ctx->stream_res.audio,
 						pipe_ctx->stream->signal,
 						&audio_output.crtc_info,
 						&audio_output.pll_info);
-
-				dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
-					dc->res_pool->dccg,
-					&dto_params);
-
 			} else
 				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
 					pipe_ctx->stream_res.audio,
diff -Nurp linux-5.19.orig/drivers/gpu/drm/amd/display/dc/dc.h linux-5.19/drivers/gpu/drm/amd/display/dc/dc.h
--- linux-5.19.orig/drivers/gpu/drm/amd/display/dc/dc.h	2022-08-20 13:43:13.134168965 +0300
+++ linux-5.19/drivers/gpu/drm/amd/display/dc/dc.h	2022-08-20 13:44:50.100168789 +0300
@@ -337,7 +337,6 @@ struct dc_config {
 	bool is_single_rank_dimm;
 	bool use_pipe_ctx_sync_logic;
 	bool ignore_dpref_ss;
-	bool enable_mipi_converter_optimization;
 };
 
 enum visual_confirm {
diff -Nurp linux-5.19.orig/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c linux-5.19/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
--- linux-5.19.orig/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c	2022-08-20 13:43:13.135168965 +0300
+++ linux-5.19/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c	2022-08-20 13:44:50.101168789 +0300
@@ -513,7 +513,7 @@ void dccg31_set_physymclk(
 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
 static void dccg31_set_dtbclk_dto(
 		struct dccg *dccg,
-		const struct dtbclk_dto_params *params)
+		struct dtbclk_dto_params *params)
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 	int req_dtbclk_khz = params->pixclk_khz;
@@ -579,17 +579,18 @@ static void dccg31_set_dtbclk_dto(
 
 void dccg31_set_audio_dtbclk_dto(
 		struct dccg *dccg,
-		const struct dtbclk_dto_params *params)
+		uint32_t req_audio_dtbclk_khz)
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
-	if (params->ref_dtbclk_khz && params->req_audio_dtbclk_khz) {
+	if (dccg->ref_dtbclk_khz && req_audio_dtbclk_khz) {
 		uint32_t modulo, phase;
 
 		// phase / modulo = dtbclk / dtbclk ref
-		modulo = params->ref_dtbclk_khz * 1000;
-		phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1),
-			params->ref_dtbclk_khz);
+		modulo = dccg->ref_dtbclk_khz * 1000;
+		phase = div_u64((((unsigned long long)modulo * req_audio_dtbclk_khz) + dccg->ref_dtbclk_khz - 1),
+			dccg->ref_dtbclk_khz);
+
 
 		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo);
 		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase);
diff -Nurp linux-5.19.orig/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h linux-5.19/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
--- linux-5.19.orig/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h	2022-08-20 13:43:13.135168965 +0300
+++ linux-5.19/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h	2022-08-20 13:44:50.101168789 +0300
@@ -192,7 +192,7 @@ void dccg31_set_physymclk(
 
 void dccg31_set_audio_dtbclk_dto(
 		struct dccg *dccg,
-		const struct dtbclk_dto_params *params);
+		uint32_t req_audio_dtbclk_khz);
 
 void dccg31_set_hdmistreamclk(
 		struct dccg *dccg,
diff -Nurp linux-5.19.orig/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h linux-5.19/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
--- linux-5.19.orig/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h	2022-08-20 13:43:13.135168965 +0300
+++ linux-5.19/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h	2022-08-20 13:44:50.101168789 +0300
@@ -120,11 +120,11 @@ struct dccg_funcs {
 
 	void (*set_dtbclk_dto)(
 			struct dccg *dccg,
-			const struct dtbclk_dto_params *params);
+			struct dtbclk_dto_params *dto_params);
 
 	void (*set_audio_dtbclk_dto)(
 			struct dccg *dccg,
-			const struct dtbclk_dto_params *params);
+			uint32_t req_audio_dtbclk_khz);
 
 	void (*set_dispclk_change_mode)(
 			struct dccg *dccg,
diff -Nurp linux-5.19.orig/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h linux-5.19/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
--- linux-5.19.orig/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h	2022-08-20 13:43:13.135168965 +0300
+++ linux-5.19/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h	2022-08-20 13:44:50.101168789 +0300
@@ -346,11 +346,6 @@ struct mpc_funcs {
 			int mpcc_id,
 			const struct mpc_grph_gamut_adjustment *adjust);
 
-	bool (*program_1dlut)(
-			struct mpc *mpc,
-			const struct pwl_params *params,
-			uint32_t rmu_idx);
-
 	bool (*program_shaper)(
 			struct mpc *mpc,
 			const struct pwl_params *params,
diff -Nurp linux-5.19.orig/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h linux-5.19/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
--- linux-5.19.orig/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h	2022-08-20 13:43:13.135168965 +0300
+++ linux-5.19/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h	2022-08-20 13:44:50.101168789 +0300
@@ -140,8 +140,6 @@ struct hwseq_private_funcs {
 			const struct dc_plane_state *plane_state);
 	bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
 			const struct dc_plane_state *plane_state);
-	bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,
-			const struct dc_plane_state *plane_state);
 	void (*PLAT_58856_wa)(struct dc_state *context,
 			struct pipe_ctx *pipe_ctx);
 	void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);

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