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<title>PIC16F884</title>
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<ul class="classMenu">
<li><a href="index.html">All</a></li>
<li><a href="enhanced-mcus.html">Enhanced</a></li>
<li><a href="extended-mcus.html">Extended</a></li>
<li><a href="regular-mcus.html">Regular</a></li>
<li><a href="12-bits-mcus.html">12 bits</a></li>
<li><a href="14-bits-mcus.html">14 bits</a></li>
<li><a href="16-bits-mcus.html">16 bits</a></li>
<li><a href="mcus-by-ram-size.html">by RAM size</a></li>
<li><a href="mcus-by-rom-size.html">by ROM size</a></li>
<li><a href="mcus-by-eeprom-size.html">by EEPROM size</a></li>
</ul>
<ul class="tabs">
<li><a href="PIC16F884-feat.html">Features</a></li>
<li><a href="PIC16F884-conf.html">Configuration Bits</a></li>
<li><a href="PIC16F884-ram.html">RAM map</a></li>
<li class="selected"><a href="PIC16F884-sfr.html">SFR map</a></li>
</ul>
<table class="sfrMap">
<tr><th colspan=9 class="sfrTableName">PIC16F884</th></tr>
<tr class="sfrGap"><td></td></tr>
<tr class="sfrHead">
<td class="vMargin"></td>
<th class="sfrBank">Bank 0</th>
<td class="vMargin"></td>
<th class="sfrBank">Bank 1</th>
<td class="vMargin"></td>
<th class="sfrBank">Bank 2</th>
<td class="vMargin"></td>
<th class="sfrBank">Bank 3</th>
<td class="vMargin"></td>
</tr>
<tr class="sfrGap"><td></td></tr>
<tr>
<td class="vMargin"></td>
<td class="sfrColumn">
<table>
<tr id="INDF">
<th class="sfrName">INDF</th>
<td class="sfrAddr">0x000</td>
</tr>
<tr id="TMR0">
<th class="sfrName">TMR0</th>
<td class="sfrAddr">0x001</td>
</tr>
<tr id="PCL">
<th class="sfrName">PCL</th>
<td class="sfrAddr">0x002</td>
</tr>
<tr id="STATUS">
<th class="sfrName">STATUS</th>
<td class="sfrAddr">0x003</td>
</tr>
<tr id="FSR">
<th class="sfrName">FSR</th>
<td class="sfrAddr">0x004</td>
</tr>
<tr id="PORTA">
<th class="sfrName">PORTA</th>
<td class="sfrAddr">0x005</td>
</tr>
<tr id="PORTB">
<th class="sfrName">PORTB</th>
<td class="sfrAddr">0x006</td>
</tr>
<tr id="PORTC">
<th class="sfrName">PORTC</th>
<td class="sfrAddr">0x007</td>
</tr>
<tr id="PORTD">
<th class="sfrName">PORTD</th>
<td class="sfrAddr">0x008</td>
</tr>
<tr id="PORTE">
<th class="sfrName">PORTE</th>
<td class="sfrAddr">0x009</td>
</tr>
<tr id="PCLATH">
<th class="sfrName">PCLATH</th>
<td class="sfrAddr">0x00A</td>
</tr>
<tr id="INTCON">
<th class="sfrName">INTCON</th>
<td class="sfrAddr">0x00B</td>
</tr>
<tr id="PIR1">
<th class="sfrName">PIR1</th>
<td class="sfrAddr">0x00C</td>
</tr>
<tr id="PIR2">
<th class="sfrName">PIR2</th>
<td class="sfrAddr">0x00D</td>
</tr>
<tr id="TMR1">
<th class="sfrNameX">TMR1<span>TMR1L</span></th>
<td class="sfrAddr">0x00E</td>
</tr>
<tr id="TMR1H">
<th class="sfrName">TMR1H</th>
<td class="sfrAddr">0x00F</td>
</tr>
<tr id="T1CON">
<th class="sfrName">T1CON</th>
<td class="sfrAddr">0x010</td>
</tr>
<tr id="TMR2">
<th class="sfrName">TMR2</th>
<td class="sfrAddr">0x011</td>
</tr>
<tr id="T2CON">
<th class="sfrName">T2CON</th>
<td class="sfrAddr">0x012</td>
</tr>
<tr id="SSPBUF">
<th class="sfrName">SSPBUF</th>
<td class="sfrAddr">0x013</td>
</tr>
<tr id="SSPCON">
<th class="sfrName">SSPCON</th>
<td class="sfrAddr">0x014</td>
</tr>
<tr id="CCPR1">
<th class="sfrNameX">CCPR1<span>CCPR1L</span></th>
<td class="sfrAddr">0x015</td>
</tr>
<tr id="CCPR1H">
<th class="sfrName">CCPR1H</th>
<td class="sfrAddr">0x016</td>
</tr>
<tr id="CCP1CON">
<th class="sfrName">CCP1CON</th>
<td class="sfrAddr">0x017</td>
</tr>
<tr id="RCSTA">
<th class="sfrName">RCSTA</th>
<td class="sfrAddr">0x018</td>
</tr>
<tr id="TXREG">
<th class="sfrName">TXREG</th>
<td class="sfrAddr">0x019</td>
</tr>
<tr id="RCREG">
<th class="sfrName">RCREG</th>
<td class="sfrAddr">0x01A</td>
</tr>
<tr id="CCPR2">
<th class="sfrNameX">CCPR2<span>CCPR2L</span></th>
<td class="sfrAddr">0x01B</td>
</tr>
<tr id="CCPR2H">
<th class="sfrName">CCPR2H</th>
<td class="sfrAddr">0x01C</td>
</tr>
<tr id="CCP2CON">
<th class="sfrName">CCP2CON</th>
<td class="sfrAddr">0x01D</td>
</tr>
<tr id="ADRESH">
<th class="sfrName">ADRESH</th>
<td class="sfrAddr">0x01E</td>
</tr>
<tr id="ADCON0">
<th class="sfrName">ADCON0</th>
<td class="sfrAddr">0x01F</td>
</tr>
</table>
</td>
<td class="vMargin"></td>
<td class="sfrColumn">
<table>
<tr><th class="sfrSep"> </th></tr>
<tr id="OPTION_REG">
<th class="sfrName">OPTION_REG</th>
<td class="sfrAddr">0x081</td>
</tr>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr id="TRISA">
<th class="sfrName">TRISA</th>
<td class="sfrAddr">0x085</td>
</tr>
<tr id="TRISB">
<th class="sfrName">TRISB</th>
<td class="sfrAddr">0x086</td>
</tr>
<tr id="TRISC">
<th class="sfrName">TRISC</th>
<td class="sfrAddr">0x087</td>
</tr>
<tr id="TRISD">
<th class="sfrName">TRISD</th>
<td class="sfrAddr">0x088</td>
</tr>
<tr id="TRISE">
<th class="sfrName">TRISE</th>
<td class="sfrAddr">0x089</td>
</tr>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr id="PIE1">
<th class="sfrName">PIE1</th>
<td class="sfrAddr">0x08C</td>
</tr>
<tr id="PIE2">
<th class="sfrName">PIE2</th>
<td class="sfrAddr">0x08D</td>
</tr>
<tr id="PCON">
<th class="sfrName">PCON</th>
<td class="sfrAddr">0x08E</td>
</tr>
<tr id="OSCCON">
<th class="sfrName">OSCCON</th>
<td class="sfrAddr">0x08F</td>
</tr>
<tr id="OSCTUNE">
<th class="sfrName">OSCTUNE</th>
<td class="sfrAddr">0x090</td>
</tr>
<tr id="SSPCON2">
<th class="sfrName">SSPCON2</th>
<td class="sfrAddr">0x091</td>
</tr>
<tr id="PR2">
<th class="sfrName">PR2</th>
<td class="sfrAddr">0x092</td>
</tr>
<tr id="MSK">
<th class="sfrNameX">MSK<span>SSPADD<br>SSPMSK</span></th>
<td class="sfrAddr">0x093</td>
</tr>
<tr id="SSPSTAT">
<th class="sfrName">SSPSTAT</th>
<td class="sfrAddr">0x094</td>
</tr>
<tr id="WPUB">
<th class="sfrName">WPUB</th>
<td class="sfrAddr">0x095</td>
</tr>
<tr id="IOCB">
<th class="sfrName">IOCB</th>
<td class="sfrAddr">0x096</td>
</tr>
<tr id="VRCON">
<th class="sfrName">VRCON</th>
<td class="sfrAddr">0x097</td>
</tr>
<tr id="TXSTA">
<th class="sfrName">TXSTA</th>
<td class="sfrAddr">0x098</td>
</tr>
<tr id="SPBRG">
<th class="sfrName">SPBRG</th>
<td class="sfrAddr">0x099</td>
</tr>
<tr id="SPBRGH">
<th class="sfrName">SPBRGH</th>
<td class="sfrAddr">0x09A</td>
</tr>
<tr id="PWM1CON">
<th class="sfrName">PWM1CON</th>
<td class="sfrAddr">0x09B</td>
</tr>
<tr id="ECCPAS">
<th class="sfrName">ECCPAS</th>
<td class="sfrAddr">0x09C</td>
</tr>
<tr id="PSTRCON">
<th class="sfrName">PSTRCON</th>
<td class="sfrAddr">0x09D</td>
</tr>
<tr id="ADRESL">
<th class="sfrName">ADRESL</th>
<td class="sfrAddr">0x09E</td>
</tr>
<tr id="ADCON1">
<th class="sfrName">ADCON1</th>
<td class="sfrAddr">0x09F</td>
</tr>
</table>
</td>
<td class="vMargin"></td>
<td class="sfrColumn">
<table>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr id="WDTCON">
<th class="sfrName">WDTCON</th>
<td class="sfrAddr">0x105</td>
</tr>
<tr><th class="sfrSep"> </th></tr>
<tr id="CM1CON0">
<th class="sfrName">CM1CON0</th>
<td class="sfrAddr">0x107</td>
</tr>
<tr id="CM2CON0">
<th class="sfrName">CM2CON0</th>
<td class="sfrAddr">0x108</td>
</tr>
<tr id="CM2CON1">
<th class="sfrName">CM2CON1</th>
<td class="sfrAddr">0x109</td>
</tr>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr id="EEDAT">
<th class="sfrNameX">EEDAT<span>EEDATA</span></th>
<td class="sfrAddr">0x10C</td>
</tr>
<tr id="EEADR">
<th class="sfrName">EEADR</th>
<td class="sfrAddr">0x10D</td>
</tr>
<tr id="EEDATH">
<th class="sfrName">EEDATH</th>
<td class="sfrAddr">0x10E</td>
</tr>
<tr id="EEADRH">
<th class="sfrName">EEADRH</th>
<td class="sfrAddr">0x10F</td>
</tr>
</table>
</td>
<td class="vMargin"></td>
<td class="sfrColumn">
<table>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr id="SRCON">
<th class="sfrName">SRCON</th>
<td class="sfrAddr">0x185</td>
</tr>
<tr><th class="sfrSep"> </th></tr>
<tr id="BAUDCTL">
<th class="sfrName">BAUDCTL</th>
<td class="sfrAddr">0x187</td>
</tr>
<tr id="ANSEL">
<th class="sfrName">ANSEL</th>
<td class="sfrAddr">0x188</td>
</tr>
<tr id="ANSELH">
<th class="sfrName">ANSELH</th>
<td class="sfrAddr">0x189</td>
</tr>
<tr><th class="sfrSep"> </th></tr>
<tr><th class="sfrSep"> </th></tr>
<tr id="EECON1">
<th class="sfrName">EECON1</th>
<td class="sfrAddr">0x18C</td>
</tr>
<tr id="EECON2">
<th class="sfrName">EECON2</th>
<td class="sfrAddr">0x18D</td>
</tr>
</table>
</td>
<td class="vMargin"></td>
</tr>
<tr class="ramGap"><td></td></tr>
<tr><td colspan=9 class="ramSumEx">The mirror of [PCL, STATUS, ...] are not shown.</td></tr>
</table>
<div class="legendContainer">
<div class="legend">
<p class="sfrNameEx"> <span class="explanation">SFR</span></p>
<p class="sfrNameXEx"> <span class="explanation">SFR with alias name.</span></p>
</div>
</div>
<div class="legendContainer">
<p class="srcInfo">This page generated automatically by the <a href="https://sourceforge.net/p/gputils/code/HEAD/tree/trunk/scripts/tools/device-help.pl"><em>device-help.pl</em></a> program (2013-05-17 07:55:35 UTC) from the <em>8bit_device.info</em> file (rev: 1.13) of <em>mpasmx</em> and from the <a href="http://gputils.sourceforge.net#Download">gputils</a> source package (rev: svn 979:980). The <em>mpasmx</em> is included in the <a href="http://www.microchip.com/pagehandler/en-us/family/mplabx">MPLAB X</a>.</p>
</div>
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distrib
>
Mageia
>
5
>
x86_64
>
media
>
core-release
>
by-pkgid
>
ea0480943e5f9837b0cc4165bae8d1c3
>
files
>
884
