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<li><a href="PIC18LF13K22-feat.html">Features</a></li>
<li class="selected"><a href="PIC18LF13K22-conf.html">Configuration Bits</a></li>
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<table class="configList">
<tr><th colspan=5 class="confTableName">PIC18LF13K22</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG1H (address:0x300001, mask:0x27)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">FOSC -- Oscillator Selection bits</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = LP</td>
<td class="confSwValue">0xF0</td>
<td class="confSwExpl">LP oscillator.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = XT</td>
<td class="confSwValue">0xF1</td>
<td class="confSwExpl">XT oscillator.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = HS</td>
<td class="confSwValue">0xF2</td>
<td class="confSwExpl">HS oscillator.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = ERCCLKOUT</td>
<td class="confSwValue">0xF3</td>
<td class="confSwExpl">External RC oscillator, CLKOUT function on OSC2.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = ECCLKOUTH</td>
<td class="confSwValue">0xF4</td>
<td class="confSwExpl">EC, CLKOUT function on OSC2 (high).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = ECH</td>
<td class="confSwValue">0xF5</td>
<td class="confSwExpl">EC (high).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = ERC</td>
<td class="confSwValue">0xF7</td>
<td class="confSwExpl">External RC oscillator.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = IRC</td>
<td class="confSwValue">0xF8</td>
<td class="confSwExpl">Internal RC oscillator.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = IRCCLKOUT</td>
<td class="confSwValue">0xF9</td>
<td class="confSwExpl">Internal RC oscillator, CLKOUT function on OSC2.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = ECCLKOUTM</td>
<td class="confSwValue">0xFA</td>
<td class="confSwExpl">EC, CLKOUT function on OSC2 (medium).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = ECM</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">EC (medium).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = ECCLKOUTL</td>
<td class="confSwValue">0xFC</td>
<td class="confSwExpl">EC, CLKOUT function on OSC2 (low).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = ECL</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">EC (low).</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">PLLEN -- 4 X PLL Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PLLEN = OFF</td>
<td class="confSwValue">0xEF</td>
<td class="confSwExpl">PLL is under software control.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PLLEN = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Oscillator multiplied by 4.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">PCLKEN -- Primary Clock Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PCLKEN = OFF</td>
<td class="confSwValue">0xDF</td>
<td class="confSwExpl">Primary clock is under software control.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PCLKEN = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Primary clock enabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">FCMEN -- Fail-Safe Clock Monitor Enable</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FCMEN = OFF</td>
<td class="confSwValue">0xBF</td>
<td class="confSwExpl">Fail-Safe Clock Monitor disabled.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FCMEN = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Fail-Safe Clock Monitor enabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">IESO -- Internal/External Oscillator Switchover bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">IESO = OFF</td>
<td class="confSwValue">0x7F</td>
<td class="confSwExpl">Oscillator Switchover mode disabled.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">IESO = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Oscillator Switchover mode enabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG2L (address:0x300002, mask:0x1F)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">PWRTEN -- Power-up Timer Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PWRTEN = ON</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">PWRT enabled.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PWRTEN = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">PWRT disabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">BOREN -- Brown-out Reset Enable bits</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BOREN = OFF</td>
<td class="confSwValue">0xF9</td>
<td class="confSwExpl">Brown-out Reset disabled in hardware and software.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BOREN = ON</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">Brown-out Reset enabled and controlled by software (SBOREN is enabled).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BOREN = NOSLP</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BOREN = SBORDIS</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Brown-out Reset enabled in hardware only (SBOREN is disabled).</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">BORV -- Brown Out Reset Voltage bits</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BORV = 30</td>
<td class="confSwValue">0xE7</td>
<td class="confSwExpl">VBOR set to 3.0 V nominal.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BORV = 27</td>
<td class="confSwValue">0xEF</td>
<td class="confSwExpl">VBOR set to 2.7 V nominal.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BORV = 22</td>
<td class="confSwValue">0xF7</td>
<td class="confSwExpl">VBOR set to 2.2 V nominal.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BORV = 19</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">VBOR set to 1.9 V nominal.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG2H (address:0x300003, mask:0x1F)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WDTEN -- Watchdog Timer Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTEN = OFF</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">WDT is controlled by SWDTEN bit of the WDTCON register.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTEN = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">WDT is always enabled. SWDTEN bit has no effect.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WDTPS -- Watchdog Timer Postscale Select bits</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 1</td>
<td class="confSwValue">0xE1</td>
<td class="confSwExpl">1:1.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 2</td>
<td class="confSwValue">0xE3</td>
<td class="confSwExpl">1:2.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 4</td>
<td class="confSwValue">0xE5</td>
<td class="confSwExpl">1:4.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 8</td>
<td class="confSwValue">0xE7</td>
<td class="confSwExpl">1:8.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 16</td>
<td class="confSwValue">0xE9</td>
<td class="confSwExpl">1:16.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 32</td>
<td class="confSwValue">0xEB</td>
<td class="confSwExpl">1:32.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 64</td>
<td class="confSwValue">0xED</td>
<td class="confSwExpl">1:64.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 128</td>
<td class="confSwValue">0xEF</td>
<td class="confSwExpl">1:128.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 256</td>
<td class="confSwValue">0xF1</td>
<td class="confSwExpl">1:256.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 512</td>
<td class="confSwValue">0xF3</td>
<td class="confSwExpl">1:512.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 1024</td>
<td class="confSwValue">0xF5</td>
<td class="confSwExpl">1:1024.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 2048</td>
<td class="confSwValue">0xF7</td>
<td class="confSwExpl">1:2048.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 4096</td>
<td class="confSwValue">0xF9</td>
<td class="confSwExpl">1:4096.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 8192</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">1:8192.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 16384</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">1:16384.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 32768</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">1:32768.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG3H (address:0x300005, mask:0x88)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">HFOFST -- HFINTOSC Fast Start-up bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">HFOFST = OFF</td>
<td class="confSwValue">0xF7</td>
<td class="confSwExpl">The system clock is held off until the HFINTOSC is stable.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">HFOFST = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">MCLRE -- MCLR Pin Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">MCLRE = OFF</td>
<td class="confSwValue">0x7F</td>
<td class="confSwExpl">RA3 input pin enabled; MCLR disabled.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">MCLRE = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">MCLR pin enabled, RA3 input pin disabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG4L (address:0x300006, mask:0x85)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">STVREN -- Stack Full/Underflow Reset Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">STVREN = OFF</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">Stack full/underflow will not cause Reset.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">STVREN = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Stack full/underflow will cause Reset.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">LVP -- Single-Supply ICSP Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">LVP = OFF</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">Single-Supply ICSP disabled.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">LVP = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Single-Supply ICSP enabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">BBSIZ -- Boot Block Size Select bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BBSIZ = OFF</td>
<td class="confSwValue">0xF7</td>
<td class="confSwExpl">512W boot block size.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BBSIZ = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">1kW boot block size.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">XINST -- Extended Instruction Set Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">XINST = OFF</td>
<td class="confSwValue">0xBF</td>
<td class="confSwExpl">Instruction set extension and Indexed Addressing mode disabled (Legacy mode).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">XINST = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Instruction set extension and Indexed Addressing mode enabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">DEBUG -- Background Debugger Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">DEBUG = ON</td>
<td class="confSwValue">0x7F</td>
<td class="confSwExpl">Background debugger enabled, RA0 and RA1 are dedicated to In-Circuit Debug.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">DEBUG = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Background debugger disabled, RA0 and RA1 configured as general purpose I/O pins.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG5L (address:0x300008, mask:0x03)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">CP0 -- Code Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CP0 = ON</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">Block 0 code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CP0 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 0 not code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">CP1 -- Code Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CP1 = ON</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">Block 1 code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CP1 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 1 not code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG5H (address:0x300009, mask:0xC0)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">CPB -- Boot Block Code Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CPB = ON</td>
<td class="confSwValue">0xBF</td>
<td class="confSwExpl">Boot block code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CPB = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Boot block not code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">CPD -- Data EEPROM Code Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CPD = ON</td>
<td class="confSwValue">0x7F</td>
<td class="confSwExpl">Data EEPROM code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CPD = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Data EEPROM not code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG6L (address:0x30000A, mask:0x03)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WRT0 -- Write Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRT0 = ON</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">Block 0 write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRT0 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 0 not write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WRT1 -- Write Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRT1 = ON</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">Block 1 write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRT1 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 1 not write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG6H (address:0x30000B, mask:0xE0)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WRTC -- Configuration Register Write Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRTC = ON</td>
<td class="confSwValue">0xDF</td>
<td class="confSwExpl">Configuration registers write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRTC = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Configuration registers not write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WRTB -- Boot Block Write Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRTB = ON</td>
<td class="confSwValue">0xBF</td>
<td class="confSwExpl">Boot block write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRTB = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Boot block not write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WRTD -- Data EEPROM Write Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRTD = ON</td>
<td class="confSwValue">0x7F</td>
<td class="confSwExpl">Data EEPROM write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRTD = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Data EEPROM not write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG7L (address:0x30000C, mask:0x03)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">EBTR0 -- Table Read Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTR0 = ON</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">Block 0 protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTR0 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 0 not protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">EBTR1 -- Table Read Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTR1 = ON</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">Block 1 protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTR1 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 1 not protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG7H (address:0x30000D, mask:0x40)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">EBTRB -- Boot Block Table Read Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTRB = ON</td>
<td class="confSwValue">0xBF</td>
<td class="confSwExpl">Boot block protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTRB = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Boot block not protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
</table>
<div class="legendContainer">
<p class="srcInfo">This page generated automatically by the <a href="https://sourceforge.net/p/gputils/code/HEAD/tree/trunk/scripts/tools/device-help.pl"><em>device-help.pl</em></a> program (2013-05-17 07:55:39 UTC) from the <em>8bit_device.info</em> file (rev: 1.13) of <em>mpasmx</em> and from the <a href="http://gputils.sourceforge.net#Download">gputils</a> source package (rev: svn 979:980). The <em>mpasmx</em> is included in the <a href="http://www.microchip.com/pagehandler/en-us/family/mplabx">MPLAB X</a>.</p>
</div>
</body>
</html>
distrib
>
Mageia
>
5
>
x86_64
>
media
>
core-release
>
by-pkgid
>
ea0480943e5f9837b0cc4165bae8d1c3
>
files
>
2113
