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<table class="configList">
<tr><th colspan=5 class="confTableName">PIC18F4458</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG1L (address:0x300000, mask:0x00)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">PLLDIV -- PLL Prescaler Selection bits</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PLLDIV = 1</td>
<td class="confSwValue">0xF8</td>
<td class="confSwExpl">No prescale (4 MHz oscillator input drives PLL directly).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PLLDIV = 2</td>
<td class="confSwValue">0xF9</td>
<td class="confSwExpl">Divide by 2 (8 MHz oscillator input).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PLLDIV = 3</td>
<td class="confSwValue">0xFA</td>
<td class="confSwExpl">Divide by 3 (12 MHz oscillator input).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PLLDIV = 4</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">Divide by 4 (16 MHz oscillator input).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PLLDIV = 5</td>
<td class="confSwValue">0xFC</td>
<td class="confSwExpl">Divide by 5 (20 MHz oscillator input).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PLLDIV = 6</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">Divide by 6 (24 MHz oscillator input).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PLLDIV = 10</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">Divide by 10 (40 MHz oscillator input).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PLLDIV = 12</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Divide by 12 (48 MHz oscillator input).</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">CPUDIV -- System Clock Postscaler Selection bits</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CPUDIV = OSC1_PLL2</td>
<td class="confSwValue">0xE7</td>
<td class="confSwExpl">[Primary Oscillator Src: /1][96 MHz PLL Src: /2].</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CPUDIV = OSC2_PLL3</td>
<td class="confSwValue">0xEF</td>
<td class="confSwExpl">[Primary Oscillator Src: /2][96 MHz PLL Src: /3].</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CPUDIV = OSC3_PLL4</td>
<td class="confSwValue">0xF7</td>
<td class="confSwExpl">[Primary Oscillator Src: /3][96 MHz PLL Src: /4].</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CPUDIV = OSC4_PLL6</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">[Primary Oscillator Src: /4][96 MHz PLL Src: /6].</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">USBDIV -- USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">USBDIV = 1</td>
<td class="confSwValue">0xDF</td>
<td class="confSwExpl">USB clock source comes directly from the primary oscillator block with no postscale.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">USBDIV = 2</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">USB clock source comes from the 96 MHz PLL divided by 2.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG1H (address:0x300001, mask:0x05)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">FOSC -- Oscillator Selection bits</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = XT_XT</td>
<td class="confSwValue">0xF0</td>
<td class="confSwExpl">XT oscillator (XT).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = XTPLL_XT</td>
<td class="confSwValue">0xF2</td>
<td class="confSwExpl">XT oscillator, PLL enabled (XTPLL).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = ECIO_EC</td>
<td class="confSwValue">0xF4</td>
<td class="confSwExpl">EC oscillator, port function on RA6 (ECIO).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = EC_EC</td>
<td class="confSwValue">0xF5</td>
<td class="confSwExpl">EC oscillator, CLKO function on RA6 (EC).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = ECPLLIO_EC</td>
<td class="confSwValue">0xF6</td>
<td class="confSwExpl">EC oscillator, PLL enabled, port function on RA6 (ECPIO).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = ECPLL_EC</td>
<td class="confSwValue">0xF7</td>
<td class="confSwExpl">EC oscillator, PLL enabled, CLKO function on RA6 (ECPLL).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = INTOSCIO_EC</td>
<td class="confSwValue">0xF8</td>
<td class="confSwExpl">Internal oscillator, port function on RA6, EC used by USB (INTIO).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = INTOSC_EC</td>
<td class="confSwValue">0xF9</td>
<td class="confSwExpl">Internal oscillator, CLKO function on RA6, EC used by USB (INTCKO).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = INTOSC_XT</td>
<td class="confSwValue">0xFA</td>
<td class="confSwExpl">Internal oscillator, XT used by USB (INTXT).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = INTOSC_HS</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">Internal oscillator, HS oscillator used by USB (INTHS).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = HS</td>
<td class="confSwValue">0xFC</td>
<td class="confSwExpl">HS oscillator (HS).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FOSC = HSPLL_HS</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">HS oscillator, PLL enabled (HSPLL).</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">FCMEN -- Fail-Safe Clock Monitor Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FCMEN = OFF</td>
<td class="confSwValue">0xBF</td>
<td class="confSwExpl">Fail-Safe Clock Monitor disabled.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">FCMEN = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Fail-Safe Clock Monitor enabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">IESO -- Internal/External Oscillator Switchover bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">IESO = OFF</td>
<td class="confSwValue">0x7F</td>
<td class="confSwExpl">Oscillator Switchover mode disabled.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">IESO = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Oscillator Switchover mode enabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG2L (address:0x300002, mask:0x1F)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">PWRT -- Power-up Timer Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PWRT = ON</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">PWRT enabled.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PWRT = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">PWRT disabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">BOR -- Brown-out Reset Enable bits</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BOR = OFF</td>
<td class="confSwValue">0xF9</td>
<td class="confSwExpl">Brown-out Reset disabled in hardware and software.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BOR = SOFT</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">Brown-out Reset enabled and controlled by software (SBOREN is enabled).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BOR = ON_ACTIVE</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BOR = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Brown-out Reset enabled in hardware only (SBOREN is disabled).</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">BORV -- Brown-out Reset Voltage bits</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BORV = 0</td>
<td class="confSwValue">0xE7</td>
<td class="confSwExpl">Maximum setting.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BORV = 1</td>
<td class="confSwValue">0xEF</td>
<td class="confSwExpl"></td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BORV = 2</td>
<td class="confSwValue">0xF7</td>
<td class="confSwExpl"></td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">BORV = 3</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Minimum setting.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">VREGEN -- USB Voltage Regulator Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">VREGEN = OFF</td>
<td class="confSwValue">0xDF</td>
<td class="confSwExpl">USB voltage regulator disabled.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">VREGEN = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">USB voltage regulator enabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG2H (address:0x300003, mask:0x1F)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WDT -- Watchdog Timer Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDT = OFF</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">WDT disabled (control is placed on the SWDTEN bit).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDT = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">WDT enabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WDTPS -- Watchdog Timer Postscale Select bits</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 1</td>
<td class="confSwValue">0xE1</td>
<td class="confSwExpl">1:1.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 2</td>
<td class="confSwValue">0xE3</td>
<td class="confSwExpl">1:2.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 4</td>
<td class="confSwValue">0xE5</td>
<td class="confSwExpl">1:4.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 8</td>
<td class="confSwValue">0xE7</td>
<td class="confSwExpl">1:8.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 16</td>
<td class="confSwValue">0xE9</td>
<td class="confSwExpl">1:16.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 32</td>
<td class="confSwValue">0xEB</td>
<td class="confSwExpl">1:32.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 64</td>
<td class="confSwValue">0xED</td>
<td class="confSwExpl">1:64.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 128</td>
<td class="confSwValue">0xEF</td>
<td class="confSwExpl">1:128.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 256</td>
<td class="confSwValue">0xF1</td>
<td class="confSwExpl">1:256.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 512</td>
<td class="confSwValue">0xF3</td>
<td class="confSwExpl">1:512.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 1024</td>
<td class="confSwValue">0xF5</td>
<td class="confSwExpl">1:1024.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 2048</td>
<td class="confSwValue">0xF7</td>
<td class="confSwExpl">1:2048.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 4096</td>
<td class="confSwValue">0xF9</td>
<td class="confSwExpl">1:4096.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 8192</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">1:8192.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 16384</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">1:16384.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WDTPS = 32768</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">1:32768.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG3H (address:0x300005, mask:0x83)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">CCP2MX -- CCP2 MUX bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CCP2MX = OFF</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">CCP2 input/output is multiplexed with RB3.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CCP2MX = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">CCP2 input/output is multiplexed with RC1.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">PBADEN -- PORTB A/D Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PBADEN = OFF</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">PORTB<4:0> pins are configured as digital I/O on Reset.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">PBADEN = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">PORTB<4:0> pins are configured as analog input channels on Reset.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">LPT1OSC -- Low-Power Timer 1 Oscillator Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">LPT1OSC = OFF</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">Timer1 configured for higher power operation.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">LPT1OSC = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Timer1 configured for low-power operation.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">MCLRE -- MCLR Pin Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">MCLRE = OFF</td>
<td class="confSwValue">0x7F</td>
<td class="confSwExpl">RE3 input pin enabled; MCLR pin disabled.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">MCLRE = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">MCLR pin enabled; RE3 input pin disabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG4L (address:0x300006, mask:0x85)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">STVREN -- Stack Full/Underflow Reset Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">STVREN = OFF</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">Stack full/underflow will not cause Reset.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">STVREN = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Stack full/underflow will cause Reset.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">LVP -- Single-Supply ICSP Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">LVP = OFF</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">Single-Supply ICSP disabled.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">LVP = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Single-Supply ICSP enabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">ICPRT -- Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">ICPRT = OFF</td>
<td class="confSwValue">0xDF</td>
<td class="confSwExpl">ICPORT disabled.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">ICPRT = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">ICPORT enabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">XINST -- Extended Instruction Set Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">XINST = OFF</td>
<td class="confSwValue">0xBF</td>
<td class="confSwExpl">Instruction set extension and Indexed Addressing mode disabled (Legacy mode).</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">XINST = ON</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Instruction set extension and Indexed Addressing mode enabled.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">DEBUG -- Background Debugger Enable bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">DEBUG = ON</td>
<td class="confSwValue">0x7F</td>
<td class="confSwExpl">Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">DEBUG = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG5L (address:0x300008, mask:0x0F)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">CP0 -- Code Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CP0 = ON</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">Block 0 (000800-001FFFh) is code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CP0 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 0 (000800-001FFFh) is not code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">CP1 -- Code Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CP1 = ON</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">Block 1 (002000-003FFFh) is code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CP1 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 1 (002000-003FFFh) is not code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">CP2 -- Code Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CP2 = ON</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">Block 2 (004000-005FFFh) is code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CP2 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 2 (004000-005FFFh) is not code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG5H (address:0x300009, mask:0xC0)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">CPB -- Boot Block Code Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CPB = ON</td>
<td class="confSwValue">0xBF</td>
<td class="confSwExpl">Boot block (000000-0007FFh) is code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CPB = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Boot block (000000-0007FFh) is not code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">CPD -- Data EEPROM Code Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CPD = ON</td>
<td class="confSwValue">0x7F</td>
<td class="confSwExpl">Data EEPROM is code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">CPD = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Data EEPROM is not code-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG6L (address:0x30000A, mask:0x0F)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WRT0 -- Write Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRT0 = ON</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">Block 0 (000800-001FFFh) is write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRT0 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 0 (000800-001FFFh) is not write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WRT1 -- Write Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRT1 = ON</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">Block 1 (002000-003FFFh) is write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRT1 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 1 (002000-003FFFh) is not write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WRT2 -- Write Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRT2 = ON</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">Block 2 (004000-005FFFh) is write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRT2 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 2 (004000-005FFFh) is not write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG6H (address:0x30000B, mask:0xE0)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WRTC -- Configuration Register Write Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRTC = ON</td>
<td class="confSwValue">0xDF</td>
<td class="confSwExpl">Configuration registers (300000-3000FFh) are write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRTC = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Configuration registers (300000-3000FFh) are not write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WRTB -- Boot Block Write Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRTB = ON</td>
<td class="confSwValue">0xBF</td>
<td class="confSwExpl">Boot block (000000-0007FFh) is write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRTB = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Boot block (000000-0007FFh) is not write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">WRTD -- Data EEPROM Write Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRTD = ON</td>
<td class="confSwValue">0x7F</td>
<td class="confSwExpl">Data EEPROM is write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">WRTD = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Data EEPROM is not write-protected.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG7L (address:0x30000C, mask:0x0F)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">EBTR0 -- Table Read Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTR0 = ON</td>
<td class="confSwValue">0xFE</td>
<td class="confSwExpl">Block 0 (000800-001FFFh) is protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTR0 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">EBTR1 -- Table Read Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTR1 = ON</td>
<td class="confSwValue">0xFD</td>
<td class="confSwExpl">Block 1 (002000-003FFFh) is protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTR1 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">EBTR2 -- Table Read Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTR2 = ON</td>
<td class="confSwValue">0xFB</td>
<td class="confSwExpl">Block 2 (004000-005FFFh) is protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTR2 = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=4 class="configWord">CONFIG7H (address:0x30000D, mask:0x40)</th></tr>
<tr class="confGap"><td></td></tr>
<tr><th colspan=3 class="confOptName">EBTRB -- Boot Block Table Read Protection bit</th></tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTRB = ON</td>
<td class="confSwValue">0xBF</td>
<td class="confSwExpl">Boot block (000000-0007FFh) is protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
<tr>
<td class="vMargin"></td>
<td class="confSwName">EBTRB = OFF</td>
<td class="confSwValue">0xFF</td>
<td class="confSwExpl">Boot block (000000-0007FFh) is not protected from table reads executed in other blocks.</td>
<td class="vMargin"></td>
</tr>
</table>
<div class="legendContainer">
<p class="srcInfo">This page generated automatically by the <a href="https://sourceforge.net/p/gputils/code/HEAD/tree/trunk/scripts/tools/device-help.pl"><em>device-help.pl</em></a> program (2013-05-17 07:55:39 UTC) from the <em>8bit_device.info</em> file (rev: 1.13) of <em>mpasmx</em> and from the <a href="http://gputils.sourceforge.net#Download">gputils</a> source package (rev: svn 979:980). The <em>mpasmx</em> is included in the <a href="http://www.microchip.com/pagehandler/en-us/family/mplabx">MPLAB X</a>.</p>
</div>
</body>
</html>
distrib
>
Mageia
>
5
>
x86_64
>
media
>
core-release
>
by-pkgid
>
ea0480943e5f9837b0cc4165bae8d1c3
>
files
>
1481
