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distrib > Mageia > 5 > x86_64 > media > core-release > by-pkgid > ea0480943e5f9837b0cc4165bae8d1c3 > files > 125

gputils-1.2.0-4.mga5.x86_64.rpm

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    <title>PIC12F520</title>
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    <ul class="classMenu">
      <li><a href="index.html">All</a></li>
      <li><a href="enhanced-mcus.html">Enhanced</a></li>
      <li><a href="extended-mcus.html">Extended</a></li>
      <li><a href="regular-mcus.html">Regular</a></li>
      <li><a href="12-bits-mcus.html">12 bits</a></li>
      <li><a href="14-bits-mcus.html">14 bits</a></li>
      <li><a href="16-bits-mcus.html">16 bits</a></li>
      <li><a href="mcus-by-ram-size.html">by RAM size</a></li>
      <li><a href="mcus-by-rom-size.html">by ROM size</a></li>
      <li><a href="mcus-by-eeprom-size.html">by EEPROM size</a></li>
    </ul>
    <ul class="tabs">
      <li><a href="PIC12F520-feat.html">Features</a></li>
      <li class="selected"><a href="PIC12F520-conf.html">Configuration Bits</a></li>
      <li><a href="PIC12F520-ram.html">RAM map</a></li>
      <li><a href="PIC12F520-sfr.html">SFR map</a></li>
    </ul>
    <table class="configList">
      <tr><th colspan=5 class="confTableName">PIC12F520</th></tr>
      <tr class="confGap"><td></td></tr>
      <tr><th colspan=4 class="configWord">CONFIG (address:0x0FFF, mask:0xFFFF)</th></tr>
      <tr class="confGap"><td></td></tr>
      <tr><th colspan=3 class="confOptName">OSC -- Oscillator</th></tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">OSC = LP</td>
        <td class="confSwValue">0x0FFC</td>
        <td class="confSwExpl">LP Osc With 18 ms DRT.</td>
        <td class="vMargin"></td>
      </tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">OSC = XT</td>
        <td class="confSwValue">0x0FFD</td>
        <td class="confSwExpl">XT Osc With 18 ms DRT.</td>
        <td class="vMargin"></td>
      </tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">OSC = INTRC</td>
        <td class="confSwValue">0x0FFE</td>
        <td class="confSwExpl">INTRC With 1 ms DRT.</td>
        <td class="vMargin"></td>
      </tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">OSC = EXTRC</td>
        <td class="confSwValue">0x0FFF</td>
        <td class="confSwExpl">EXTRC With 1 ms DRT.</td>
        <td class="vMargin"></td>
      </tr>
      <tr class="confGap"><td></td></tr>
      <tr><th colspan=3 class="confOptName">WDT -- Watchdog Timer Enable</th></tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">WDT = OFF</td>
        <td class="confSwValue">0x0FFB</td>
        <td class="confSwExpl">WDT disabled.</td>
        <td class="vMargin"></td>
      </tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">WDT = ON</td>
        <td class="confSwValue">0x0FFF</td>
        <td class="confSwExpl">WDT enabled.</td>
        <td class="vMargin"></td>
      </tr>
      <tr class="confGap"><td></td></tr>
      <tr><th colspan=3 class="confOptName">CP -- Code Protect</th></tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">CP = ON</td>
        <td class="confSwValue">0x0FF7</td>
        <td class="confSwExpl">Code protection on.</td>
        <td class="vMargin"></td>
      </tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">CP = OFF</td>
        <td class="confSwValue">0x0FFF</td>
        <td class="confSwExpl">Code protection off.</td>
        <td class="vMargin"></td>
      </tr>
      <tr class="confGap"><td></td></tr>
      <tr><th colspan=3 class="confOptName">MCLR -- Master Clear Enable</th></tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">MCLR = OFF</td>
        <td class="confSwValue">0x0FEF</td>
        <td class="confSwExpl">RB3/MCLR Functions as RB3.</td>
        <td class="vMargin"></td>
      </tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">MCLR = ON</td>
        <td class="confSwValue">0x0FFF</td>
        <td class="confSwExpl">RB3/MCLR Functions as MCLR.</td>
        <td class="vMargin"></td>
      </tr>
      <tr class="confGap"><td></td></tr>
      <tr><th colspan=3 class="confOptName">IOSCFS -- Internal Oscillator Frequency Select</th></tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">IOSCFS = 4MHZ</td>
        <td class="confSwValue">0x0FDF</td>
        <td class="confSwExpl">4 MHz INTOSC Speed.</td>
        <td class="vMargin"></td>
      </tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">IOSCFS = 8MHZ</td>
        <td class="confSwValue">0x0FFF</td>
        <td class="confSwExpl">8 MHz INTOSC Speed.</td>
        <td class="vMargin"></td>
      </tr>
      <tr class="confGap"><td></td></tr>
      <tr><th colspan=3 class="confOptName">CPDF -- Code Protect bit - Self Writable Memory</th></tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">CPDF = ON</td>
        <td class="confSwValue">0x0FBF</td>
        <td class="confSwExpl">Code protection on.</td>
        <td class="vMargin"></td>
      </tr>
      <tr>
        <td class="vMargin"></td>
        <td class="confSwName">CPDF = OFF</td>
        <td class="confSwValue">0x0FFF</td>
        <td class="confSwExpl">Code protection off.</td>
        <td class="vMargin"></td>
      </tr>
    </table>
    <div class="legendContainer">
      <p class="srcInfo">This page generated automatically by the <a href="https://sourceforge.net/p/gputils/code/HEAD/tree/trunk/scripts/tools/device-help.pl"><em>device-help.pl</em></a> program (2013-05-17 07:55:34 UTC) from the <em>8bit_device.info</em> file (rev: 1.13) of <em>mpasmx</em> and from the <a href="http://gputils.sourceforge.net#Download">gputils</a> source package (rev: svn 979:980). The <em>mpasmx</em> is included in the <a href="http://www.microchip.com/pagehandler/en-us/family/mplabx">MPLAB X</a>.</p>
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