# KDE#305728 - Add support for AVX2, BMI1, BMI2 and FMA instructions
# Combined patch for:
# - valgrind-avx2-1.patch
# - valgrind-avx2-2.patch
# - valgrind-avx2-3.patch
# - valgrind-avx2-4.patch
# - valgrind-bmi-1.patch
# - valgrind-bmi-2.patch
# - valgrind-bmi-3.patch
# - valgrind-fma-1.patch
# - valgrind-memcheck-avx2-bmi-fma.patch
# - valgrind-vmaskmov-load.patch
# - valgrind-avx2-5.patch
# - valgrind-bmi-4.patch
# - valgrind-avx2-bmi-fma-tests.tar.bz2
#
# NOTE: Need to touch empty files from tar file:
# ./none/tests/amd64/avx2-1.stderr.exp
# ./none/tests/amd64/fma.stderr.exp
# ./none/tests/amd64/bmi.stderr.exp
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/configure valgrind-3.8.0.new/configure
--- valgrind-3.8.0.orig/configure 2012-09-12 17:37:34.433928694 +0200
+++ valgrind-3.8.0.new/configure 2012-09-12 20:20:29.868427602 +0200
@@ -636,6 +636,12 @@
BUILD_IFUNC_TESTS_TRUE
BUILD_MOVBE_TESTS_FALSE
BUILD_MOVBE_TESTS_TRUE
+BUILD_FMA_TESTS_FALSE
+BUILD_FMA_TESTS_TRUE
+BUILD_BMI_TESTS_FALSE
+BUILD_BMI_TESTS_TRUE
+BUILD_AVX2_TESTS_FALSE
+BUILD_AVX2_TESTS_TRUE
BUILD_AVX_TESTS_FALSE
BUILD_AVX_TESTS_TRUE
BUILD_SSE42_TESTS_FALSE
@@ -8319,6 +8325,155 @@
+# does the x86/amd64 assembler understand AVX2 instructions?
+# Note, this doesn't generate a C-level symbol. It generates a
+# automake-level symbol (BUILD_AVX2_TESTS), used in test Makefile.am's
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if x86/amd64 assembler speaks AVX2" >&5
+$as_echo_n "checking if x86/amd64 assembler speaks AVX2... " >&6; }
+
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ do { long long int x;
+ __asm__ __volatile__(
+ "vpsravd (%%rsp), %%ymm8, %%ymm7" : : : "xmm7", "xmm8" );
+ __asm__ __volatile__(
+ "vpaddb %%ymm6,%%ymm7,%%ymm8" : : : "xmm6","xmm7","xmm8"); }
+ while (0)
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+
+ac_have_as_avx2=yes
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+
+else
+
+ac_have_as_avx2=no
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
+ if test x$ac_have_as_avx2 = xyes; then
+ BUILD_AVX2_TESTS_TRUE=
+ BUILD_AVX2_TESTS_FALSE='#'
+else
+ BUILD_AVX2_TESTS_TRUE='#'
+ BUILD_AVX2_TESTS_FALSE=
+fi
+
+
+
+# does the x86/amd64 assembler understand BMI1 and BMI2 instructions?
+# Note, this doesn't generate a C-level symbol. It generates a
+# automake-level symbol (BUILD_BMI_TESTS), used in test Makefile.am's
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if x86/amd64 assembler speaks BMI1 and BMI2" >&5
+$as_echo_n "checking if x86/amd64 assembler speaks BMI1 and BMI2... " >&6; }
+
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ do { unsigned int h, l;
+ __asm__ __volatile__(
+ "andn %2, %1, %0" : "=r" (h) : "r" (0x1234567), "r" (0x7654321) ); }
+ __asm__ __volatile__(
+ "movl %2, %%edx; mulx %3, %1, %0" : "=r" (h), "=r" (l) : "g" (0x1234567), "g" (0x7654321) : "edx" ); }
+ while (0)
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+
+ac_have_as_bmi=yes
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+
+else
+
+ac_have_as_bmi=no
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
+ if test x$ac_have_as_bmi = xyes; then
+ BUILD_BMI_TESTS_TRUE=
+ BUILD_BMI_TESTS_FALSE='#'
+else
+ BUILD_BMI_TESTS_TRUE='#'
+ BUILD_BMI_TESTS_FALSE=
+fi
+
+
+
+# does the x86/amd64 assembler understand FMA instructions?
+# Note, this doesn't generate a C-level symbol. It generates a
+# automake-level symbol (BUILD_FMA_TESTS), used in test Makefile.am's
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if x86/amd64 assembler speaks FMA" >&5
+$as_echo_n "checking if x86/amd64 assembler speaks FMA... " >&6; }
+
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ do { unsigned int h, l;
+ __asm__ __volatile__(
+ "vfmadd132ps (%%rsp), %%ymm8, %%ymm7" : : : "xmm7", "xmm8" );
+ __asm__ __volatile__(
+ "vfnmsub231sd (%%rsp), %%xmm8, %%xmm7" : : : "xmm7", "xmm8" );
+ __asm__ __volatile__(
+ "vfmsubadd213pd (%%rsp), %%xmm8, %%xmm7" : : : "xmm7", "xmm8" ); }
+ while (0)
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+
+ac_have_as_fma=yes
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+
+else
+
+ac_have_as_fma=no
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
+ if test x$ac_have_as_fma = xyes; then
+ BUILD_FMA_TESTS_TRUE=
+ BUILD_FMA_TESTS_FALSE='#'
+else
+ BUILD_FMA_TESTS_TRUE='#'
+ BUILD_FMA_TESTS_FALSE=
+fi
+
+
+
# does the x86/amd64 assembler understand MOVBE?
# Note, this doesn't generate a C-level symbol. It generates a
# automake-level symbol (BUILD_MOVBE_TESTS), used in test Makefile.am's
@@ -8942,7 +9097,6 @@
main ()
{
char *data, *data2, *data3;
- const char *cdata2;
int i, pagesize;
int fd, fd2;
@@ -8967,10 +9121,10 @@
fd2 = open ("conftest.txt", O_RDWR | O_CREAT | O_TRUNC, 0600);
if (fd2 < 0)
return 4;
- cdata2 = "";
- if (write (fd2, cdata2, 1) != 1)
+ data2 = "";
+ if (write (fd2, data2, 1) != 1)
return 5;
- data2 = (char *) mmap (0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd2, 0L);
+ data2 = mmap (0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd2, 0L);
if (data2 == MAP_FAILED)
return 6;
for (i = 0; i < pagesize; ++i)
@@ -10182,6 +10336,18 @@
as_fn_error "conditional \"BUILD_AVX_TESTS\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
+if test -z "${BUILD_AVX2_TESTS_TRUE}" && test -z "${BUILD_AVX2_TESTS_FALSE}"; then
+ as_fn_error "conditional \"BUILD_AVX2_TESTS\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${BUILD_BMI_TESTS_TRUE}" && test -z "${BUILD_BMI_TESTS_FALSE}"; then
+ as_fn_error "conditional \"BUILD_BMI_TESTS\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${BUILD_FMA_TESTS_TRUE}" && test -z "${BUILD_FMA_TESTS_FALSE}"; then
+ as_fn_error "conditional \"BUILD_FMA_TESTS\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
if test -z "${BUILD_MOVBE_TESTS_TRUE}" && test -z "${BUILD_MOVBE_TESTS_FALSE}"; then
as_fn_error "conditional \"BUILD_MOVBE_TESTS\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/configure.in valgrind-3.8.0.new/configure.in
--- valgrind-3.8.0.orig/configure.in 2012-09-12 17:37:34.534930179 +0200
+++ valgrind-3.8.0.new/configure.in 2012-09-12 19:54:55.747334083 +0200
@@ -1791,6 +1791,77 @@
AM_CONDITIONAL(BUILD_AVX_TESTS, test x$ac_have_as_avx = xyes)
+# does the x86/amd64 assembler understand AVX2 instructions?
+# Note, this doesn't generate a C-level symbol. It generates a
+# automake-level symbol (BUILD_AVX2_TESTS), used in test Makefile.am's
+AC_MSG_CHECKING([if x86/amd64 assembler speaks AVX2])
+
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[
+ do { long long int x;
+ __asm__ __volatile__(
+ "vpsravd (%%rsp), %%ymm8, %%ymm7" : : : "xmm7", "xmm8" );
+ __asm__ __volatile__(
+ "vpaddb %%ymm6,%%ymm7,%%ymm8" : : : "xmm6","xmm7","xmm8"); }
+ while (0)
+]])], [
+ac_have_as_avx2=yes
+AC_MSG_RESULT([yes])
+], [
+ac_have_as_avx2=no
+AC_MSG_RESULT([no])
+])
+
+AM_CONDITIONAL(BUILD_AVX2_TESTS, test x$ac_have_as_avx2 = xyes)
+
+
+# does the x86/amd64 assembler understand BMI1 and BMI2 instructions?
+# Note, this doesn't generate a C-level symbol. It generates a
+# automake-level symbol (BUILD_BMI_TESTS), used in test Makefile.am's
+AC_MSG_CHECKING([if x86/amd64 assembler speaks BMI1 and BMI2])
+
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[
+ do { unsigned int h, l;
+ __asm__ __volatile__(
+ "andn %2, %1, %0" : "=r" (h) : "r" (0x1234567), "r" (0x7654321) ); }
+ __asm__ __volatile__(
+ "movl %2, %%edx; mulx %3, %1, %0" : "=r" (h), "=r" (l) : "g" (0x1234567), "g" (0x7654321) : "edx" ); }
+ while (0)
+]])], [
+ac_have_as_bmi=yes
+AC_MSG_RESULT([yes])
+], [
+ac_have_as_bmi=no
+AC_MSG_RESULT([no])
+])
+
+AM_CONDITIONAL(BUILD_BMI_TESTS, test x$ac_have_as_bmi = xyes)
+
+
+# does the x86/amd64 assembler understand FMA instructions?
+# Note, this doesn't generate a C-level symbol. It generates a
+# automake-level symbol (BUILD_FMA_TESTS), used in test Makefile.am's
+AC_MSG_CHECKING([if x86/amd64 assembler speaks FMA])
+
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[
+ do { unsigned int h, l;
+ __asm__ __volatile__(
+ "vfmadd132ps (%%rsp), %%ymm8, %%ymm7" : : : "xmm7", "xmm8" );
+ __asm__ __volatile__(
+ "vfnmsub231sd (%%rsp), %%xmm8, %%xmm7" : : : "xmm7", "xmm8" );
+ __asm__ __volatile__(
+ "vfmsubadd213pd (%%rsp), %%xmm8, %%xmm7" : : : "xmm7", "xmm8" ); }
+ while (0)
+]])], [
+ac_have_as_fma=yes
+AC_MSG_RESULT([yes])
+], [
+ac_have_as_fma=no
+AC_MSG_RESULT([no])
+])
+
+AM_CONDITIONAL(BUILD_FMA_TESTS, test x$ac_have_as_fma = xyes)
+
+
# does the x86/amd64 assembler understand MOVBE?
# Note, this doesn't generate a C-level symbol. It generates a
# automake-level symbol (BUILD_MOVBE_TESTS), used in test Makefile.am's
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/coregrind/m_machine.c valgrind-3.8.0.new/coregrind/m_machine.c
--- valgrind-3.8.0.orig/coregrind/m_machine.c 2012-09-12 17:37:34.447928901 +0200
+++ valgrind-3.8.0.new/coregrind/m_machine.c 2012-09-12 19:54:35.312026314 +0200
@@ -755,8 +755,8 @@
#elif defined(VGA_amd64)
{ Bool have_sse3, have_cx8, have_cx16;
- Bool have_lzcnt, have_avx /*, have_fma*/;
- UInt eax, ebx, ecx, edx, max_extended;
+ Bool have_lzcnt, have_avx, have_bmi, have_avx2;
+ UInt eax, ebx, ecx, edx, max_basic, max_extended;
UChar vstr[13];
vstr[0] = 0;
@@ -765,7 +765,8 @@
return False;
VG_(cpuid)(0, 0, &eax, &ebx, &ecx, &edx);
- if (eax < 1)
+ max_basic = eax;
+ if (max_basic < 1)
/* we can't ask for cpuid(x) for x > 0. Give up. */
return False;
@@ -822,19 +823,29 @@
/* on amd64 we tolerate older cpus, which don't have cmpxchg16b */
have_cx16 = (ecx & (1<<13)) != 0; /* True => have cmpxchg16b */
- /* Figure out if this is an AMD that can do LZCNT. */
+ /* Figure out if the CPU can do LZCNT. */
have_lzcnt = False;
- if (0 == VG_(strcmp)(vstr, "AuthenticAMD")
- && max_extended >= 0x80000001) {
+ if (max_extended >= 0x80000001) {
VG_(cpuid)(0x80000001, 0, &eax, &ebx, &ecx, &edx);
have_lzcnt = (ecx & (1<<5)) != 0; /* True => have LZCNT */
}
+ /* Check for BMI1 and AVX2. */
+ have_bmi = False;
+ have_avx2 = False;
+ if (max_basic >= 7) {
+ VG_(cpuid)(7, 0, &eax, &ebx, &ecx, &edx);
+ have_bmi = (ebx & (1<<3)) != 0; /* True => have BMI1 */
+ have_avx2 = have_avx && ((ebx & (1<<5)) != 0); /* True => have AVX2 */
+ }
+
va = VexArchAMD64;
vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0)
| (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0)
| (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0)
- | (have_avx ? VEX_HWCAPS_AMD64_AVX : 0);
+ | (have_avx ? VEX_HWCAPS_AMD64_AVX : 0)
+ | (have_bmi ? VEX_HWCAPS_AMD64_BMI : 0)
+ | (have_avx2 ? VEX_HWCAPS_AMD64_AVX2 : 0);
return True;
}
--- valgrind-3.8.0.orig/Makefile.vex.am 2012-09-12 17:37:34.431928664 +0200
+++ valgrind-3.8.0.new/Makefile.vex.am 2012-09-12 19:54:55.636332414 +0200
@@ -46,6 +46,8 @@
priv/host_generic_regs.h \
priv/host_generic_simd64.h \
priv/host_generic_simd128.h \
+ priv/host_generic_simd256.h \
+ priv/host_generic_maddf.h \
priv/host_x86_defs.h \
priv/host_amd64_defs.h \
priv/host_ppc_defs.h \
@@ -115,6 +117,8 @@
priv/host_generic_regs.c \
priv/host_generic_simd64.c \
priv/host_generic_simd128.c \
+ priv/host_generic_simd256.c \
+ priv/host_generic_maddf.c \
priv/host_generic_reg_alloc2.c \
priv/host_x86_defs.c \
priv/host_x86_isel.c \
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/Makefile.vex.in valgrind-3.8.0.new/Makefile.vex.in
--- valgrind-3.8.0.orig/Makefile.vex.in 2012-09-12 17:37:34.416928442 +0200
+++ valgrind-3.8.0.new/Makefile.vex.in 2012-09-13 13:24:01.844153871 +0200
@@ -113,6 +113,8 @@
libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT) \
libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT) \
libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.$(OBJEXT) \
+ libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.$(OBJEXT) \
+ libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.$(OBJEXT) \
libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.$(OBJEXT) \
libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_x86_defs.$(OBJEXT) \
libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_x86_isel.$(OBJEXT) \
@@ -143,7 +145,8 @@
priv/guest_s390_helpers.c priv/guest_s390_toIR.c \
priv/guest_mips_helpers.c priv/guest_mips_toIR.c \
priv/host_generic_regs.c priv/host_generic_simd64.c \
- priv/host_generic_simd128.c priv/host_generic_reg_alloc2.c \
+ priv/host_generic_simd128.c priv/host_generic_simd256.c \
+ priv/host_generic_maddf.c priv/host_generic_reg_alloc2.c \
priv/host_x86_defs.c priv/host_x86_isel.c \
priv/host_amd64_defs.c priv/host_amd64_isel.c \
priv/host_ppc_defs.c priv/host_ppc_isel.c priv/host_arm_defs.c \
@@ -174,6 +177,8 @@
libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT) \
libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT) \
libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.$(OBJEXT) \
+ libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.$(OBJEXT) \
+ libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.$(OBJEXT) \
libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.$(OBJEXT) \
libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_x86_defs.$(OBJEXT) \
libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_x86_isel.$(OBJEXT) \
@@ -513,6 +518,8 @@
priv/host_generic_regs.h \
priv/host_generic_simd64.h \
priv/host_generic_simd128.h \
+ priv/host_generic_simd256.h \
+ priv/host_generic_maddf.h \
priv/host_x86_defs.h \
priv/host_amd64_defs.h \
priv/host_ppc_defs.h \
@@ -553,6 +560,8 @@
priv/host_generic_regs.c \
priv/host_generic_simd64.c \
priv/host_generic_simd128.c \
+ priv/host_generic_simd256.c \
+ priv/host_generic_maddf.c \
priv/host_generic_reg_alloc2.c \
priv/host_x86_defs.c \
priv/host_x86_isel.c \
@@ -688,9 +697,11 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_amd64_isel.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_arm_defs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_arm_isel.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_regs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_defs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_isel.Po@am__quote@
@@ -725,9 +736,11 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_amd64_isel.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_arm_defs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_arm_isel.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_regs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_defs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_isel.Po@am__quote@
@@ -1081,6 +1094,34 @@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.obj `if test -f 'priv/host_generic_simd128.c'; then $(CYGPATH_W) 'priv/host_generic_simd128.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd128.c'; fi`
+libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.o: priv/host_generic_simd256.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.o -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.Tpo -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.o `test -f 'priv/host_generic_simd256.c' || echo '$(srcdir)/'`priv/host_generic_simd256.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='priv/host_generic_simd256.c' object='libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.o `test -f 'priv/host_generic_simd256.c' || echo '$(srcdir)/'`priv/host_generic_simd256.c
+
+libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.obj: priv/host_generic_simd256.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.obj -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.Tpo -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.obj `if test -f 'priv/host_generic_simd256.c'; then $(CYGPATH_W) 'priv/host_generic_simd256.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd256.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='priv/host_generic_simd256.c' object='libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.obj `if test -f 'priv/host_generic_simd256.c'; then $(CYGPATH_W) 'priv/host_generic_simd256.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd256.c'; fi`
+
+libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.o: priv/host_generic_maddf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.o -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.Tpo -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.o `test -f 'priv/host_generic_maddf.c' || echo '$(srcdir)/'`priv/host_generic_maddf.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='priv/host_generic_maddf.c' object='libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.o `test -f 'priv/host_generic_maddf.c' || echo '$(srcdir)/'`priv/host_generic_maddf.c
+
+libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.obj: priv/host_generic_maddf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.obj -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.Tpo -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.obj `if test -f 'priv/host_generic_maddf.c'; then $(CYGPATH_W) 'priv/host_generic_maddf.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_maddf.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='priv/host_generic_maddf.c' object='libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_maddf.obj `if test -f 'priv/host_generic_maddf.c'; then $(CYGPATH_W) 'priv/host_generic_maddf.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_maddf.c'; fi`
+
libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.o: priv/host_generic_reg_alloc2.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.o -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.Tpo -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.o `test -f 'priv/host_generic_reg_alloc2.c' || echo '$(srcdir)/'`priv/host_generic_reg_alloc2.c
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@@ -1599,6 +1640,34 @@
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+libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.o: priv/host_generic_simd256.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.o -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.Tpo -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.o `test -f 'priv/host_generic_simd256.c' || echo '$(srcdir)/'`priv/host_generic_simd256.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='priv/host_generic_simd256.c' object='libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.o' libtool=no @AMDEPBACKSLASH@
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+
+libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.obj: priv/host_generic_simd256.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.obj -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.Tpo -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.obj `if test -f 'priv/host_generic_simd256.c'; then $(CYGPATH_W) 'priv/host_generic_simd256.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd256.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='priv/host_generic_simd256.c' object='libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.obj `if test -f 'priv/host_generic_simd256.c'; then $(CYGPATH_W) 'priv/host_generic_simd256.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd256.c'; fi`
+
+libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.o: priv/host_generic_maddf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.o -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.Tpo -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.o `test -f 'priv/host_generic_maddf.c' || echo '$(srcdir)/'`priv/host_generic_maddf.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='priv/host_generic_maddf.c' object='libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.o `test -f 'priv/host_generic_maddf.c' || echo '$(srcdir)/'`priv/host_generic_maddf.c
+
+libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.obj: priv/host_generic_maddf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.obj -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.Tpo -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.obj `if test -f 'priv/host_generic_maddf.c'; then $(CYGPATH_W) 'priv/host_generic_maddf.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_maddf.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='priv/host_generic_maddf.c' object='libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_maddf.obj `if test -f 'priv/host_generic_maddf.c'; then $(CYGPATH_W) 'priv/host_generic_maddf.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_maddf.c'; fi`
+
libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.o: priv/host_generic_reg_alloc2.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.o -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.Tpo -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.o `test -f 'priv/host_generic_reg_alloc2.c' || echo '$(srcdir)/'`priv/host_generic_reg_alloc2.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.Po
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/memcheck/mc_translate.c valgrind-3.8.0.new/memcheck/mc_translate.c
--- valgrind-3.8.0.orig/memcheck/mc_translate.c 2012-09-12 17:37:34.474929295 +0200
+++ valgrind-3.8.0.new/memcheck/mc_translate.c 2012-09-12 19:55:08.913532373 +0200
@@ -576,6 +576,7 @@
case Ity_I64: return mkUifU64(mce, a1, a2);
case Ity_I128: return mkUifU128(mce, a1, a2);
case Ity_V128: return mkUifUV128(mce, a1, a2);
+ case Ity_V256: return mkUifUV256(mce, a1, a2);
default:
VG_(printf)("\n"); ppIRType(vty); VG_(printf)("\n");
VG_(tool_panic)("memcheck:mkUifU");
@@ -821,6 +822,13 @@
tmp1 = assignNew('V', mce, Ity_I64, unop(Iop_1Sto64, tmp1));
tmp1 = assignNew('V', mce, Ity_I128, binop(Iop_64HLto128, tmp1, tmp1));
return tmp1;
+ case Ity_V256:
+ tmp1 = assignNew('V', mce, Ity_I64, unop(Iop_1Sto64, tmp1));
+ tmp1 = assignNew('V', mce, Ity_V128, binop(Iop_64HLtoV128,
+ tmp1, tmp1));
+ tmp1 = assignNew('V', mce, Ity_V256, binop(Iop_V128HLtoV256,
+ tmp1, tmp1));
+ return tmp1;
default:
ppIRType(dst_ty);
VG_(tool_panic)("mkPCastTo(2)");
@@ -1880,11 +1888,21 @@
return assignNew('V', mce, Ity_I64, unop(Iop_CmpNEZ32x2, at));
}
+static IRAtom* mkPCast16x16 ( MCEnv* mce, IRAtom* at )
+{
+ return assignNew('V', mce, Ity_V256, unop(Iop_CmpNEZ16x16, at));
+}
+
static IRAtom* mkPCast16x4 ( MCEnv* mce, IRAtom* at )
{
return assignNew('V', mce, Ity_I64, unop(Iop_CmpNEZ16x4, at));
}
+static IRAtom* mkPCast8x32 ( MCEnv* mce, IRAtom* at )
+{
+ return assignNew('V', mce, Ity_V256, unop(Iop_CmpNEZ8x32, at));
+}
+
static IRAtom* mkPCast8x8 ( MCEnv* mce, IRAtom* at )
{
return assignNew('V', mce, Ity_I64, unop(Iop_CmpNEZ8x8, at));
@@ -2289,6 +2307,44 @@
/* Simple ... UifU the args and per-lane pessimise the results. */
+/* --- V256-bit versions --- */
+
+static
+IRAtom* binary8Ix32 ( MCEnv* mce, IRAtom* vatom1, IRAtom* vatom2 )
+{
+ IRAtom* at;
+ at = mkUifUV256(mce, vatom1, vatom2);
+ at = mkPCast8x32(mce, at);
+ return at;
+}
+
+static
+IRAtom* binary16Ix16 ( MCEnv* mce, IRAtom* vatom1, IRAtom* vatom2 )
+{
+ IRAtom* at;
+ at = mkUifUV256(mce, vatom1, vatom2);
+ at = mkPCast16x16(mce, at);
+ return at;
+}
+
+static
+IRAtom* binary32Ix8 ( MCEnv* mce, IRAtom* vatom1, IRAtom* vatom2 )
+{
+ IRAtom* at;
+ at = mkUifUV256(mce, vatom1, vatom2);
+ at = mkPCast32x8(mce, at);
+ return at;
+}
+
+static
+IRAtom* binary64Ix4 ( MCEnv* mce, IRAtom* vatom1, IRAtom* vatom2 )
+{
+ IRAtom* at;
+ at = mkUifUV256(mce, vatom1, vatom2);
+ at = mkPCast64x4(mce, at);
+ return at;
+}
+
/* --- V128-bit versions --- */
static
@@ -3522,6 +3578,82 @@
case Iop_XorV256:
return mkUifUV256(mce, vatom1, vatom2);
+ /* V256-bit SIMD */
+
+ case Iop_ShrN16x16:
+ case Iop_ShrN32x8:
+ case Iop_ShrN64x4:
+ case Iop_SarN16x16:
+ case Iop_SarN32x8:
+ case Iop_ShlN16x16:
+ case Iop_ShlN32x8:
+ case Iop_ShlN64x4:
+ /* Same scheme as with all other shifts. Note: 22 Oct 05:
+ this is wrong now, scalar shifts are done properly lazily.
+ Vector shifts should be fixed too. */
+ complainIfUndefined(mce, atom2, NULL);
+ return assignNew('V', mce, Ity_V256, binop(op, vatom1, atom2));
+
+ case Iop_QSub8Ux32:
+ case Iop_QSub8Sx32:
+ case Iop_Sub8x32:
+ case Iop_Min8Ux32:
+ case Iop_Min8Sx32:
+ case Iop_Max8Ux32:
+ case Iop_Max8Sx32:
+ case Iop_CmpGT8Sx32:
+ case Iop_CmpEQ8x32:
+ case Iop_Avg8Ux32:
+ case Iop_QAdd8Ux32:
+ case Iop_QAdd8Sx32:
+ case Iop_Add8x32:
+ return binary8Ix32(mce, vatom1, vatom2);
+
+ case Iop_QSub16Ux16:
+ case Iop_QSub16Sx16:
+ case Iop_Sub16x16:
+ case Iop_Mul16x16:
+ case Iop_MulHi16Sx16:
+ case Iop_MulHi16Ux16:
+ case Iop_Min16Sx16:
+ case Iop_Min16Ux16:
+ case Iop_Max16Sx16:
+ case Iop_Max16Ux16:
+ case Iop_CmpGT16Sx16:
+ case Iop_CmpEQ16x16:
+ case Iop_Avg16Ux16:
+ case Iop_QAdd16Ux16:
+ case Iop_QAdd16Sx16:
+ case Iop_Add16x16:
+ return binary16Ix16(mce, vatom1, vatom2);
+
+ case Iop_Sub32x8:
+ case Iop_CmpGT32Sx8:
+ case Iop_CmpEQ32x8:
+ case Iop_Add32x8:
+ case Iop_Max32Ux8:
+ case Iop_Max32Sx8:
+ case Iop_Min32Ux8:
+ case Iop_Min32Sx8:
+ case Iop_Mul32x8:
+ return binary32Ix8(mce, vatom1, vatom2);
+
+ case Iop_Sub64x4:
+ case Iop_Add64x4:
+ case Iop_CmpEQ64x4:
+ case Iop_CmpGT64Sx4:
+ return binary64Ix4(mce, vatom1, vatom2);
+
+ /* Perm32x8: rearrange values in left arg using steering values
+ from right arg. So rearrange the vbits in the same way but
+ pessimise wrt steering values. */
+ case Iop_Perm32x8:
+ return mkUifUV256(
+ mce,
+ assignNew('V', mce, Ity_V256, binop(op, vatom1, atom2)),
+ mkPCast32x8(mce, vatom2)
+ );
+
default:
ppIROp(op);
VG_(tool_panic)("memcheck:expr2vbits_Binop");
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/avx-1.c valgrind-3.8.0.new/none/tests/amd64/avx-1.c
--- valgrind-3.8.0.orig/none/tests/amd64/avx-1.c 2012-09-12 17:37:34.545930341 +0200
+++ valgrind-3.8.0.new/none/tests/amd64/avx-1.c 2012-09-12 20:27:57.310151656 +0200
@@ -2129,6 +2129,26 @@
"vcmpss $0x9, %%xmm6, %%xmm8, %%xmm7",
"vcmpss $0x9, (%%rax), %%xmm8, %%xmm7")
+GEN_test_Monly(VMASKMOVPS_128_LoadForm,
+ "vmaskmovps (%%rax), %%xmm8, %%xmm7;"
+ "vxorps %%xmm6, %%xmm6, %%xmm6;"
+ "vmaskmovps (%%rax,%%rax,4), %%xmm6, %%xmm9")
+
+GEN_test_Monly(VMASKMOVPS_256_LoadForm,
+ "vmaskmovps (%%rax), %%ymm8, %%ymm7;"
+ "vxorps %%ymm6, %%ymm6, %%ymm6;"
+ "vmaskmovps (%%rax,%%rax,4), %%ymm6, %%ymm9")
+
+GEN_test_Monly(VMASKMOVPD_128_LoadForm,
+ "vmaskmovpd (%%rax), %%xmm8, %%xmm7;"
+ "vxorpd %%xmm6, %%xmm6, %%xmm6;"
+ "vmaskmovpd (%%rax,%%rax,4), %%xmm6, %%xmm9")
+
+GEN_test_Monly(VMASKMOVPD_256_LoadForm,
+ "vmaskmovpd (%%rax), %%ymm8, %%ymm7;"
+ "vxorpd %%ymm6, %%ymm6, %%ymm6;"
+ "vmaskmovpd (%%rax,%%rax,4), %%ymm6, %%ymm9")
+
/* Comment duplicated above, for convenient reference:
Allowed operands in test insns:
Reg form: %ymm6, %ymm7, %ymm8, %ymm9 and %r14.
@@ -2669,6 +2689,10 @@
DO_D( VPCLMULQDQ_0x11 );
DO_D( VPCLMULQDQ_0xFF );
DO_D( VCMPSS_128_0x9 );
+ DO_D( VMASKMOVPS_128_LoadForm );
+ DO_D( VMASKMOVPS_256_LoadForm );
+ DO_D( VMASKMOVPD_128_LoadForm );
+ DO_D( VMASKMOVPD_256_LoadForm );
return 0;
}
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/avx-1.stdout.exp valgrind-3.8.0.new/none/tests/amd64/avx-1.stdout.exp
--- valgrind-3.8.0.orig/none/tests/amd64/avx-1.stdout.exp 2012-09-12 17:37:34.541930280 +0200
+++ valgrind-3.8.0.new/none/tests/amd64/avx-1.stdout.exp 2012-09-12 20:27:57.362152436 +0200
@@ -42793,3 +42793,327 @@
feb443c176d0cbb9.03548618f3c01756.212ac3ccd86b0351.95adf830a94ebc85
b165299dda543e63
+VMASKMOVPS_128_LoadForm(reg)
+ before
+ 9c0849d369c6ac28.280114a7abbea487.9b988f7ca02be891.5cd9546656fb9ec4
+ b0e1543ff2324180.15e28197e333466f.6f2dc520380802cb.2cf683d3894be479
+ 4a3e464b12243b18.a122067d3a3a6d9b.da5e256e59e6a2ad.6d4dcc018d67919e
+ c6691c656427d49c.a88f1f46cedfd437.3a79a9d49f4e03e6.fbaaacda7f5c615c
+ b2d99e4c7a350fe2
+ after
+ 9c0849d369c6ac28.280114a7abbea487.9b988f7ca02be891.5cd9546656fb9ec4
+ b0e1543ff2324180.15e28197e333466f.6f2dc520380802cb.2cf683d3894be479
+ 4a3e464b12243b18.a122067d3a3a6d9b.da5e256e59e6a2ad.6d4dcc018d67919e
+ c6691c656427d49c.a88f1f46cedfd437.3a79a9d49f4e03e6.fbaaacda7f5c615c
+ b2d99e4c7a350fe2
+VMASKMOVPS_128_LoadForm(mem)
+ before
+ 6ea61e429bfe585a.80afd1f885c748b7.06f348dcb82e3871.eac84fbca5ce631f
+ 0bdca8a8fdc3f8f0.d45c616f1090d516.971bfe2c16345572.4598129408f1fc07
+ 6549b86abd91aad1.1ebcc838a20fb564.37d3bc2304fde769.a935eec763440a48
+ 58b7cb74f6742b29.ba1a03bed6cf244e.c2e7feac9d93a980.70eadfc15252cb8f
+ f805e2ee72a77987
+ after
+ 6ea61e429bfe585a.80afd1f885c748b7.06f348dcb82e3871.eac84fbca5ce631f
+ 0bdca8a8fdc3f8f0.d45c616f1090d516.971bfe2c16345572.4598129408f1fc07
+ 0000000000000000.0000000000000000.06f348dc00000000.0000000000000000
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ f805e2ee72a77987
+
+VMASKMOVPS_128_LoadForm(reg)
+ before
+ 9bd0f2ba5ed051dd.c0f35cb3c5763723.04c40c6e495c6080.142340b2fd0458e3
+ b7990b92b3588e3c.79c9e71145a589ec.5804e1b29643a3a5.0852fe23415cb0bf
+ a6aa29e00dcb6e51.5e05e87c930ddfb0.12277df75a0f2a69.7c41b5ea84a56c40
+ c550481106b62bc8.4d72dcdecab8f39a.8e79dda9304d317a.4bbce0f3e3ed4991
+ 518ffb2a794003df
+ after
+ 9bd0f2ba5ed051dd.c0f35cb3c5763723.04c40c6e495c6080.142340b2fd0458e3
+ b7990b92b3588e3c.79c9e71145a589ec.5804e1b29643a3a5.0852fe23415cb0bf
+ a6aa29e00dcb6e51.5e05e87c930ddfb0.12277df75a0f2a69.7c41b5ea84a56c40
+ c550481106b62bc8.4d72dcdecab8f39a.8e79dda9304d317a.4bbce0f3e3ed4991
+ 518ffb2a794003df
+VMASKMOVPS_128_LoadForm(mem)
+ before
+ 6986837b63a85556.71d665923da4014c.21de3e2506b581d7.2846fb35b488f382
+ 716df2d3bc33fd21.048a7bce4b212e8a.b5138a3b640d4792.3bdad506834cad2d
+ 4310c61ca1edb56d.dbb68630cfbaec2e.e7de3c0e00cefff8.2580668739259b28
+ bd3a7a432de13965.52a8822662fa78e3.920bd089f5036635.4186aa2671a0f91f
+ eb369e4ec74802be
+ after
+ 6986837b63a85556.71d665923da4014c.21de3e2506b581d7.2846fb35b488f382
+ 716df2d3bc33fd21.048a7bce4b212e8a.b5138a3b640d4792.3bdad506834cad2d
+ 0000000000000000.0000000000000000.21de3e2500000000.00000000b488f382
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ eb369e4ec74802be
+
+VMASKMOVPS_128_LoadForm(reg)
+ before
+ 7edd3c6bd8aaf3af.bab88a357d1b4736.c5aa6c1ba26d0e55.9166c3985fb83774
+ 58c782e93f5107a1.155673ddaca7990b.91093f7b2ba0e931.c2ba90275bfa30e1
+ d3406b3499c97c3e.ace0af26d792ec12.1011f7b2981e4623.ffd5b32304d40baa
+ 4d93f4b8819f8c33.5922bcfe19e7fb74.9f0d902c867361d7.2681a876775284f9
+ 118beb0dcf8159fa
+ after
+ 7edd3c6bd8aaf3af.bab88a357d1b4736.c5aa6c1ba26d0e55.9166c3985fb83774
+ 58c782e93f5107a1.155673ddaca7990b.91093f7b2ba0e931.c2ba90275bfa30e1
+ d3406b3499c97c3e.ace0af26d792ec12.1011f7b2981e4623.ffd5b32304d40baa
+ 4d93f4b8819f8c33.5922bcfe19e7fb74.9f0d902c867361d7.2681a876775284f9
+ 118beb0dcf8159fa
+VMASKMOVPS_128_LoadForm(mem)
+ before
+ 9ebff9d5296c44da.210e17e2945d742b.fae715508eb2845f.9a4b0656902c75f8
+ a7e94db8a02002c5.aafbd21c6d926fd3.69fd3708530041ff.5d15569a52d4bf32
+ 09d563a451a84ee6.46a720d4a9c7bbd6.832e9c1284dcee80.44b87b6569f87b32
+ a14fb8845710e66a.4f5efd74e38a92e1.2547c25b3c53490d.ab8071247122e5a4
+ eeb9344205e13834
+ after
+ 9ebff9d5296c44da.210e17e2945d742b.fae715508eb2845f.9a4b0656902c75f8
+ a7e94db8a02002c5.aafbd21c6d926fd3.69fd3708530041ff.5d15569a52d4bf32
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ eeb9344205e13834
+
+VMASKMOVPS_256_LoadForm(reg)
+ before
+ 69afc12ac1beb18d.4922c644cf64847c.226c666ab86730a0.291424cd97700cd3
+ 78ae124a42478c5b.de1b0bd0d4b1e449.1c1c5521c3e8d3be.6c613e55b23ff4fd
+ 7601250d2307054b.3c0602148202c4fd.97bcc805a19bb5e8.cafa8ce0a8ccbdb8
+ c1f5f6df018a5709.40af27fcf664dec3.f196ba82ed0c13ca.20aa8b589624222f
+ 483fb6ab9752e08f
+ after
+ 69afc12ac1beb18d.4922c644cf64847c.226c666ab86730a0.291424cd97700cd3
+ 78ae124a42478c5b.de1b0bd0d4b1e449.1c1c5521c3e8d3be.6c613e55b23ff4fd
+ 7601250d2307054b.3c0602148202c4fd.97bcc805a19bb5e8.cafa8ce0a8ccbdb8
+ c1f5f6df018a5709.40af27fcf664dec3.f196ba82ed0c13ca.20aa8b589624222f
+ 483fb6ab9752e08f
+VMASKMOVPS_256_LoadForm(mem)
+ before
+ 1f8389c4c863b304.b4d67f2c775dbf40.c4e2f7744ce2efc8.84f7270443c5290f
+ 8143808f446256b9.abf0be61220b799d.a56bec689f88b337.ad2b0cf740543263
+ 4a4b18f8285b86db.018fade89d21c0cc.bf1584c50b63e53d.c87e64c780456b74
+ 5666cceb8f5bff95.14ff4a2e852ad178.eead3a75ad7d4206.313c2be19e2210eb
+ 45b15daf36795c77
+ after
+ 1f8389c4c863b304.b4d67f2c775dbf40.c4e2f7744ce2efc8.84f7270443c5290f
+ 8143808f446256b9.abf0be61220b799d.a56bec689f88b337.ad2b0cf740543263
+ 1f8389c400000000.b4d67f2c00000000.c4e2f7744ce2efc8.84f7270400000000
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 45b15daf36795c77
+
+VMASKMOVPS_256_LoadForm(reg)
+ before
+ 5e28f69fe5d68cc2.81621854966d7d14.3f8b91a075b2e84e.0eff8b66a1e586bd
+ d9eef31b46c3dc79.a709781f589dbb84.dd807ca9094641f9.fbd7f18302a46c8f
+ 124f4f91f6ce8847.a4296839f1f87610.4c2b09b4de711726.9101eab7ecc8b1a7
+ 6597066c9083cbd9.548c658c7e896ae5.e6d6332f90bfa780.ac49f1f07c5d1132
+ 287a8219cd6d485c
+ after
+ 5e28f69fe5d68cc2.81621854966d7d14.3f8b91a075b2e84e.0eff8b66a1e586bd
+ d9eef31b46c3dc79.a709781f589dbb84.dd807ca9094641f9.fbd7f18302a46c8f
+ 124f4f91f6ce8847.a4296839f1f87610.4c2b09b4de711726.9101eab7ecc8b1a7
+ 6597066c9083cbd9.548c658c7e896ae5.e6d6332f90bfa780.ac49f1f07c5d1132
+ 287a8219cd6d485c
+VMASKMOVPS_256_LoadForm(mem)
+ before
+ e1621a1efc061150.2e121418b16de2da.93ffea061b5c532e.09cef685babc2db5
+ b3cb33ec24332a3b.c90c7501f41809f7.3d4d7391e37dec18.105e4e22f8f5e46e
+ 79824b6d61014c48.92d02693f6107cdb.2e447c1bf2f9f2ce.56d43872e7f60959
+ 1153dd8ed17b36a4.e5ab223a52e27634.41af818f65dc217e.387aafe12349d822
+ 139dafdb477c8d75
+ after
+ e1621a1efc061150.2e121418b16de2da.93ffea061b5c532e.09cef685babc2db5
+ b3cb33ec24332a3b.c90c7501f41809f7.3d4d7391e37dec18.105e4e22f8f5e46e
+ e1621a1e00000000.2e121418b16de2da.000000001b5c532e.00000000babc2db5
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 139dafdb477c8d75
+
+VMASKMOVPS_256_LoadForm(reg)
+ before
+ 418934cdef1a63fd.560a663c8dada27b.1eea6562a41934ab.5459ffd957303451
+ 208a3a21b8b09767.24726061b3a44df8.99d7eb788a42f1ef.420f71e5e503e876
+ 0aecbe453dc9655e.565949eb5f6bf348.b1beb1e69de7ebaa.e79d539f2b61f917
+ 5cfbbba31bf1088f.ca899cc5ac0f4f96.c4edb21a7b975c88.1ecf21f343552260
+ c57158cd4ceb217e
+ after
+ 418934cdef1a63fd.560a663c8dada27b.1eea6562a41934ab.5459ffd957303451
+ 208a3a21b8b09767.24726061b3a44df8.99d7eb788a42f1ef.420f71e5e503e876
+ 0aecbe453dc9655e.565949eb5f6bf348.b1beb1e69de7ebaa.e79d539f2b61f917
+ 5cfbbba31bf1088f.ca899cc5ac0f4f96.c4edb21a7b975c88.1ecf21f343552260
+ c57158cd4ceb217e
+VMASKMOVPS_256_LoadForm(mem)
+ before
+ b74e731a5f2fb09d.72022da9edb5bda5.5bcfd5dab69a1e0f.2dafea7fc0db8136
+ cf33eec49a2e8be8.a94e10c250a0c04d.e4f771189a1a1cde.484f558007419560
+ ebed45b919f3708c.5b2c615adf3f4d33.43cdea6a749b0530.701aef8bec54d6b1
+ e546f4e3f78a19b5.e5e61bdd361c9f02.521cbebc5f279431.035cb50b0ca17ed6
+ 5c61a26c02b3c97b
+ after
+ b74e731a5f2fb09d.72022da9edb5bda5.5bcfd5dab69a1e0f.2dafea7fc0db8136
+ cf33eec49a2e8be8.a94e10c250a0c04d.e4f771189a1a1cde.484f558007419560
+ b74e731a5f2fb09d.72022da900000000.5bcfd5dab69a1e0f.0000000000000000
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 5c61a26c02b3c97b
+
+VMASKMOVPD_128_LoadForm(reg)
+ before
+ d675b21a6b16f54b.9b0b78305100438e.a3c83ab7f3c5f367.efb268fb77cd860c
+ cfe3e182e2563cf3.e7074c8b4260a943.f120ba54afc6850d.f4596411d99697ee
+ a1f92c0e0400db1e.a708ece0e6b70902.2b39972008a990a1.3fde2feba0908203
+ aa018e2b6ca00d79.b5d8d41b5a0f1df5.ad5ece889afd52cf.aa0d4476e9c60476
+ 13b21e9ccf44d973
+ after
+ d675b21a6b16f54b.9b0b78305100438e.a3c83ab7f3c5f367.efb268fb77cd860c
+ cfe3e182e2563cf3.e7074c8b4260a943.f120ba54afc6850d.f4596411d99697ee
+ a1f92c0e0400db1e.a708ece0e6b70902.2b39972008a990a1.3fde2feba0908203
+ aa018e2b6ca00d79.b5d8d41b5a0f1df5.ad5ece889afd52cf.aa0d4476e9c60476
+ 13b21e9ccf44d973
+VMASKMOVPD_128_LoadForm(mem)
+ before
+ 54993c4b6f17bd28.44480346b7c00faf.ee458128ba77a148.d3dc5af6004b0542
+ 4a8e176ee44a6bbf.cd1a87ca80ee1d6d.2f196ef321f85328.f9ff37d8d621e5a7
+ d15c2df14aeaa064.9fc3162264b5735f.52211768aba0edc1.7b136199b90a30a9
+ c6d0f8c0bf021844.188fadbcfea24d30.3429f874757a2c3e.b564d5a4449220f5
+ 033d8e671446f237
+ after
+ 54993c4b6f17bd28.44480346b7c00faf.ee458128ba77a148.d3dc5af6004b0542
+ 4a8e176ee44a6bbf.cd1a87ca80ee1d6d.2f196ef321f85328.f9ff37d8d621e5a7
+ 0000000000000000.0000000000000000.0000000000000000.d3dc5af6004b0542
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 033d8e671446f237
+
+VMASKMOVPD_128_LoadForm(reg)
+ before
+ c1ec884dc4b1e11a.03b6f6c75c9e8e8b.92c94703eb40e68d.b1fc8d019a93cccc
+ 4abbbfc2f1602a4b.65daa3f23fcac064.6abfe063c61b7b22.a66853fd37f58896
+ fcf72f3237de0975.c808792d849367fc.fdbb74482bc0479a.ed37c55367af1dc9
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+ after
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+ 32ecd50a30b7ba45.080cf6644605427e.a50a001eb7ba88a1.63365fee47ca4791
+ e4319dbcf254c119
+VMASKMOVPD_128_LoadForm(mem)
+ before
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+ ccd3a93208c0c5b5
+ after
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+ 774bf69e1be3981b.9930b09db1ab8085.90c4d277b2107ff3.a7d0ec4eb2de530f
+ 0000000000000000.0000000000000000.01b19584a12a0b17.bff87e52069578e5
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ ccd3a93208c0c5b5
+
+VMASKMOVPD_128_LoadForm(reg)
+ before
+ 8450ac8a4736a837.22be68f50a21940f.8eeda30cf873ab8c.508916823ebc34cd
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+ ed3f7cc3315308ad
+ after
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+ b85dc8a3f2c1ce00.9814c7d709c80f10.8f329de37ff9ddae.3cdb5b321adb592f
+ ed3f7cc3315308ad
+VMASKMOVPD_128_LoadForm(mem)
+ before
+ 13711b87deec42cd.003c201883247797.28c698e3c74f6c1a.94036e563da4798c
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+ after
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+ 0000000000000000.0000000000000000.0000000000000000.94036e563da4798c
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 5a250d91490be365
+
+VMASKMOVPD_256_LoadForm(reg)
+ before
+ 8362f7581d4fa8cf.6c34341197824418.1b9747f866a7c332.5d0b8b73bce2cfae
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+ df557fbe1da7e818.1743f1072092b3e8.2f78e03b7c421201.0aed0077fdd18b2d
+ c18d42a5e8dbbdcb
+ after
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+ df557fbe1da7e818.1743f1072092b3e8.2f78e03b7c421201.0aed0077fdd18b2d
+ c18d42a5e8dbbdcb
+VMASKMOVPD_256_LoadForm(mem)
+ before
+ fc81e09c952b7942.d00d36f9fb706c70.d494f19c68ddb24d.d65e2129f1c08905
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+ 3194afab236ecc13
+ after
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+ fc81e09c952b7942.0000000000000000.d494f19c68ddb24d.0000000000000000
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 3194afab236ecc13
+
+VMASKMOVPD_256_LoadForm(reg)
+ before
+ 0244209a54032171.3488a3cf1f1b6e04.9c86094b61878cab.4c91522951fe8c6b
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+ d42d56b850e5d173
+ after
+ 0244209a54032171.3488a3cf1f1b6e04.9c86094b61878cab.4c91522951fe8c6b
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+ 2b36f07ffdb28959.194afaece6fd3da3.27deddec1b7fc609.7ebdf4526ce70bc9
+ d42d56b850e5d173
+VMASKMOVPD_256_LoadForm(mem)
+ before
+ 3af673fea6d09dac.fc7aa73bf064967e.5b8dea649f30ae0f.e8cd6e4f4d93077f
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+ after
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+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ b4e16805c295deec
+
+VMASKMOVPD_256_LoadForm(reg)
+ before
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+ after
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+ ffc2f56cbe8d10f3.113b49d997039d3f.fdc58e1ba7fa7793.2efec0b9c2b5eaa1
+ 788f01b287cb1101
+VMASKMOVPD_256_LoadForm(mem)
+ before
+ e101db21ecf33d26.a70509244c6b15af.ef83a85068000f1d.0e6f0eb05e273285
+ 451ec9f20c39293c.c4b0c2727e545b40.9a511cf3a7562314.251df5652b59d036
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+ 272eef853089597e
+ after
+ e101db21ecf33d26.a70509244c6b15af.ef83a85068000f1d.0e6f0eb05e273285
+ 451ec9f20c39293c.c4b0c2727e545b40.9a511cf3a7562314.251df5652b59d036
+ 0000000000000000.a70509244c6b15af.ef83a85068000f1d.0000000000000000
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 272eef853089597e
+
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/avx2-1.c valgrind-3.8.0.new/none/tests/amd64/avx2-1.c
--- valgrind-3.8.0.orig/none/tests/amd64/avx2-1.c 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/none/tests/amd64/avx2-1.c 2012-09-12 20:28:05.911280911 +0200
@@ -0,0 +1,1467 @@
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <malloc.h>
+
+typedef unsigned char UChar;
+typedef unsigned int UInt;
+typedef unsigned long int UWord;
+typedef unsigned long long int ULong;
+
+UChar randArray[1027] __attribute__((used));
+
+#define IS_32_ALIGNED(_ptr) (0 == (0x1F & (UWord)(_ptr)))
+
+typedef union { UChar u8[32]; UInt u32[8]; } YMM;
+
+typedef struct { YMM a1; YMM a2; YMM a3; YMM a4; ULong u64; } Block;
+
+void showYMM ( YMM* vec )
+{
+ int i;
+ assert(IS_32_ALIGNED(vec));
+ for (i = 31; i >= 0; i--) {
+ printf("%02x", (UInt)vec->u8[i]);
+ if (i > 0 && 0 == ((i+0) & 7)) printf(".");
+ }
+}
+
+void showBlock ( char* msg, Block* block )
+{
+ printf(" %s\n", msg);
+ printf(" "); showYMM(&block->a1); printf("\n");
+ printf(" "); showYMM(&block->a2); printf("\n");
+ printf(" "); showYMM(&block->a3); printf("\n");
+ printf(" "); showYMM(&block->a4); printf("\n");
+ printf(" %016llx\n", block->u64);
+}
+
+UChar randUChar ( void )
+{
+ static UInt seed = 80021;
+ seed = 1103515245 * seed + 12345;
+ return (seed >> 17) & 0xFF;
+}
+
+void randBlock ( Block* b )
+{
+ int i;
+ UChar* p = (UChar*)b;
+ for (i = 0; i < sizeof(Block); i++)
+ p[i] = randUChar();
+}
+
+
+/* Generate a function test_NAME, that tests the given insn, in both
+ its mem and reg forms. The reg form of the insn may mention, as
+ operands only %ymm6, %ymm7, %ymm8, %ymm9 and %r14. The mem form of
+ the insn may mention as operands only (%rax), %ymm7, %ymm8, %ymm9
+ and %r14. It's OK for the insn to clobber ymm0, as this is needed
+ for testing PCMPxSTRx. */
+
+#define GEN_test_RandM(_name, _reg_form, _mem_form) \
+ \
+ __attribute__ ((noinline)) static void test_##_name ( void ) \
+ { \
+ Block* b = memalign(32, sizeof(Block)); \
+ randBlock(b); \
+ printf("%s(reg)\n", #_name); \
+ showBlock("before", b); \
+ __asm__ __volatile__( \
+ "vmovdqa 0(%0),%%ymm7" "\n\t" \
+ "vmovdqa 32(%0),%%ymm8" "\n\t" \
+ "vmovdqa 64(%0),%%ymm6" "\n\t" \
+ "vmovdqa 96(%0),%%ymm9" "\n\t" \
+ "movq 128(%0),%%r14" "\n\t" \
+ _reg_form "\n\t" \
+ "vmovdqa %%ymm7, 0(%0)" "\n\t" \
+ "vmovdqa %%ymm8, 32(%0)" "\n\t" \
+ "vmovdqa %%ymm6, 64(%0)" "\n\t" \
+ "vmovdqa %%ymm9, 96(%0)" "\n\t" \
+ "movq %%r14, 128(%0)" "\n\t" \
+ : /*OUT*/ \
+ : /*IN*/"r"(b) \
+ : /*TRASH*/"xmm0","xmm7","xmm8","xmm6","xmm9","r14","memory","cc" \
+ ); \
+ showBlock("after", b); \
+ randBlock(b); \
+ printf("%s(mem)\n", #_name); \
+ showBlock("before", b); \
+ __asm__ __volatile__( \
+ "leaq 0(%0),%%rax" "\n\t" \
+ "vmovdqa 32(%0),%%ymm8" "\n\t" \
+ "vmovdqa 64(%0),%%ymm7" "\n\t" \
+ "vmovdqa 96(%0),%%ymm9" "\n\t" \
+ "movq 128(%0),%%r14" "\n\t" \
+ _mem_form "\n\t" \
+ "vmovdqa %%ymm8, 32(%0)" "\n\t" \
+ "vmovdqa %%ymm7, 64(%0)" "\n\t" \
+ "vmovdqa %%ymm9, 96(%0)" "\n\t" \
+ "movq %%r14, 128(%0)" "\n\t" \
+ : /*OUT*/ \
+ : /*IN*/"r"(b) \
+ : /*TRASH*/"xmm0","xmm8","xmm7","xmm9","r14","rax","memory","cc" \
+ ); \
+ showBlock("after", b); \
+ printf("\n"); \
+ free(b); \
+ }
+
+#define GEN_test_Ronly(_name, _reg_form) \
+ GEN_test_RandM(_name, _reg_form, "")
+#define GEN_test_Monly(_name, _mem_form) \
+ GEN_test_RandM(_name, "", _mem_form)
+
+/* Vector integers promoved from 128-bit in AVX to 256-bit in AVX2. */
+
+GEN_test_RandM(VPOR_256,
+ "vpor %%ymm6, %%ymm8, %%ymm7",
+ "vpor (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPXOR_256,
+ "vpxor %%ymm6, %%ymm8, %%ymm7",
+ "vpxor (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSUBB_256,
+ "vpsubb %%ymm6, %%ymm8, %%ymm7",
+ "vpsubb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSUBD_256,
+ "vpsubd %%ymm6, %%ymm8, %%ymm7",
+ "vpsubd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPADDD_256,
+ "vpaddd %%ymm6, %%ymm8, %%ymm7",
+ "vpaddd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMOVZXWD_256,
+ "vpmovzxwd %%xmm6, %%ymm8",
+ "vpmovzxwd (%%rax), %%ymm8")
+
+GEN_test_RandM(VPMOVZXBW_256,
+ "vpmovzxbw %%xmm6, %%ymm8",
+ "vpmovzxbw (%%rax), %%ymm8")
+
+GEN_test_RandM(VPBLENDVB_256,
+ "vpblendvb %%ymm9, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendvb %%ymm9, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMINSD_256,
+ "vpminsd %%ymm6, %%ymm8, %%ymm7",
+ "vpminsd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMAXSD_256,
+ "vpmaxsd %%ymm6, %%ymm8, %%ymm7",
+ "vpmaxsd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSHUFB_256,
+ "vpshufb %%ymm6, %%ymm8, %%ymm7",
+ "vpshufb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPUNPCKLBW_256,
+ "vpunpcklbw %%ymm6, %%ymm8, %%ymm7",
+ "vpunpcklbw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPUNPCKHBW_256,
+ "vpunpckhbw %%ymm6, %%ymm8, %%ymm7",
+ "vpunpckhbw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPABSD_256,
+ "vpabsd %%ymm6, %%ymm8",
+ "vpabsd (%%rax), %%ymm8")
+
+GEN_test_RandM(VPACKUSWB_256,
+ "vpackuswb %%ymm9, %%ymm8, %%ymm7",
+ "vpackuswb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_Ronly(VPMOVMSKB_256,
+ "vpmovmskb %%ymm8, %%r14")
+
+GEN_test_RandM(VPAND_256,
+ "vpand %%ymm9, %%ymm8, %%ymm7",
+ "vpand (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPCMPEQB_256,
+ "vpcmpeqb %%ymm9, %%ymm8, %%ymm7",
+ "vpcmpeqb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSHUFLW_0x39_256,
+ "vpshuflw $0x39, %%ymm9, %%ymm7",
+ "vpshuflw $0xC6, (%%rax), %%ymm8")
+
+GEN_test_RandM(VPSHUFHW_0x39_256,
+ "vpshufhw $0x39, %%ymm9, %%ymm7",
+ "vpshufhw $0xC6, (%%rax), %%ymm8")
+
+GEN_test_RandM(VPMULLW_256,
+ "vpmullw %%ymm9, %%ymm8, %%ymm7",
+ "vpmullw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPADDUSW_256,
+ "vpaddusw %%ymm9, %%ymm8, %%ymm7",
+ "vpaddusw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMULHUW_256,
+ "vpmulhuw %%ymm9, %%ymm8, %%ymm7",
+ "vpmulhuw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPADDUSB_256,
+ "vpaddusb %%ymm9, %%ymm8, %%ymm7",
+ "vpaddusb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPUNPCKLWD_256,
+ "vpunpcklwd %%ymm6, %%ymm8, %%ymm7",
+ "vpunpcklwd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPUNPCKHWD_256,
+ "vpunpckhwd %%ymm6, %%ymm8, %%ymm7",
+ "vpunpckhwd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_Ronly(VPSLLD_0x05_256,
+ "vpslld $0x5, %%ymm9, %%ymm7")
+
+GEN_test_Ronly(VPSRLD_0x05_256,
+ "vpsrld $0x5, %%ymm9, %%ymm7")
+
+GEN_test_Ronly(VPSRAD_0x05_256,
+ "vpsrad $0x5, %%ymm9, %%ymm7")
+
+GEN_test_RandM(VPSUBUSB_256,
+ "vpsubusb %%ymm9, %%ymm8, %%ymm7",
+ "vpsubusb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSUBSB_256,
+ "vpsubsb %%ymm9, %%ymm8, %%ymm7",
+ "vpsubsb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_Ronly(VPSRLDQ_0x05_256,
+ "vpsrldq $0x5, %%ymm9, %%ymm7")
+
+GEN_test_Ronly(VPSLLDQ_0x05_256,
+ "vpslldq $0x5, %%ymm9, %%ymm7")
+
+GEN_test_RandM(VPANDN_256,
+ "vpandn %%ymm9, %%ymm8, %%ymm7",
+ "vpandn (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPUNPCKLQDQ_256,
+ "vpunpcklqdq %%ymm6, %%ymm8, %%ymm7",
+ "vpunpcklqdq (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_Ronly(VPSRLW_0x05_256,
+ "vpsrlw $0x5, %%ymm9, %%ymm7")
+
+GEN_test_Ronly(VPSLLW_0x05_256,
+ "vpsllw $0x5, %%ymm9, %%ymm7")
+
+GEN_test_RandM(VPADDW_256,
+ "vpaddw %%ymm6, %%ymm8, %%ymm7",
+ "vpaddw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPACKSSDW_256,
+ "vpackssdw %%ymm9, %%ymm8, %%ymm7",
+ "vpackssdw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPUNPCKLDQ_256,
+ "vpunpckldq %%ymm6, %%ymm8, %%ymm7",
+ "vpunpckldq (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPCMPEQD_256,
+ "vpcmpeqd %%ymm6, %%ymm8, %%ymm7",
+ "vpcmpeqd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSHUFD_0x39_256,
+ "vpshufd $0x39, %%ymm9, %%ymm8",
+ "vpshufd $0xC6, (%%rax), %%ymm7")
+
+GEN_test_RandM(VPADDQ_256,
+ "vpaddq %%ymm6, %%ymm8, %%ymm7",
+ "vpaddq (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSUBQ_256,
+ "vpsubq %%ymm6, %%ymm8, %%ymm7",
+ "vpsubq (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSUBW_256,
+ "vpsubw %%ymm6, %%ymm8, %%ymm7",
+ "vpsubw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPCMPEQQ_256,
+ "vpcmpeqq %%ymm6, %%ymm8, %%ymm7",
+ "vpcmpeqq (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPCMPGTQ_256,
+ "vpcmpgtq %%ymm6, %%ymm8, %%ymm7",
+ "vpcmpgtq (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_Ronly(VPSRLQ_0x05_256,
+ "vpsrlq $0x5, %%ymm9, %%ymm7")
+
+GEN_test_RandM(VPMULUDQ_256,
+ "vpmuludq %%ymm6, %%ymm8, %%ymm7",
+ "vpmuludq (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMULDQ_256,
+ "vpmuldq %%ymm6, %%ymm8, %%ymm7",
+ "vpmuldq (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_Ronly(VPSLLQ_0x05_256,
+ "vpsllq $0x5, %%ymm9, %%ymm7")
+
+GEN_test_RandM(VPMAXUD_256,
+ "vpmaxud %%ymm6, %%ymm8, %%ymm7",
+ "vpmaxud (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMINUD_256,
+ "vpminud %%ymm6, %%ymm8, %%ymm7",
+ "vpminud (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMULLD_256,
+ "vpmulld %%ymm6, %%ymm8, %%ymm7",
+ "vpmulld (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMAXUW_256,
+ "vpmaxuw %%ymm6, %%ymm8, %%ymm7",
+ "vpmaxuw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMINUW_256,
+ "vpminuw %%ymm6, %%ymm8, %%ymm7",
+ "vpminuw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMAXSW_256,
+ "vpmaxsw %%ymm6, %%ymm8, %%ymm7",
+ "vpmaxsw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMINSW_256,
+ "vpminsw %%ymm6, %%ymm8, %%ymm7",
+ "vpminsw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMAXUB_256,
+ "vpmaxub %%ymm6, %%ymm8, %%ymm7",
+ "vpmaxub (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMINUB_256,
+ "vpminub %%ymm6, %%ymm8, %%ymm7",
+ "vpminub (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMAXSB_256,
+ "vpmaxsb %%ymm6, %%ymm8, %%ymm7",
+ "vpmaxsb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMINSB_256,
+ "vpminsb %%ymm6, %%ymm8, %%ymm7",
+ "vpminsb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMOVSXBW_256,
+ "vpmovsxbw %%xmm6, %%ymm8",
+ "vpmovsxbw (%%rax), %%ymm8")
+
+GEN_test_RandM(VPSUBUSW_256,
+ "vpsubusw %%ymm9, %%ymm8, %%ymm7",
+ "vpsubusw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSUBSW_256,
+ "vpsubsw %%ymm9, %%ymm8, %%ymm7",
+ "vpsubsw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPCMPEQW_256,
+ "vpcmpeqw %%ymm6, %%ymm8, %%ymm7",
+ "vpcmpeqw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPADDB_256,
+ "vpaddb %%ymm6, %%ymm8, %%ymm7",
+ "vpaddb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPUNPCKHDQ_256,
+ "vpunpckhdq %%ymm6, %%ymm8, %%ymm7",
+ "vpunpckhdq (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMOVSXDQ_256,
+ "vpmovsxdq %%xmm6, %%ymm8",
+ "vpmovsxdq (%%rax), %%ymm8")
+
+GEN_test_RandM(VPMOVSXWD_256,
+ "vpmovsxwd %%xmm6, %%ymm8",
+ "vpmovsxwd (%%rax), %%ymm8")
+
+GEN_test_RandM(VPMULHW_256,
+ "vpmulhw %%ymm9, %%ymm8, %%ymm7",
+ "vpmulhw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPUNPCKHQDQ_256,
+ "vpunpckhqdq %%ymm6, %%ymm8, %%ymm7",
+ "vpunpckhqdq (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_Ronly(VPSRAW_0x05_256,
+ "vpsraw $0x5, %%ymm9, %%ymm7")
+
+GEN_test_RandM(VPCMPGTB_256,
+ "vpcmpgtb %%ymm6, %%ymm8, %%ymm7",
+ "vpcmpgtb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPCMPGTW_256,
+ "vpcmpgtw %%ymm6, %%ymm8, %%ymm7",
+ "vpcmpgtw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPCMPGTD_256,
+ "vpcmpgtd %%ymm6, %%ymm8, %%ymm7",
+ "vpcmpgtd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMOVZXBD_256,
+ "vpmovzxbd %%xmm6, %%ymm8",
+ "vpmovzxbd (%%rax), %%ymm8")
+
+GEN_test_RandM(VPMOVSXBD_256,
+ "vpmovsxbd %%xmm6, %%ymm8",
+ "vpmovsxbd (%%rax), %%ymm8")
+
+GEN_test_RandM(VPALIGNR_256_1of3,
+ "vpalignr $0, %%ymm6, %%ymm8, %%ymm7",
+ "vpalignr $3, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPALIGNR_256_2of3,
+ "vpalignr $6, %%ymm6, %%ymm8, %%ymm7",
+ "vpalignr $9, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPALIGNR_256_3of3,
+ "vpalignr $12, %%ymm6, %%ymm8, %%ymm7",
+ "vpalignr $15, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPBLENDW_256_0x00,
+ "vpblendw $0x00, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendw $0x01, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDW_256_0xFE,
+ "vpblendw $0xFE, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendw $0xFF, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDW_256_0x30,
+ "vpblendw $0x30, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendw $0x03, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDW_256_0x21,
+ "vpblendw $0x21, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendw $0x12, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDW_256_0xD7,
+ "vpblendw $0xD7, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendw $0x6C, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDW_256_0xB5,
+ "vpblendw $0xB5, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendw $0x4A, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDW_256_0x85,
+ "vpblendw $0x85, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendw $0xDC, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDW_256_0x29,
+ "vpblendw $0x29, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendw $0x92, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSLLW_256,
+ "andl $15, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsllw %%xmm6, %%ymm8, %%ymm9",
+ "andq $15, 128(%%rax);"
+ "vpsllw 128(%%rax), %%ymm8, %%ymm9")
+
+GEN_test_RandM(VPSRLW_256,
+ "andl $15, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsrlw %%xmm6, %%ymm8, %%ymm9",
+ "andq $15, 128(%%rax);"
+ "vpsrlw 128(%%rax), %%ymm8, %%ymm9")
+
+GEN_test_RandM(VPSRAW_256,
+ "andl $31, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsraw %%xmm6, %%ymm8, %%ymm9",
+ "andq $15, 128(%%rax);"
+ "vpsraw 128(%%rax), %%ymm8, %%ymm9")
+
+GEN_test_RandM(VPSLLD_256,
+ "andl $31, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpslld %%xmm6, %%ymm8, %%ymm9",
+ "andq $31, 128(%%rax);"
+ "vpslld 128(%%rax), %%ymm8, %%ymm9")
+
+GEN_test_RandM(VPSRLD_256,
+ "andl $31, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsrld %%xmm6, %%ymm8, %%ymm9",
+ "andq $31, 128(%%rax);"
+ "vpsrld 128(%%rax), %%ymm8, %%ymm9")
+
+GEN_test_RandM(VPSRAD_256,
+ "andl $31, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsrad %%xmm6, %%ymm8, %%ymm9",
+ "andq $31, 128(%%rax);"
+ "vpsrad 128(%%rax), %%ymm8, %%ymm9")
+
+GEN_test_RandM(VPSLLQ_256,
+ "andl $63, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsllq %%xmm6, %%ymm8, %%ymm9",
+ "andq $63, 128(%%rax);"
+ "vpsllq 128(%%rax), %%ymm8, %%ymm9")
+
+GEN_test_RandM(VPSRLQ_256,
+ "andl $63, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsrlq %%xmm6, %%ymm8, %%ymm9",
+ "andq $63, 128(%%rax);"
+ "vpsrlq 128(%%rax), %%ymm8, %%ymm9")
+
+GEN_test_RandM(VPMADDWD_256,
+ "vpmaddwd %%ymm6, %%ymm8, %%ymm7",
+ "vpmaddwd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_Monly(VMOVNTDQA_256,
+ "vmovntdqa (%%rax), %%ymm9")
+
+GEN_test_RandM(VPACKSSWB_256,
+ "vpacksswb %%ymm6, %%ymm8, %%ymm7",
+ "vpacksswb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPAVGB_256,
+ "vpavgb %%ymm6, %%ymm8, %%ymm7",
+ "vpavgb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPAVGW_256,
+ "vpavgw %%ymm6, %%ymm8, %%ymm7",
+ "vpavgw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPADDSB_256,
+ "vpaddsb %%ymm6, %%ymm8, %%ymm7",
+ "vpaddsb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPADDSW_256,
+ "vpaddsw %%ymm6, %%ymm8, %%ymm7",
+ "vpaddsw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPHADDW_256,
+ "vphaddw %%ymm6, %%ymm8, %%ymm7",
+ "vphaddw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPHADDD_256,
+ "vphaddd %%ymm6, %%ymm8, %%ymm7",
+ "vphaddd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPHADDSW_256,
+ "vphaddsw %%ymm6, %%ymm8, %%ymm7",
+ "vphaddsw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMADDUBSW_256,
+ "vpmaddubsw %%ymm6, %%ymm8, %%ymm7",
+ "vpmaddubsw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPHSUBW_256,
+ "vphsubw %%ymm6, %%ymm8, %%ymm7",
+ "vphsubw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPHSUBD_256,
+ "vphsubd %%ymm6, %%ymm8, %%ymm7",
+ "vphsubd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPHSUBSW_256,
+ "vphsubsw %%ymm6, %%ymm8, %%ymm7",
+ "vphsubsw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPABSB_256,
+ "vpabsb %%ymm6, %%ymm7",
+ "vpabsb (%%rax), %%ymm7")
+
+GEN_test_RandM(VPABSW_256,
+ "vpabsw %%ymm6, %%ymm7",
+ "vpabsw (%%rax), %%ymm7")
+
+GEN_test_RandM(VPMOVSXBQ_256,
+ "vpmovsxbq %%xmm6, %%ymm8",
+ "vpmovsxbq (%%rax), %%ymm8")
+
+GEN_test_RandM(VPMOVSXWQ_256,
+ "vpmovsxwq %%xmm6, %%ymm8",
+ "vpmovsxwq (%%rax), %%ymm8")
+
+GEN_test_RandM(VPACKUSDW_256,
+ "vpackusdw %%ymm6, %%ymm8, %%ymm7",
+ "vpackusdw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMOVZXBQ_256,
+ "vpmovzxbq %%xmm6, %%ymm8",
+ "vpmovzxbq (%%rax), %%ymm8")
+
+GEN_test_RandM(VPMOVZXWQ_256,
+ "vpmovzxwq %%xmm6, %%ymm8",
+ "vpmovzxwq (%%rax), %%ymm8")
+
+GEN_test_RandM(VPMOVZXDQ_256,
+ "vpmovzxdq %%xmm6, %%ymm8",
+ "vpmovzxdq (%%rax), %%ymm8")
+
+GEN_test_RandM(VMPSADBW_256_0x0,
+ "vmpsadbw $0, %%ymm6, %%ymm8, %%ymm7",
+ "vmpsadbw $0, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VMPSADBW_256_0x39,
+ "vmpsadbw $0x39, %%ymm6, %%ymm8, %%ymm7",
+ "vmpsadbw $0x39, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VMPSADBW_256_0x32,
+ "vmpsadbw $0x32, %%ymm6, %%ymm8, %%ymm7",
+ "vmpsadbw $0x32, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VMPSADBW_256_0x2b,
+ "vmpsadbw $0x2b, %%ymm6, %%ymm8, %%ymm7",
+ "vmpsadbw $0x2b, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VMPSADBW_256_0x24,
+ "vmpsadbw $0x24, %%ymm6, %%ymm8, %%ymm7",
+ "vmpsadbw $0x24, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VMPSADBW_256_0x1d,
+ "vmpsadbw $0x1d, %%ymm6, %%ymm8, %%ymm7",
+ "vmpsadbw $0x1d, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VMPSADBW_256_0x16,
+ "vmpsadbw $0x16, %%ymm6, %%ymm8, %%ymm7",
+ "vmpsadbw $0x16, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VMPSADBW_256_0x0f,
+ "vmpsadbw $0x0f, %%ymm6, %%ymm8, %%ymm7",
+ "vmpsadbw $0x0f, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSADBW_256,
+ "vpsadbw %%ymm6, %%ymm8, %%ymm7",
+ "vpsadbw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSIGNB_256,
+ "vpsignb %%ymm6, %%ymm8, %%ymm7",
+ "vpsignb (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSIGNW_256,
+ "vpsignw %%ymm6, %%ymm8, %%ymm7",
+ "vpsignw (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSIGND_256,
+ "vpsignd %%ymm6, %%ymm8, %%ymm7",
+ "vpsignd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMULHRSW_256,
+ "vpmulhrsw %%ymm6, %%ymm8, %%ymm7",
+ "vpmulhrsw (%%rax), %%ymm8, %%ymm7")
+
+/* Instructions new in AVX2. */
+
+GEN_test_Monly(VBROADCASTI128,
+ "vbroadcasti128 (%%rax), %%ymm9")
+
+GEN_test_RandM(VEXTRACTI128_0x0,
+ "vextracti128 $0x0, %%ymm7, %%xmm9",
+ "vextracti128 $0x0, %%ymm7, (%%rax)")
+
+GEN_test_RandM(VEXTRACTI128_0x1,
+ "vextracti128 $0x1, %%ymm7, %%xmm9",
+ "vextracti128 $0x1, %%ymm7, (%%rax)")
+
+GEN_test_RandM(VINSERTI128_0x0,
+ "vinserti128 $0x0, %%xmm9, %%ymm7, %%ymm8",
+ "vinserti128 $0x0, (%%rax), %%ymm7, %%ymm8")
+
+GEN_test_RandM(VINSERTI128_0x1,
+ "vinserti128 $0x1, %%xmm9, %%ymm7, %%ymm8",
+ "vinserti128 $0x1, (%%rax), %%ymm7, %%ymm8")
+
+GEN_test_RandM(VPERM2I128_0x00,
+ "vperm2i128 $0x00, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2i128 $0x00, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2I128_0xFF,
+ "vperm2i128 $0xFF, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2i128 $0xFF, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2I128_0x30,
+ "vperm2i128 $0x30, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2i128 $0x30, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2I128_0x21,
+ "vperm2i128 $0x21, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2i128 $0x21, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2I128_0x12,
+ "vperm2i128 $0x12, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2i128 $0x12, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2I128_0x03,
+ "vperm2i128 $0x03, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2i128 $0x03, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2I128_0x85,
+ "vperm2i128 $0x85, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2i128 $0x85, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2I128_0x5A,
+ "vperm2i128 $0x5A, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2i128 $0x5A, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_Ronly(VBROADCASTSS_128,
+ "vbroadcastss %%xmm9, %%xmm7")
+
+GEN_test_Ronly(VBROADCASTSS_256,
+ "vbroadcastss %%xmm9, %%ymm7")
+
+GEN_test_Ronly(VBROADCASTSD_256,
+ "vbroadcastsd %%xmm9, %%ymm7")
+
+GEN_test_RandM(VPERMD,
+ "vpermd %%ymm6, %%ymm7, %%ymm9",
+ "vpermd (%%rax), %%ymm7, %%ymm9")
+
+GEN_test_RandM(VPERMQ_0x00,
+ "vpermq $0x00, %%ymm6, %%ymm7",
+ "vpermq $0x01, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMQ_0xFE,
+ "vpermq $0xFE, %%ymm6, %%ymm7",
+ "vpermq $0xFF, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMQ_0x30,
+ "vpermq $0x30, %%ymm6, %%ymm7",
+ "vpermq $0x03, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMQ_0x21,
+ "vpermq $0x21, %%ymm6, %%ymm7",
+ "vpermq $0x12, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMQ_0xD7,
+ "vpermq $0xD7, %%ymm6, %%ymm7",
+ "vpermq $0x6C, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMQ_0xB5,
+ "vpermq $0xB5, %%ymm6, %%ymm7",
+ "vpermq $0x4A, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMQ_0x85,
+ "vpermq $0x85, %%ymm6, %%ymm7",
+ "vpermq $0xDC, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMQ_0x29,
+ "vpermq $0x29, %%ymm6, %%ymm7",
+ "vpermq $0x92, (%%rax), %%ymm7")
+
+GEN_test_RandM(VPERMPS,
+ "vpermps %%ymm6, %%ymm7, %%ymm9",
+ "vpermps (%%rax), %%ymm7, %%ymm9")
+
+GEN_test_RandM(VPERMPD_0x00,
+ "vpermpd $0x00, %%ymm6, %%ymm7",
+ "vpermpd $0x01, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMPD_0xFE,
+ "vpermpd $0xFE, %%ymm6, %%ymm7",
+ "vpermpd $0xFF, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMPD_0x30,
+ "vpermpd $0x30, %%ymm6, %%ymm7",
+ "vpermpd $0x03, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMPD_0x21,
+ "vpermpd $0x21, %%ymm6, %%ymm7",
+ "vpermpd $0x12, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMPD_0xD7,
+ "vpermpd $0xD7, %%ymm6, %%ymm7",
+ "vpermpd $0x6C, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMPD_0xB5,
+ "vpermpd $0xB5, %%ymm6, %%ymm7",
+ "vpermpd $0x4A, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMPD_0x85,
+ "vpermpd $0x85, %%ymm6, %%ymm7",
+ "vpermpd $0xDC, (%%rax), %%ymm7")
+GEN_test_RandM(VPERMPD_0x29,
+ "vpermpd $0x29, %%ymm6, %%ymm7",
+ "vpermpd $0x92, (%%rax), %%ymm7")
+
+GEN_test_RandM(VPBLENDD_128_0x00,
+ "vpblendd $0x00, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendd $0x01, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDD_128_0x02,
+ "vpblendd $0x02, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendd $0x03, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDD_128_0x04,
+ "vpblendd $0x04, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendd $0x05, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDD_128_0x06,
+ "vpblendd $0x06, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendd $0x07, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDD_128_0x08,
+ "vpblendd $0x08, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendd $0x09, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDD_128_0x0A,
+ "vpblendd $0x0A, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendd $0x0B, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDD_128_0x0C,
+ "vpblendd $0x0C, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendd $0x0D, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDD_128_0x0E,
+ "vpblendd $0x0E, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendd $0x0F, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPBLENDD_256_0x00,
+ "vpblendd $0x00, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendd $0x01, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDD_256_0xFE,
+ "vpblendd $0xFE, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendd $0xFF, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDD_256_0x30,
+ "vpblendd $0x30, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendd $0x03, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDD_256_0x21,
+ "vpblendd $0x21, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendd $0x12, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDD_256_0xD7,
+ "vpblendd $0xD7, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendd $0x6C, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDD_256_0xB5,
+ "vpblendd $0xB5, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendd $0x4A, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDD_256_0x85,
+ "vpblendd $0x85, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendd $0xDC, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPBLENDD_256_0x29,
+ "vpblendd $0x29, %%ymm6, %%ymm8, %%ymm7",
+ "vpblendd $0x92, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSLLVD_128,
+ "vpslld $27, %%xmm6, %%xmm6;"
+ "vpsrld $27, %%xmm6, %%xmm6;"
+ "vpsllvd %%xmm6, %%xmm8, %%xmm7",
+ "andl $31, (%%rax);"
+ "andl $31, 4(%%rax);"
+ "andl $31, 8(%%rax);"
+ "vpsllvd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSLLVD_256,
+ "vpslld $27, %%ymm6, %%ymm6;"
+ "vpsrld $27, %%ymm6, %%ymm6;"
+ "vpsllvd %%ymm6, %%ymm8, %%ymm7",
+ "andl $31, (%%rax);"
+ "andl $31, 4(%%rax);"
+ "andl $31, 8(%%rax);"
+ "andl $31, 16(%%rax);"
+ "andl $31, 20(%%rax);"
+ "andl $31, 24(%%rax);"
+ "vpsllvd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSLLVQ_128,
+ "vpsllq $58, %%xmm6, %%xmm6;"
+ "vpsrlq $58, %%xmm6, %%xmm6;"
+ "vpsllvq %%xmm6, %%xmm8, %%xmm7",
+ "andl $63, (%%rax);"
+ "vpsllvq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSLLVQ_256,
+ "vpsllq $58, %%ymm6, %%ymm6;"
+ "vpsrlq $58, %%ymm6, %%ymm6;"
+ "vpsllvq %%ymm6, %%ymm8, %%ymm7",
+ "andl $63, (%%rax);"
+ "andl $63, 8(%%rax);"
+ "andl $63, 16(%%rax);"
+ "vpsllvq (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSRLVD_128,
+ "vpslld $27, %%xmm6, %%xmm6;"
+ "vpsrld $27, %%xmm6, %%xmm6;"
+ "vpsrlvd %%xmm6, %%xmm8, %%xmm7",
+ "andl $31, (%%rax);"
+ "andl $31, 4(%%rax);"
+ "andl $31, 8(%%rax);"
+ "vpsrlvd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSRLVD_256,
+ "vpslld $27, %%ymm6, %%ymm6;"
+ "vpsrld $27, %%ymm6, %%ymm6;"
+ "vpsrlvd %%ymm6, %%ymm8, %%ymm7",
+ "andl $31, (%%rax);"
+ "andl $31, 4(%%rax);"
+ "andl $31, 8(%%rax);"
+ "andl $31, 16(%%rax);"
+ "andl $31, 20(%%rax);"
+ "andl $31, 24(%%rax);"
+ "vpsrlvd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSRLVQ_128,
+ "vpsllq $58, %%xmm6, %%xmm6;"
+ "vpsrlq $58, %%xmm6, %%xmm6;"
+ "vpsrlvq %%xmm6, %%xmm8, %%xmm7",
+ "andl $63, (%%rax);"
+ "vpsrlvq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSRLVQ_256,
+ "vpsllq $58, %%ymm6, %%ymm6;"
+ "vpsrlq $58, %%ymm6, %%ymm6;"
+ "vpsrlvq %%ymm6, %%ymm8, %%ymm7",
+ "andl $63, (%%rax);"
+ "andl $63, 8(%%rax);"
+ "andl $63, 16(%%rax);"
+ "vpsrlvq (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSRAVD_128,
+ "vpslld $27, %%xmm6, %%xmm6;"
+ "vpsrld $27, %%xmm6, %%xmm6;"
+ "vpsravd %%xmm6, %%xmm8, %%xmm7",
+ "andl $31, (%%rax);"
+ "andl $31, 4(%%rax);"
+ "andl $31, 8(%%rax);"
+ "vpsravd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSRAVD_256,
+ "vpslld $27, %%ymm6, %%ymm6;"
+ "vpsrld $27, %%ymm6, %%ymm6;"
+ "vpsravd %%ymm6, %%ymm8, %%ymm7",
+ "andl $31, (%%rax);"
+ "andl $31, 4(%%rax);"
+ "andl $31, 8(%%rax);"
+ "andl $31, 16(%%rax);"
+ "andl $31, 20(%%rax);"
+ "andl $31, 24(%%rax);"
+ "vpsravd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPBROADCASTB_128,
+ "vpbroadcastb %%xmm9, %%xmm7",
+ "vpbroadcastb (%%rax), %%xmm7")
+
+GEN_test_RandM(VPBROADCASTB_256,
+ "vpbroadcastb %%xmm9, %%ymm7",
+ "vpbroadcastb (%%rax), %%ymm7")
+
+GEN_test_RandM(VPBROADCASTW_128,
+ "vpbroadcastw %%xmm9, %%xmm7",
+ "vpbroadcastw (%%rax), %%xmm7")
+
+GEN_test_RandM(VPBROADCASTW_256,
+ "vpbroadcastw %%xmm9, %%ymm7",
+ "vpbroadcastw (%%rax), %%ymm7")
+
+GEN_test_RandM(VPBROADCASTD_128,
+ "vpbroadcastd %%xmm9, %%xmm7",
+ "vpbroadcastd (%%rax), %%xmm7")
+
+GEN_test_RandM(VPBROADCASTD_256,
+ "vpbroadcastd %%xmm9, %%ymm7",
+ "vpbroadcastd (%%rax), %%ymm7")
+
+GEN_test_RandM(VPBROADCASTQ_128,
+ "vpbroadcastq %%xmm9, %%xmm7",
+ "vpbroadcastq (%%rax), %%xmm7")
+
+GEN_test_RandM(VPBROADCASTQ_256,
+ "vpbroadcastq %%xmm9, %%ymm7",
+ "vpbroadcastq (%%rax), %%ymm7")
+
+GEN_test_Monly(VPMASKMOVD_128_LoadForm,
+ "vpmaskmovd (%%rax), %%xmm8, %%xmm7;"
+ "vxorps %%xmm6, %%xmm6, %%xmm6;"
+ "vpmaskmovd (%%rax,%%rax,4), %%xmm6, %%xmm9")
+
+GEN_test_Monly(VPMASKMOVD_256_LoadForm,
+ "vpmaskmovd (%%rax), %%ymm8, %%ymm7;"
+ "vxorps %%ymm6, %%ymm6, %%ymm6;"
+ "vpmaskmovd (%%rax,%%rax,4), %%ymm6, %%ymm9")
+
+GEN_test_Monly(VPMASKMOVQ_128_LoadForm,
+ "vpmaskmovq (%%rax), %%xmm8, %%xmm7;"
+ "vxorpd %%xmm6, %%xmm6, %%xmm6;"
+ "vpmaskmovq (%%rax,%%rax,4), %%xmm6, %%xmm9")
+
+GEN_test_Monly(VPMASKMOVQ_256_LoadForm,
+ "vpmaskmovq (%%rax), %%ymm8, %%ymm7;"
+ "vxorpd %%ymm6, %%ymm6, %%ymm6;"
+ "vpmaskmovq (%%rax,%%rax,4), %%ymm6, %%ymm9")
+
+GEN_test_Ronly(VGATHERDPS_128,
+ "vpslld $25, %%xmm7, %%xmm8;"
+ "vpsrld $25, %%xmm8, %%xmm8;"
+ "vblendvps %%xmm6, %%xmm8, %%xmm7, %%xmm8;"
+ "leaq randArray(%%rip), %%r14;"
+ "vgatherdps %%xmm6, 3(%%r14,%%xmm8,4), %%xmm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VGATHERDPS_256,
+ "vpslld $25, %%ymm7, %%ymm8;"
+ "vpsrld $25, %%ymm8, %%ymm8;"
+ "vblendvps %%ymm6, %%ymm8, %%ymm7, %%ymm8;"
+ "leaq randArray(%%rip), %%r14;"
+ "vgatherdps %%ymm6, 3(%%r14,%%ymm8,4), %%ymm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VGATHERQPS_128_1,
+ "vpsllq $57, %%xmm7, %%xmm8;"
+ "vpsrlq $57, %%xmm8, %%xmm8;"
+ "vpmovsxdq %%xmm6, %%xmm9;"
+ "vblendvpd %%xmm9, %%xmm8, %%xmm7, %%xmm8;"
+ "vmovdqa 96(%0), %%ymm9;"
+ "leaq randArray(%%rip), %%r14;"
+ "vgatherqps %%xmm6, 3(%%r14,%%xmm8,4), %%xmm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VGATHERQPS_256_1,
+ "vpsllq $57, %%ymm7, %%ymm8;"
+ "vpsrlq $57, %%ymm8, %%ymm8;"
+ "vpmovsxdq %%xmm6, %%ymm9;"
+ "vblendvpd %%ymm9, %%ymm8, %%ymm7, %%ymm8;"
+ "vmovdqa 96(%0), %%ymm9;"
+ "leaq randArray(%%rip), %%r14;"
+ "vgatherqps %%xmm6, 3(%%r14,%%ymm8,4), %%xmm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VGATHERQPS_128_2,
+ "vpsllq $57, %%xmm7, %%xmm8;"
+ "vpsrlq $57, %%xmm8, %%xmm8;"
+ "vpmovsxdq %%xmm6, %%xmm9;"
+ "vblendvpd %%xmm9, %%xmm8, %%xmm7, %%xmm8;"
+ "vmovdqa 96(%0), %%ymm9;"
+ "leaq randArray(%%rip), %%r14;"
+ "vmovq %%r14, %%xmm7;"
+ "vpsllq $2, %%xmm8, %%xmm8;"
+ "vpbroadcastq %%xmm7, %%xmm7;"
+ "vpaddq %%xmm7, %%xmm8, %%xmm8;"
+ "vgatherqps %%xmm6, 1(,%%xmm8,1), %%xmm9;"
+ "vpsubq %%xmm7, %%xmm8, %%xmm8;"
+ "vmovdqa 0(%0), %%ymm7;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VGATHERQPS_256_2,
+ "vpsllq $57, %%ymm7, %%ymm8;"
+ "vpsrlq $57, %%ymm8, %%ymm8;"
+ "vpmovsxdq %%xmm6, %%ymm9;"
+ "vblendvpd %%ymm9, %%ymm8, %%ymm7, %%ymm8;"
+ "vmovdqa 96(%0), %%ymm9;"
+ "leaq randArray(%%rip), %%r14;"
+ "vmovq %%r14, %%xmm7;"
+ "vpsllq $2, %%ymm8, %%ymm8;"
+ "vpbroadcastq %%xmm7, %%ymm7;"
+ "vpaddq %%ymm7, %%ymm8, %%ymm8;"
+ "vgatherqps %%xmm6, 1(,%%ymm8,1), %%xmm9;"
+ "vpsubq %%ymm7, %%ymm8, %%ymm8;"
+ "vmovdqa 0(%0), %%ymm7;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VGATHERDPD_128,
+ "vpslld $26, %%xmm7, %%xmm8;"
+ "vpsrld $26, %%xmm8, %%xmm8;"
+ "vshufps $13, %%xmm6, %%xmm6, %%xmm9;"
+ "vblendvps %%xmm9, %%xmm8, %%xmm7, %%xmm8;"
+ "vmovdqa 96(%0), %%ymm9;"
+ "leaq randArray(%%rip), %%r14;"
+ "vgatherdpd %%xmm6, 3(%%r14,%%xmm8,8), %%xmm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VGATHERDPD_256,
+ "vpslld $26, %%ymm7, %%ymm8;"
+ "vpsrld $26, %%ymm8, %%ymm8;"
+ "vextracti128 $1, %%ymm6, %%xmm9;"
+ "vshufps $221, %%ymm9, %%ymm6, %%ymm9;"
+ "vblendvps %%ymm9, %%ymm8, %%ymm7, %%ymm8;"
+ "vmovdqa 96(%0), %%ymm9;"
+ "leaq randArray(%%rip), %%r14;"
+ "vgatherdpd %%ymm6, 3(%%r14,%%xmm8,8), %%ymm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VGATHERQPD_128_1,
+ "vpsllq $58, %%xmm7, %%xmm8;"
+ "vpsrlq $58, %%xmm8, %%xmm8;"
+ "vblendvpd %%xmm6, %%xmm8, %%xmm7, %%xmm8;"
+ "leaq randArray(%%rip), %%r14;"
+ "vgatherqpd %%xmm6, 3(%%r14,%%xmm8,8), %%xmm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VGATHERQPD_256_1,
+ "vpsllq $58, %%ymm7, %%ymm8;"
+ "vpsrlq $58, %%ymm8, %%ymm8;"
+ "vblendvpd %%ymm6, %%ymm8, %%ymm7, %%ymm8;"
+ "leaq randArray(%%rip), %%r14;"
+ "vgatherqpd %%ymm6, 3(%%r14,%%ymm8,8), %%ymm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VGATHERQPD_128_2,
+ "vpsllq $58, %%xmm7, %%xmm8;"
+ "vpsrlq $58, %%xmm8, %%xmm8;"
+ "vblendvpd %%xmm6, %%xmm8, %%xmm7, %%xmm8;"
+ "leaq randArray(%%rip), %%r14;"
+ "vmovq %%r14, %%xmm7;"
+ "vpsllq $2, %%xmm8, %%xmm8;"
+ "vpbroadcastq %%xmm7, %%xmm7;"
+ "vpaddq %%xmm7, %%xmm8, %%xmm8;"
+ "vgatherqpd %%xmm6, 1(,%%xmm8,1), %%xmm9;"
+ "vpsubq %%xmm7, %%xmm8, %%xmm8;"
+ "vmovdqa 0(%0), %%ymm7;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VGATHERQPD_256_2,
+ "vpsllq $58, %%ymm7, %%ymm8;"
+ "vpsrlq $58, %%ymm8, %%ymm8;"
+ "vblendvpd %%ymm6, %%ymm8, %%ymm7, %%ymm8;"
+ "leaq randArray(%%rip), %%r14;"
+ "vmovq %%r14, %%xmm7;"
+ "vpsllq $2, %%ymm8, %%ymm8;"
+ "vpbroadcastq %%xmm7, %%ymm7;"
+ "vpaddq %%ymm7, %%ymm8, %%ymm8;"
+ "vgatherqpd %%ymm6, 1(,%%ymm8,1), %%ymm9;"
+ "vpsubq %%ymm7, %%ymm8, %%ymm8;"
+ "vmovdqa 0(%0), %%ymm7;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VPGATHERDD_128,
+ "vpslld $25, %%xmm7, %%xmm8;"
+ "vpsrld $25, %%xmm8, %%xmm8;"
+ "vblendvps %%xmm6, %%xmm8, %%xmm7, %%xmm8;"
+ "leaq randArray(%%rip), %%r14;"
+ "vpgatherdd %%xmm6, 3(%%r14,%%xmm8,4), %%xmm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VPGATHERDD_256,
+ "vpslld $25, %%ymm7, %%ymm8;"
+ "vpsrld $25, %%ymm8, %%ymm8;"
+ "vblendvps %%ymm6, %%ymm8, %%ymm7, %%ymm8;"
+ "leaq randArray(%%rip), %%r14;"
+ "vpgatherdd %%ymm6, 3(%%r14,%%ymm8,4), %%ymm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VPGATHERQD_128_1,
+ "vpsllq $57, %%xmm7, %%xmm8;"
+ "vpsrlq $57, %%xmm8, %%xmm8;"
+ "vpmovsxdq %%xmm6, %%xmm9;"
+ "vblendvpd %%xmm9, %%xmm8, %%xmm7, %%xmm8;"
+ "vmovdqa 96(%0), %%ymm9;"
+ "leaq randArray(%%rip), %%r14;"
+ "vpgatherqd %%xmm6, 3(%%r14,%%xmm8,4), %%xmm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VPGATHERQD_256_1,
+ "vpsllq $57, %%ymm7, %%ymm8;"
+ "vpsrlq $57, %%ymm8, %%ymm8;"
+ "vpmovsxdq %%xmm6, %%ymm9;"
+ "vblendvpd %%ymm9, %%ymm8, %%ymm7, %%ymm8;"
+ "vmovdqa 96(%0), %%ymm9;"
+ "leaq randArray(%%rip), %%r14;"
+ "vpgatherqd %%xmm6, 3(%%r14,%%ymm8,4), %%xmm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VPGATHERQD_128_2,
+ "vpsllq $57, %%xmm7, %%xmm8;"
+ "vpsrlq $57, %%xmm8, %%xmm8;"
+ "vpmovsxdq %%xmm6, %%xmm9;"
+ "vblendvpd %%xmm9, %%xmm8, %%xmm7, %%xmm8;"
+ "vmovdqa 96(%0), %%ymm9;"
+ "leaq randArray(%%rip), %%r14;"
+ "vmovq %%r14, %%xmm7;"
+ "vpsllq $2, %%xmm8, %%xmm8;"
+ "vpbroadcastq %%xmm7, %%xmm7;"
+ "vpaddq %%xmm7, %%xmm8, %%xmm8;"
+ "vpgatherqd %%xmm6, 1(,%%xmm8,1), %%xmm9;"
+ "vpsubq %%xmm7, %%xmm8, %%xmm8;"
+ "vmovdqa 0(%0), %%ymm7;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VPGATHERQD_256_2,
+ "vpsllq $57, %%ymm7, %%ymm8;"
+ "vpsrlq $57, %%ymm8, %%ymm8;"
+ "vpmovsxdq %%xmm6, %%ymm9;"
+ "vblendvpd %%ymm9, %%ymm8, %%ymm7, %%ymm8;"
+ "vmovdqa 96(%0), %%ymm9;"
+ "leaq randArray(%%rip), %%r14;"
+ "vmovq %%r14, %%xmm7;"
+ "vpsllq $2, %%ymm8, %%ymm8;"
+ "vpbroadcastq %%xmm7, %%ymm7;"
+ "vpaddq %%ymm7, %%ymm8, %%ymm8;"
+ "vpgatherqd %%xmm6, 1(,%%ymm8,1), %%xmm9;"
+ "vpsubq %%ymm7, %%ymm8, %%ymm8;"
+ "vmovdqa 0(%0), %%ymm7;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VPGATHERDQ_128,
+ "vpslld $26, %%xmm7, %%xmm8;"
+ "vpsrld $26, %%xmm8, %%xmm8;"
+ "vshufps $13, %%xmm6, %%xmm6, %%xmm9;"
+ "vblendvps %%xmm9, %%xmm8, %%xmm7, %%xmm8;"
+ "vmovdqa 96(%0), %%ymm9;"
+ "leaq randArray(%%rip), %%r14;"
+ "vpgatherdq %%xmm6, 3(%%r14,%%xmm8,8), %%xmm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VPGATHERDQ_256,
+ "vpslld $26, %%ymm7, %%ymm8;"
+ "vpsrld $26, %%ymm8, %%ymm8;"
+ "vextracti128 $1, %%ymm6, %%xmm9;"
+ "vshufps $221, %%ymm9, %%ymm6, %%ymm9;"
+ "vblendvps %%ymm9, %%ymm8, %%ymm7, %%ymm8;"
+ "vmovdqa 96(%0), %%ymm9;"
+ "leaq randArray(%%rip), %%r14;"
+ "vpgatherdq %%ymm6, 3(%%r14,%%xmm8,8), %%ymm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VPGATHERQQ_128_1,
+ "vpsllq $58, %%xmm7, %%xmm8;"
+ "vpsrlq $58, %%xmm8, %%xmm8;"
+ "vblendvpd %%xmm6, %%xmm8, %%xmm7, %%xmm8;"
+ "leaq randArray(%%rip), %%r14;"
+ "vpgatherqq %%xmm6, 3(%%r14,%%xmm8,8), %%xmm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VPGATHERQQ_256_1,
+ "vpsllq $58, %%ymm7, %%ymm8;"
+ "vpsrlq $58, %%ymm8, %%ymm8;"
+ "vblendvpd %%ymm6, %%ymm8, %%ymm7, %%ymm8;"
+ "leaq randArray(%%rip), %%r14;"
+ "vpgatherqq %%ymm6, 3(%%r14,%%ymm8,8), %%ymm9;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VPGATHERQQ_128_2,
+ "vpsllq $58, %%xmm7, %%xmm8;"
+ "vpsrlq $58, %%xmm8, %%xmm8;"
+ "vblendvpd %%xmm6, %%xmm8, %%xmm7, %%xmm8;"
+ "leaq randArray(%%rip), %%r14;"
+ "vmovq %%r14, %%xmm7;"
+ "vpsllq $2, %%xmm8, %%xmm8;"
+ "vpbroadcastq %%xmm7, %%xmm7;"
+ "vpaddq %%xmm7, %%xmm8, %%xmm8;"
+ "vpgatherqq %%xmm6, 1(,%%xmm8,1), %%xmm9;"
+ "vpsubq %%xmm7, %%xmm8, %%xmm8;"
+ "vmovdqa 0(%0), %%ymm7;"
+ "xorl %%r14d, %%r14d")
+
+GEN_test_Ronly(VPGATHERQQ_256_2,
+ "vpsllq $58, %%ymm7, %%ymm8;"
+ "vpsrlq $58, %%ymm8, %%ymm8;"
+ "vblendvpd %%ymm6, %%ymm8, %%ymm7, %%ymm8;"
+ "leaq randArray(%%rip), %%r14;"
+ "vmovq %%r14, %%xmm7;"
+ "vpsllq $2, %%ymm8, %%ymm8;"
+ "vpbroadcastq %%xmm7, %%ymm7;"
+ "vpaddq %%ymm7, %%ymm8, %%ymm8;"
+ "vpgatherqq %%ymm6, 1(,%%ymm8,1), %%ymm9;"
+ "vpsubq %%ymm7, %%ymm8, %%ymm8;"
+ "vmovdqa 0(%0), %%ymm7;"
+ "xorl %%r14d, %%r14d")
+
+/* Comment duplicated above, for convenient reference:
+ Allowed operands in test insns:
+ Reg form: %ymm6, %ymm7, %ymm8, %ymm9 and %r14.
+ Mem form: (%rax), %ymm7, %ymm8, %ymm9 and %r14.
+ Imm8 etc fields are also allowed, where they make sense.
+*/
+
+#define N_DEFAULT_ITERS 3
+
+// Do the specified test some number of times
+#define DO_N(_iters, _testfn) \
+ do { int i; for (i = 0; i < (_iters); i++) { test_##_testfn(); } } while (0)
+
+// Do the specified test the default number of times
+#define DO_D(_testfn) DO_N(N_DEFAULT_ITERS, _testfn)
+
+
+int main ( void )
+{
+ DO_D( VPOR_256 );
+ DO_D( VPXOR_256 );
+ DO_D( VPSUBB_256 );
+ DO_D( VPSUBD_256 );
+ DO_D( VPADDD_256 );
+ DO_D( VPMOVZXWD_256 );
+ DO_D( VPMOVZXBW_256 );
+ DO_D( VPBLENDVB_256 );
+ DO_D( VPMINSD_256 );
+ DO_D( VPMAXSD_256 );
+ DO_D( VPSHUFB_256 );
+ DO_D( VPUNPCKLBW_256 );
+ DO_D( VPUNPCKHBW_256 );
+ DO_D( VPABSD_256 );
+ DO_D( VPACKUSWB_256 );
+ DO_D( VPMOVMSKB_256 );
+ DO_D( VPAND_256 );
+ DO_D( VPCMPEQB_256 );
+ DO_D( VPSHUFLW_0x39_256 );
+ DO_D( VPSHUFHW_0x39_256 );
+ DO_D( VPMULLW_256 );
+ DO_D( VPADDUSW_256 );
+ DO_D( VPMULHUW_256 );
+ DO_D( VPADDUSB_256 );
+ DO_D( VPUNPCKLWD_256 );
+ DO_D( VPUNPCKHWD_256 );
+ DO_D( VPSLLD_0x05_256 );
+ DO_D( VPSRLD_0x05_256 );
+ DO_D( VPSRAD_0x05_256 );
+ DO_D( VPSUBUSB_256 );
+ DO_D( VPSUBSB_256 );
+ DO_D( VPSRLDQ_0x05_256 );
+ DO_D( VPSLLDQ_0x05_256 );
+ DO_D( VPANDN_256 );
+ DO_D( VPUNPCKLQDQ_256 );
+ DO_D( VPSRLW_0x05_256 );
+ DO_D( VPSLLW_0x05_256 );
+ DO_D( VPADDW_256 );
+ DO_D( VPACKSSDW_256 );
+ DO_D( VPUNPCKLDQ_256 );
+ DO_D( VPCMPEQD_256 );
+ DO_D( VPSHUFD_0x39_256 );
+ DO_D( VPADDQ_256 );
+ DO_D( VPSUBQ_256 );
+ DO_D( VPSUBW_256 );
+ DO_D( VPCMPEQQ_256 );
+ DO_D( VPCMPGTQ_256 );
+ DO_D( VPSRLQ_0x05_256 );
+ DO_D( VPMULUDQ_256 );
+ DO_D( VPMULDQ_256 );
+ DO_D( VPSLLQ_0x05_256 );
+ DO_D( VPMAXUD_256 );
+ DO_D( VPMINUD_256 );
+ DO_D( VPMULLD_256 );
+ DO_D( VPMAXUW_256 );
+ DO_D( VPMINUW_256 );
+ DO_D( VPMAXSW_256 );
+ DO_D( VPMINSW_256 );
+ DO_D( VPMAXUB_256 );
+ DO_D( VPMINUB_256 );
+ DO_D( VPMAXSB_256 );
+ DO_D( VPMINSB_256 );
+ DO_D( VPMOVSXBW_256 );
+ DO_D( VPSUBUSW_256 );
+ DO_D( VPSUBSW_256 );
+ DO_D( VPCMPEQW_256 );
+ DO_D( VPADDB_256 );
+ DO_D( VPUNPCKHDQ_256 );
+ DO_D( VPMOVSXDQ_256 );
+ DO_D( VPMOVSXWD_256 );
+ DO_D( VPMULHW_256 );
+ DO_D( VPUNPCKHQDQ_256 );
+ DO_D( VPSRAW_0x05_256 );
+ DO_D( VPCMPGTB_256 );
+ DO_D( VPCMPGTW_256 );
+ DO_D( VPCMPGTD_256 );
+ DO_D( VPMOVZXBD_256 );
+ DO_D( VPMOVSXBD_256 );
+ DO_D( VPALIGNR_256_1of3 );
+ DO_D( VPALIGNR_256_2of3 );
+ DO_D( VPALIGNR_256_3of3 );
+ DO_D( VPBLENDW_256_0x00 );
+ DO_D( VPBLENDW_256_0xFE );
+ DO_D( VPBLENDW_256_0x30 );
+ DO_D( VPBLENDW_256_0x21 );
+ DO_D( VPBLENDW_256_0xD7 );
+ DO_D( VPBLENDW_256_0xB5 );
+ DO_D( VPBLENDW_256_0x85 );
+ DO_D( VPBLENDW_256_0x29 );
+ DO_D( VPSLLW_256 );
+ DO_D( VPSRLW_256 );
+ DO_D( VPSRAW_256 );
+ DO_D( VPSLLD_256 );
+ DO_D( VPSRLD_256 );
+ DO_D( VPSRAD_256 );
+ DO_D( VPSLLQ_256 );
+ DO_D( VPSRLQ_256 );
+ DO_D( VPMADDWD_256 );
+ DO_D( VMOVNTDQA_256 );
+ DO_D( VPACKSSWB_256 );
+ DO_D( VPAVGB_256 );
+ DO_D( VPAVGW_256 );
+ DO_D( VPADDSB_256 );
+ DO_D( VPADDSW_256 );
+ DO_D( VPHADDW_256 );
+ DO_D( VPHADDD_256 );
+ DO_D( VPHADDSW_256 );
+ DO_D( VPMADDUBSW_256 );
+ DO_D( VPHSUBW_256 );
+ DO_D( VPHSUBD_256 );
+ DO_D( VPHSUBSW_256 );
+ DO_D( VPABSB_256 );
+ DO_D( VPABSW_256 );
+ DO_D( VPMOVSXBQ_256 );
+ DO_D( VPMOVSXWQ_256 );
+ DO_D( VPACKUSDW_256 );
+ DO_D( VPMOVZXBQ_256 );
+ DO_D( VPMOVZXWQ_256 );
+ DO_D( VPMOVZXDQ_256 );
+ DO_D( VMPSADBW_256_0x0 );
+ DO_D( VMPSADBW_256_0x39 );
+ DO_D( VMPSADBW_256_0x32 );
+ DO_D( VMPSADBW_256_0x2b );
+ DO_D( VMPSADBW_256_0x24 );
+ DO_D( VMPSADBW_256_0x1d );
+ DO_D( VMPSADBW_256_0x16 );
+ DO_D( VMPSADBW_256_0x0f );
+ DO_D( VPSADBW_256 );
+ DO_D( VPSIGNB_256 );
+ DO_D( VPSIGNW_256 );
+ DO_D( VPSIGND_256 );
+ DO_D( VPMULHRSW_256 );
+ DO_D( VBROADCASTI128 );
+ DO_D( VEXTRACTI128_0x0 );
+ DO_D( VEXTRACTI128_0x1 );
+ DO_D( VINSERTI128_0x0 );
+ DO_D( VINSERTI128_0x1 );
+ DO_D( VPERM2I128_0x00 );
+ DO_D( VPERM2I128_0xFF );
+ DO_D( VPERM2I128_0x30 );
+ DO_D( VPERM2I128_0x21 );
+ DO_D( VPERM2I128_0x12 );
+ DO_D( VPERM2I128_0x03 );
+ DO_D( VPERM2I128_0x85 );
+ DO_D( VPERM2I128_0x5A );
+ DO_D( VBROADCASTSS_128 );
+ DO_D( VBROADCASTSS_256 );
+ DO_D( VBROADCASTSD_256 );
+ DO_D( VPERMD );
+ DO_D( VPERMQ_0x00 );
+ DO_D( VPERMQ_0xFE );
+ DO_D( VPERMQ_0x30 );
+ DO_D( VPERMQ_0x21 );
+ DO_D( VPERMQ_0xD7 );
+ DO_D( VPERMQ_0xB5 );
+ DO_D( VPERMQ_0x85 );
+ DO_D( VPERMQ_0x29 );
+ DO_D( VPERMPS );
+ DO_D( VPERMPD_0x00 );
+ DO_D( VPERMPD_0xFE );
+ DO_D( VPERMPD_0x30 );
+ DO_D( VPERMPD_0x21 );
+ DO_D( VPERMPD_0xD7 );
+ DO_D( VPERMPD_0xB5 );
+ DO_D( VPERMPD_0x85 );
+ DO_D( VPERMPD_0x29 );
+ DO_D( VPBLENDD_128_0x00 );
+ DO_D( VPBLENDD_128_0x02 );
+ DO_D( VPBLENDD_128_0x04 );
+ DO_D( VPBLENDD_128_0x06 );
+ DO_D( VPBLENDD_128_0x08 );
+ DO_D( VPBLENDD_128_0x0A );
+ DO_D( VPBLENDD_128_0x0C );
+ DO_D( VPBLENDD_128_0x0E );
+ DO_D( VPBLENDD_256_0x00 );
+ DO_D( VPBLENDD_256_0xFE );
+ DO_D( VPBLENDD_256_0x30 );
+ DO_D( VPBLENDD_256_0x21 );
+ DO_D( VPBLENDD_256_0xD7 );
+ DO_D( VPBLENDD_256_0xB5 );
+ DO_D( VPBLENDD_256_0x85 );
+ DO_D( VPBLENDD_256_0x29 );
+ DO_D( VPSLLVD_128 );
+ DO_D( VPSLLVD_256 );
+ DO_D( VPSLLVQ_128 );
+ DO_D( VPSLLVQ_256 );
+ DO_D( VPSRLVD_128 );
+ DO_D( VPSRLVD_256 );
+ DO_D( VPSRLVQ_128 );
+ DO_D( VPSRLVQ_256 );
+ DO_D( VPSRAVD_128 );
+ DO_D( VPSRAVD_256 );
+ DO_D( VPBROADCASTB_128 );
+ DO_D( VPBROADCASTB_256 );
+ DO_D( VPBROADCASTW_128 );
+ DO_D( VPBROADCASTW_256 );
+ DO_D( VPBROADCASTD_128 );
+ DO_D( VPBROADCASTD_256 );
+ DO_D( VPBROADCASTQ_128 );
+ DO_D( VPBROADCASTQ_256 );
+ DO_D( VPMASKMOVD_128_LoadForm );
+ DO_D( VPMASKMOVD_256_LoadForm );
+ DO_D( VPMASKMOVQ_128_LoadForm );
+ DO_D( VPMASKMOVQ_256_LoadForm );
+ { int i; for (i = 0; i < sizeof(randArray); i++) randArray[i] = randUChar(); }
+ DO_D( VGATHERDPS_128 );
+ DO_D( VGATHERDPS_256 );
+ DO_D( VGATHERQPS_128_1 );
+ DO_D( VGATHERQPS_256_1 );
+ DO_D( VGATHERQPS_128_2 );
+ DO_D( VGATHERQPS_256_2 );
+ DO_D( VGATHERDPD_128 );
+ DO_D( VGATHERDPD_256 );
+ DO_D( VGATHERQPD_128_1 );
+ DO_D( VGATHERQPD_256_1 );
+ DO_D( VGATHERQPD_128_2 );
+ DO_D( VGATHERQPD_256_2 );
+ DO_D( VPGATHERDD_128 );
+ DO_D( VPGATHERDD_256 );
+ DO_D( VPGATHERQD_128_1 );
+ DO_D( VPGATHERQD_256_1 );
+ DO_D( VPGATHERQD_128_2 );
+ DO_D( VPGATHERQD_256_2 );
+ DO_D( VPGATHERDQ_128 );
+ DO_D( VPGATHERDQ_256 );
+ DO_D( VPGATHERQQ_128_1 );
+ DO_D( VPGATHERQQ_256_1 );
+ DO_D( VPGATHERQQ_128_2 );
+ DO_D( VPGATHERQQ_256_2 );
+ return 0;
+}
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/avx2-1.stdout.exp valgrind-3.8.0.new/none/tests/amd64/avx2-1.stdout.exp
--- valgrind-3.8.0.orig/none/tests/amd64/avx2-1.stdout.exp 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/none/tests/amd64/avx2-1.stdout.exp 2012-09-13 11:19:25.190050679 +0200
@@ -0,0 +1,18468 @@
+VPOR_256(reg)
+ before
+ 7d6528c5fa956a0d.69c3e9a6af27d13b.5175e39d19c9ca1e.98f24a4984175700
+ b6d2fb5aa7bc5127.fe9915e556a044b2.60b160857d45c484.47b8d8c0eeef1e50
+ 065d77195d623e6b.842adc6450659e17.19a348215c3a67fd.399182c2dbcc2d38
+ cb509970b8136c85.d740b80eb7839b97.d89998df5035ed36.4a4bc43968bc40e5
+ 56b01a12b0ca1583
+ after
+ b6dfff5bfffe7f6f.febbdde556e5deb7.79b368a57d7fe7fd.7fb9dac2ffef3f78
+ b6d2fb5aa7bc5127.fe9915e556a044b2.60b160857d45c484.47b8d8c0eeef1e50
+ 065d77195d623e6b.842adc6450659e17.19a348215c3a67fd.399182c2dbcc2d38
+ cb509970b8136c85.d740b80eb7839b97.d89998df5035ed36.4a4bc43968bc40e5
+ 56b01a12b0ca1583
+VPOR_256(mem)
+ before
+ 398e0039cf03663d.5ff85bc9535c191f.d3a727d1a705f65d.f9dd4a29f8c093db
+ cfaff39be272ef40.20a1bb92cbc97fe8.542da4983df76c96.d8bc5c6dee699597
+ f4e06e2205236eb7.6897b536bbe4da8a.369dab4f9465b86e.d182c916cebc2e17
+ 84ededbc53239dcf.95264321bf3b68b2.55c2b9e2c95c9810.407b8d9035449b06
+ 81f2a547be8d1811
+ after
+ 398e0039cf03663d.5ff85bc9535c191f.d3a727d1a705f65d.f9dd4a29f8c093db
+ cfaff39be272ef40.20a1bb92cbc97fe8.542da4983df76c96.d8bc5c6dee699597
+ ffaff3bbef73ef7d.7ff9fbdbdbdd7fff.d7afa7d9bff7fedf.f9fd5e6dfee997df
+ 84ededbc53239dcf.95264321bf3b68b2.55c2b9e2c95c9810.407b8d9035449b06
+ 81f2a547be8d1811
+
+VPOR_256(reg)
+ before
+ f0350ca70523e0e4.5ba1ec54e87d39b3.019963bf7459630b.8d69483df7e8c6a9
+ e98ebd1ca893312a.54cae7d5e13dfe91.0a3e0f7c75cb0842.b95ed64d3b13ff64
+ c84ab71340684590.4d325b2d5a70a792.0a5f45c55f1c9202.b76ddefcb0ebfe6e
+ e9b5f3f66b2e58c1.21a6c3476d21f1e5.5f490104ced83ff8.6262dd37727c80f3
+ 96084deb9ed0411e
+ after
+ e9cebf1fe8fb75ba.5dfafffdfb7dff93.0a7f4ffd7fdf9a42.bf7fdefdbbfbff6e
+ e98ebd1ca893312a.54cae7d5e13dfe91.0a3e0f7c75cb0842.b95ed64d3b13ff64
+ c84ab71340684590.4d325b2d5a70a792.0a5f45c55f1c9202.b76ddefcb0ebfe6e
+ e9b5f3f66b2e58c1.21a6c3476d21f1e5.5f490104ced83ff8.6262dd37727c80f3
+ 96084deb9ed0411e
+VPOR_256(mem)
+ before
+ 2e2dac0350f6fd1c.a81b6e33c572a86a.acf29b0f395c98b4.63483da65c8c49d0
+ 089b756aa3f77018.61c82534e9bf6f37.c9e25f72d82e582b.73a8f718a8c3ec35
+ ff1f240eb3e1553f.6f07136773a2ead3.56428c5a66a2ec77.ecb42ac54b0966d4
+ ee8536da9dbf68bc.3026343700a654eb.2ddd9db4ffc411c4.28bad218e4ebf159
+ 8404eb7f0cf4ca6f
+ after
+ 2e2dac0350f6fd1c.a81b6e33c572a86a.acf29b0f395c98b4.63483da65c8c49d0
+ 089b756aa3f77018.61c82534e9bf6f37.c9e25f72d82e582b.73a8f718a8c3ec35
+ 2ebffd6bf3f7fd1c.e9db6f37edffef7f.edf2df7ff97ed8bf.73e8ffbefccfedf5
+ ee8536da9dbf68bc.3026343700a654eb.2ddd9db4ffc411c4.28bad218e4ebf159
+ 8404eb7f0cf4ca6f
+
+VPOR_256(reg)
+ before
+ 5cdf726562b02dc2.b39925ba7d9d67bc.ff6f850f2c57ea2a.2c810e6dc1a1833d
+ 0c9761367fac55ff.28276f9a6e880c6b.372f015d9242e83d.2ef85b6fc544fd0f
+ f078b65e01737fd2.2bfa8f668c8b14f4.36b2a38dcef18acf.0e0f01a829ba3c66
+ 65ce6d498492e7e7.96df010bf4b23b84.57436a097df30b8d.aa927a03090dfc6d
+ dc4c446c804bf950
+ after
+ fcfff77e7fff7fff.2bffeffeee8b1cff.37bfa3dddef3eaff.2eff5befedfefd6f
+ 0c9761367fac55ff.28276f9a6e880c6b.372f015d9242e83d.2ef85b6fc544fd0f
+ f078b65e01737fd2.2bfa8f668c8b14f4.36b2a38dcef18acf.0e0f01a829ba3c66
+ 65ce6d498492e7e7.96df010bf4b23b84.57436a097df30b8d.aa927a03090dfc6d
+ dc4c446c804bf950
+VPOR_256(mem)
+ before
+ 810bdacfab80ee3d.c5e48064a393c8e9.47a34273c10a3c47.f5304f3e3ad1a923
+ 769ab818a5b7985e.6d08ed19fa045f84.1810cd8c109ed568.6ec34f98a2199d3c
+ 95c45b338afcb3df.b984aed62671e865.e6f21d40fc7bc013.1c4a678450562685
+ bc563e0c775bfaed.05a5c205c3659f38.8e17b17da2acb976.5d0f926ce1157eaa
+ 8b5fccbef0e1e256
+ after
+ 810bdacfab80ee3d.c5e48064a393c8e9.47a34273c10a3c47.f5304f3e3ad1a923
+ 769ab818a5b7985e.6d08ed19fa045f84.1810cd8c109ed568.6ec34f98a2199d3c
+ f79bfadfafb7fe7f.edeced7dfb97dfed.5fb3cfffd19efd6f.fff34fbebad9bd3f
+ bc563e0c775bfaed.05a5c205c3659f38.8e17b17da2acb976.5d0f926ce1157eaa
+ 8b5fccbef0e1e256
+
+VPXOR_256(reg)
+ before
+ 048612e51a468e36.c51cdd8f87e12ab4.acb722146c6cbfa9.ea4a022e1d3d7dbb
+ 22cf5e4cfad1bdf5.8de2b4a9d799ff5f.0c05cb6ebd128663.d7568e3e8a3ac80e
+ 4288ae612c0dad40.f0733f448390351b.80ddba7e53e42d12.3208cf9b04b0569c
+ c1fbfd8f4d8698c2.cb9dfb4ea5d18713.6489eab2c96df363.d52c4330a7aae391
+ 9d8e66ea90352a18
+ after
+ 6047f02dd6dc10b5.7d918bed5409ca44.8cd87110eef6ab71.e55e41a58e8a9e92
+ 22cf5e4cfad1bdf5.8de2b4a9d799ff5f.0c05cb6ebd128663.d7568e3e8a3ac80e
+ 4288ae612c0dad40.f0733f448390351b.80ddba7e53e42d12.3208cf9b04b0569c
+ c1fbfd8f4d8698c2.cb9dfb4ea5d18713.6489eab2c96df363.d52c4330a7aae391
+ 9d8e66ea90352a18
+VPXOR_256(mem)
+ before
+ 66fab2b3db5ce85e.f9754842f9c9ba28.f82a63b15c68b274.14575775bc3a1202
+ 0c3ca578a32bd88e.474289e7cb61501e.54e7f35bc162726a.ec91fe34c7d6c79a
+ 6b1fba2604afb8d5.08aebee85fda964f.bba02737f3c98220.4784d95987cd4ed8
+ 5f706da71bf2425f.9605e2b252c1c868.09217c310baca0c3.837be65197abe268
+ fbc4208894fdc0f5
+ after
+ 66fab2b3db5ce85e.f9754842f9c9ba28.f82a63b15c68b274.14575775bc3a1202
+ 0c3ca578a32bd88e.474289e7cb61501e.54e7f35bc162726a.ec91fe34c7d6c79a
+ 6ac617cb787730d0.be37c1a532a8ea36.accd90ea9d0ac01e.f8c6a9417becd598
+ 5f706da71bf2425f.9605e2b252c1c868.09217c310baca0c3.837be65197abe268
+ fbc4208894fdc0f5
+
+VPXOR_256(reg)
+ before
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+ 2c3ffa1aebe6a4d2
+VPXOR_256(mem)
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+ 16559ec50352a3d9
+
+VPXOR_256(reg)
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+ 89fba268812abdb2.1e4a9e0958fac555.adddf0eb4808f067.04c857e949cc0fac
+ bc3127138b19183c
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+ 0194ddb82b49abf0
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+VPSUBB_256(reg)
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+ be625608d5abd787
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+VPSUBB_256(reg)
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+ 10fd4e94e9c808f5
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+ 31005fb9ada2074b
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+VPSUBB_256(reg)
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+ 1f1030333fb8fa4b
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+VPSUBD_256(reg)
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+ b3fd9698098ef5b0
+VPSUBD_256(mem)
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+ 2993e139f7d64ff4
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+VPSUBD_256(reg)
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+ f099b6dd61462ec3
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+ d4ec68f21f468712
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+VPSUBD_256(reg)
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+ a1cd852d9cd97050.2d146432e64644c9.30c9028972f8733d.11f7fa4450de2529
+ c33ebc4b44b8ddd8
+VPSUBD_256(mem)
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+ 84db9fe3e4b100d4
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+VPADDD_256(reg)
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+ 62bbc77143b71e92.668b24fb9133bf52.1adad8978cbfb478.29861f0d48dc87f5
+ 805ff098ce3ed14b
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+ 7b813bf15120fbc8
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+VPADDD_256(reg)
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+ de62d56351fe96da
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+VPADDD_256(reg)
+ before
+ e76fcc086aeb0414.a9cd126c0869c6a0.9cdd1a32cd007ff7.daac12cf3a64acbd
+ 6fa194a173e020c0.ede3baf27b7b85bb.d973ba438b80fdb5.56878af3ad4a4cb8
+ d444299809682589.6787a06c436d8e39.8514e93e478d067a.5a4ac156a6cb98bf
+ 71a4885bc70f501c.f18441c67d4b9e45.fa0ba48e9db3d6f2.c0c135e244f24dfe
+ 65b86284a1cb27a3
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+ 6fa194a173e020c0.ede3baf27b7b85bb.d973ba438b80fdb5.56878af3ad4a4cb8
+ d444299809682589.6787a06c436d8e39.8514e93e478d067a.5a4ac156a6cb98bf
+ 71a4885bc70f501c.f18441c67d4b9e45.fa0ba48e9db3d6f2.c0c135e244f24dfe
+ 65b86284a1cb27a3
+VPADDD_256(mem)
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+ 26fbc229d962e2d7.a20cab554a62dd24.68a718ec4422710c.95a6e59e2a7fabcb
+ dd55d3bb09c439c9.c3ca90f22dec084f.a9bca1cab4fdc2ba.b330aadc8a7cbfaf
+ 67940f284cfce9a3.3028339e0d3a0c46.8e8f584ceae94e7a.aef4eeb358364f4a
+ a082f55bbf17ae91.45738ec585d726b8.f4ecb95e02f1d179.e33fad8f313a9649
+ af5de4ddb013d258
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+ dd55d3bb09c439c9.c3ca90f22dec084f.a9bca1cab4fdc2ba.b330aadc8a7cbfaf
+ 045195e4e3271ca0.65d73c47784ee573.1263bab6f92033c6.48d7907ab4fc6b7a
+ a082f55bbf17ae91.45738ec585d726b8.f4ecb95e02f1d179.e33fad8f313a9649
+ af5de4ddb013d258
+
+VPMOVZXWD_256(reg)
+ before
+ 6c9a8e07714d3d22.64ecfe407d2043c1.5df79fd3324f914f.b79f41ec172107e2
+ 7742a77a11751354.8f9ea7c3a323665c.d6006035af2e8bb7.b3736be34585abe2
+ 2ca02ba32b169299.fd646dd04c2dd191.0bd9cf5599014e9d.c435b32da92a7aa5
+ e70216ec5cbcf49e.8a09cb539549408a.57d0e8a18b5417ad.c6b295b85f1c3056
+ 95b48e6f81658922
+ after
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+ 00000bd90000cf55.0000990100004e9d.0000c4350000b32d.0000a92a00007aa5
+ 2ca02ba32b169299.fd646dd04c2dd191.0bd9cf5599014e9d.c435b32da92a7aa5
+ e70216ec5cbcf49e.8a09cb539549408a.57d0e8a18b5417ad.c6b295b85f1c3056
+ 95b48e6f81658922
+VPMOVZXWD_256(mem)
+ before
+ 0d07193d2e134034.05b265c33ff4760f.125b3d3899837173.182fa58322b12192
+ 0a79b210803112b9.e0fd139371495497.7124406c74e81e7a.a9430469f9a6aaf9
+ 68d5d5d393ccbadd.d52f1cc78e47c9e3.83314ed9438203c8.655800beacbeec8e
+ 03e6fe7283eff6cb.40947ccd307b129e.244ee56d2260de8c.aaba95edd88623fc
+ d2b5bf6419898df0
+ after
+ 0d07193d2e134034.05b265c33ff4760f.125b3d3899837173.182fa58322b12192
+ 0000125b00003d38.0000998300007173.0000182f0000a583.000022b100002192
+ 68d5d5d393ccbadd.d52f1cc78e47c9e3.83314ed9438203c8.655800beacbeec8e
+ 03e6fe7283eff6cb.40947ccd307b129e.244ee56d2260de8c.aaba95edd88623fc
+ d2b5bf6419898df0
+
+VPMOVZXWD_256(reg)
+ before
+ 3b947b8f0a536415.b779aada6ea680b0.7d772f10f5706b75.304780122c8b69f0
+ 3fa5c4d84771e518.605a54f56dfe15b7.e82632fc79b30f14.83e79bb67d116120
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+ 8c88ed7717d6d466.003692f81dbe4ede.b71315802c502c58.6d5043a8665c8797
+ bdb0c6ce36392d36
+ after
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+ 0000ddeb000080fe.000057ce00003c26.0000f9fc0000b344.000032fe00008249
+ 3b3296ac6d6e4ba4.d95578b09e02700d.ddeb80fe57ce3c26.f9fcb34432fe8249
+ 8c88ed7717d6d466.003692f81dbe4ede.b71315802c502c58.6d5043a8665c8797
+ bdb0c6ce36392d36
+VPMOVZXWD_256(mem)
+ before
+ c4e8bba2bda13050.8cf3c5a6e236ba0a.b0c81fb7053f6b55.d4eaedef93c21b55
+ 5dc49b10189f4c14.98bf1ba36919393b.c4d999db7390839e.8fbc05b829b247ca
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+ ba97106bb88dbd45.45a92ebc1d99f6f6.8da34afe4ed3935a.4f80e2044f3a41cb
+ 0b0b9f6018e987ae
+ after
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+ 0000b0c800001fb7.0000053f00006b55.0000d4ea0000edef.000093c200001b55
+ 6610e404623f3cac.0d37eadc490b8fa6.1a337e4f82bd51e7.44d5584589abea63
+ ba97106bb88dbd45.45a92ebc1d99f6f6.8da34afe4ed3935a.4f80e2044f3a41cb
+ 0b0b9f6018e987ae
+
+VPMOVZXWD_256(reg)
+ before
+ d6c08bc57f47f9ba.34279d2f35968b0a.9d5fe4af824eabd8.f8f577d6f4dd0223
+ 0beca39f21ddd399.b28a073ef6656128.71a6062013b6eaf8.39f583c290e85d6f
+ 05dbe25a9a3951f7.0e8dc8821606fcca.1eca927d6d5eee01.2a6fe8ae3cfe5e6a
+ 22d9446284e6ae81.26fc5ee9b286181e.fe1783322bd1f4a0.a92e2587172ec23f
+ 90ffb3373b81451b
+ after
+ d6c08bc57f47f9ba.34279d2f35968b0a.9d5fe4af824eabd8.f8f577d6f4dd0223
+ 00001eca0000927d.00006d5e0000ee01.00002a6f0000e8ae.00003cfe00005e6a
+ 05dbe25a9a3951f7.0e8dc8821606fcca.1eca927d6d5eee01.2a6fe8ae3cfe5e6a
+ 22d9446284e6ae81.26fc5ee9b286181e.fe1783322bd1f4a0.a92e2587172ec23f
+ 90ffb3373b81451b
+VPMOVZXWD_256(mem)
+ before
+ bdaf0fabc405a22a.bd31c5237e7128e3.d4a3445ee5f0714d.6ed9d5a9ea9b3880
+ 0a08b6d0cfc59797.3131620a2265f8c8.f64df6cdcb51c286.ca5b844f4549f54e
+ 55d7239077cddd8e.dc2316810c4e5ddd.66c8f02281b3c8f2.6eeb8d90d86668b6
+ 78e7d2d9d92a333d.1854ddf6d8b991ce.01deaf4923243fc0.b6d3ebd9407ecd63
+ fe609a94181e6002
+ after
+ bdaf0fabc405a22a.bd31c5237e7128e3.d4a3445ee5f0714d.6ed9d5a9ea9b3880
+ 0000d4a30000445e.0000e5f00000714d.00006ed90000d5a9.0000ea9b00003880
+ 55d7239077cddd8e.dc2316810c4e5ddd.66c8f02281b3c8f2.6eeb8d90d86668b6
+ 78e7d2d9d92a333d.1854ddf6d8b991ce.01deaf4923243fc0.b6d3ebd9407ecd63
+ fe609a94181e6002
+
+VPMOVZXBW_256(reg)
+ before
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+ fe98dc158b24fec4.bafee7b33811fa6d.b7a39486894259f1.290e68be98626e2d
+ 6ddc67b25da28240.909c451c6eb3e447.d1587d7aa579647d.6dc05be3a4469f24
+ 4df433720fd7245d.afacd5bdced9cd88.ee7d691b14613094.4d3d038a0b69312c
+ a353dba0ead5df70
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+ 00d10058007d007a.00a500790064007d.006d00c0005b00e3.00a40046009f0024
+ 6ddc67b25da28240.909c451c6eb3e447.d1587d7aa579647d.6dc05be3a4469f24
+ 4df433720fd7245d.afacd5bdced9cd88.ee7d691b14613094.4d3d038a0b69312c
+ a353dba0ead5df70
+VPMOVZXBW_256(mem)
+ before
+ 4ccc5e105c99661d.f92e3cc13e4f1fc8.f3fa1382738f705b.685c54d57186f6e2
+ 24750ac67ebe825f.cdd47e0b8597b02c.38527c577ae28aed.9c423a145875f514
+ 071b5bad6b52ee61.2533f6bc813a1336.5b808a28feded669.e77b184466b967d6
+ d187cbb340606850.5c979f40cdc58392.364fbbe21b8d12fc.a353e8d137de89d3
+ 2d16a827667197b8
+ after
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+ 00f300fa00130082.0073008f0070005b.0068005c005400d5.0071008600f600e2
+ 071b5bad6b52ee61.2533f6bc813a1336.5b808a28feded669.e77b184466b967d6
+ d187cbb340606850.5c979f40cdc58392.364fbbe21b8d12fc.a353e8d137de89d3
+ 2d16a827667197b8
+
+VPMOVZXBW_256(reg)
+ before
+ e11053b38ffdcd30.5e88d8c318f5aa57.d04b750405c33deb.a68d8a6feefdf8d2
+ 1b8ce6e04f0e66e8.8ae9fdca101c70a3.dc9d7472c7c07dee.870474bd92394516
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+ 913db0cc02f1b3c7.2ff97f68cd517cb9.2b46de0152e87ea0.0ccf8549bf47029a
+ 68bca55e8030eb32
+ after
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+ 00db00d7009800f8.00ac0048007f0046.00b5008100f300b7.0024004e00b400f5
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+ 913db0cc02f1b3c7.2ff97f68cd517cb9.2b46de0152e87ea0.0ccf8549bf47029a
+ 68bca55e8030eb32
+VPMOVZXBW_256(mem)
+ before
+ a513cfe482162be8.850ae0642ddae046.6041d5d9cb7738db.263641f8552cb7a7
+ 9e9f80c6e2047dea.6f8ae74d5f7960b4.a01933ef595f6af1.2af3bd4b509e6608
+ 312d32f1bb069e61.ab09c2f3335970be.cb4d15989216cc28.91c94f65dfccc66f
+ 3989634f2a294a7c.95d26cc246074b10.bda9f7bf92a71bac.b903f1b29f411487
+ fcefa19f2c8a8cfd
+ after
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+ 0060004100d500d9.00cb0077003800db.00260036004100f8.0055002c00b700a7
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+ 3989634f2a294a7c.95d26cc246074b10.bda9f7bf92a71bac.b903f1b29f411487
+ fcefa19f2c8a8cfd
+
+VPMOVZXBW_256(reg)
+ before
+ b8d75a9620326a7d.927f8ecd4a783d65.8932e026330d2e55.52f8564f761e13a8
+ 470818041ac5e9b2.18db305838ff3248.e3761d8b97fa553a.6508ac365a886f48
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+ 527594f68adebded.1af4c541ebe715af.39d4db0931b25e92.7a9632b68f624628
+ 32ad5a2818eb39be
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+ 00ff00e8001c005e.000d005700fc006a.00d400a30077005f.005800f000ec00ba
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+ 527594f68adebded.1af4c541ebe715af.39d4db0931b25e92.7a9632b68f624628
+ 32ad5a2818eb39be
+VPMOVZXBW_256(mem)
+ before
+ dab3699f129680a9.85484a52397b894a.4f49b178e95f7a8a.ed8854faa096b85e
+ 4d76dd08966fd815.fc95f5d55c34e70e.2034036b2540d210.764f859cf68f4679
+ 66c03150c383fd2d.13a692ea909413e3.6b813705ba95d96d.32746a5ace2a448f
+ 035ee161b2ddaa1e.27c81bff70274976.0afcca34c46a4acc.7c44fda2c4f3ed4e
+ b00b3cdf75747e60
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+ 004f004900b10078.00e9005f007a008a.00ed0088005400fa.00a0009600b8005e
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+ 035ee161b2ddaa1e.27c81bff70274976.0afcca34c46a4acc.7c44fda2c4f3ed4e
+ b00b3cdf75747e60
+
+VPBLENDVB_256(reg)
+ before
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+ d2bc96d6b1a87f5b.c30eedfc43f567c8.7be936badd663098.0aa27329b5b3ecd2
+ 37f62011aebf77d2
+VPBLENDVB_256(mem)
+ before
+ e0401415c692d5dd.fbc9f1302bfc1b23.d243aed4a862c488.ded3251e3f2e1bf3
+ e34bca20163ac21e.3795df0806520647.8d94b3ff795f1228.6597ea0af6727713
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+ 62d86d00d43737f5.549a65de5531bc50.72bb7bf9cc326fbb.4fd7e326d29b7454
+ 6aed102f2e988dcd
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+ e34bca20163ac21e.3795df0806520647.8d94b3ff795f1228.6597ea0af6727713
+ e340ca20c63ac2dd.37c9df3006521b47.8d43b3d4a85f1288.65d3250a3f2e7713
+ 62d86d00d43737f5.549a65de5531bc50.72bb7bf9cc326fbb.4fd7e326d29b7454
+ 6aed102f2e988dcd
+
+VPBLENDVB_256(reg)
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+ 35954eb164b81a01.5d181eb0d13422c0.35a6a7f8600f343f.11658d574d95c3f7
+ 88c900901dc5368c
+VPBLENDVB_256(mem)
+ before
+ 8aa9987b39e47961.cccf2d05af86747e.dec1b4c5c4fa8650.fefa2b0bfdbeddb4
+ f3d1cf04bdfd4aa3.c38dbdaccabb5bcc.988bec41d1f55876.ba6d23fbddcfb6e4
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+ 6a280fa06b4f801c.40c9e0a4e28cc38e.27b63222a6b73935.76df5c23d344e727
+ 2f76953322c0b892
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+ f3d1cf04bdfd4aa3.c38dbdaccabb5bcc.988bec41d1f55876.ba6d23fbddcfb6e4
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+ 6a280fa06b4f801c.40c9e0a4e28cc38e.27b63222a6b73935.76df5c23d344e727
+ 2f76953322c0b892
+
+VPBLENDVB_256(reg)
+ before
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+ 1ab8e17b2178e568
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+ 7fe0332c6ed78e2a.fc4561d270bed6b6.8a8cc509a7178875.c1b1aa5552bf7b54
+ 1ab8e17b2178e568
+VPBLENDVB_256(mem)
+ before
+ 8c419b68e9c69d73.bafa353551a25467.46b48a7dd8000fc0.313cbec68670df4e
+ f3185309c7b360a0.23de85e7f3ba676c.d7ca3327879cb597.17d247361590a45a
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+ 0fe0ad1832a0f513.ef3804f7e2035f7c.3d1ff6252d13375a.14dcfee0b45668b5
+ e2e823f1fc15de5d
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+ f3185309c7b360a0.23de85e7f3ba676c.d7ca3327879cb597.17d247361590a45a
+ f3419b09c7c69da0.bade853551ba676c.d7ca8a27879cb597.173cbec68690a44e
+ 0fe0ad1832a0f513.ef3804f7e2035f7c.3d1ff6252d13375a.14dcfee0b45668b5
+ e2e823f1fc15de5d
+
+VPMINSD_256(reg)
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+ c0b48a0655b1d345
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+ 48e3f1cf4820c03b
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+VPMINSD_256(reg)
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+ 2d0fa3c734a93060
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+VPMINSD_256(reg)
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+VPMAXSD_256(reg)
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+VPMAXSD_256(reg)
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+VPMAXSD_256(reg)
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+ 53ac1abaaba25024
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+ a6368e1cc3188fca
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+VPSHUFB_256(reg)
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+ cbc7d36dc1d5402f
+VPSHUFB_256(mem)
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+ 3fad6a0b2cb38936
+
+VPSHUFB_256(reg)
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+ 9e0a48b8c8011cc8
+VPSHUFB_256(mem)
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+ 5b8587b3952b0921.765d9b3d8cf2e62a.dcdeda3442e5c8ed.b59e4ea568df2b44
+ 00000000b3000000.005b0000005d0000.c80000a500dfc800.000000002b00c800
+ 1b276fefe9c6d174.2ef9b0a22bd197c3.76de3baf5fdb8ce1.2ebbabf3470db878
+ 62988b5f5746fb94
+
+VPSHUFB_256(reg)
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+ a26641cf5aff34ce
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+ 0bb64f05552e696e.2762baa7a1d0708a.d50420276581181f.0f0b8f5d0353bc2f
+ a26641cf5aff34ce
+VPSHUFB_256(mem)
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+ 6a8f11cbec2196ce.cfd2893ae6ff22b4.33bbdde4c7ff080c.84323c09c110a7a3
+ 0000e6b496000021.cf0011ce6a000021.00a309c100a33300.00bbbb000000a73c
+ 6ef8025fbb4dcba1.b32227dc5a8cb261.c3bb28e1f220fb09.9bfcc47ec7469435
+ d399277fd05ca4f2
+
+VPUNPCKLBW_256(reg)
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+ 892d6649f507b77e
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+ 997223d4fcb4b3e7.a908c6d194412d3c.5bdb13e5665fd76e.ee30ba9cd9b572f2
+ 892d6649f507b77e
+VPUNPCKLBW_256(mem)
+ before
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+ 0baa45fb18692c7b.3f0f2ce5b8203000.a06e5a6e5dc91ac6.de05200cbf652c8e
+ a9c470d95890d444.86b5a6a102107e8e.f40422303b1b9254.ae17ffe2435999be
+ 007fbd9e326c6c23.3ef813ba0fe17c57.53958e24e4db5aa2.02e2121f7aa8d894
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+ 0baa45fb18692c7b.3f0f2ce5b8203000.a06e5a6e5dc91ac6.de05200cbf652c8e
+ 0f3fbd0faa2c1ae5.95b8852055300200.37de60057b20310c.55bf4065552c578e
+ 007fbd9e326c6c23.3ef813ba0fe17c57.53958e24e4db5aa2.02e2121f7aa8d894
+ 36b2573003de24bc
+
+VPUNPCKLBW_256(reg)
+ before
+ a5d2c97f7788bae1.eca9a838c108ae44.c4276f9d7a206608.9aed1b36751530dd
+ ad90647a7432d6af.490cad91217056d5.748db6b4df58784c.a3da435209d5ce30
+ a936258b9666b4d4.f37549976fb022ff.aa75e46ddb16edd0.4b278464bc28f0c8
+ f411072078b28ffa.c6b0f635c6d5ccf1.c32cf63309e40240.6e9f5a58ac1a54d1
+ e80f3f1bf2b5b476
+ after
+ f349750c49ad9791.6f21b0702256ffd5.4ba327da84436452.bc0928d5f0cec830
+ ad90647a7432d6af.490cad91217056d5.748db6b4df58784c.a3da435209d5ce30
+ a936258b9666b4d4.f37549976fb022ff.aa75e46ddb16edd0.4b278464bc28f0c8
+ f411072078b28ffa.c6b0f635c6d5ccf1.c32cf63309e40240.6e9f5a58ac1a54d1
+ e80f3f1bf2b5b476
+VPUNPCKLBW_256(mem)
+ before
+ 9444b197ac07cce3.ec6d05a4b6a1a4cd.9e88325743eb11d5.19fee7710650f247
+ 50072abaf61c5a46.eb961e83edc02ffa.57cb79e901fcadd7.0937b3956de6fb92
+ f727286eebfe18c9.4fd84b29b99a6b2d.cd4345d71d165b24.ef23560adb3157cc
+ 656f27a1a7bbc398.727e8a02b5bb9511.dbbd140db245d8e8.270ecc3cebbd43a2
+ 0d4312973a16fac0
+ after
+ 9444b197ac07cce3.ec6d05a4b6a1a4cd.9e88325743eb11d5.19fee7710650f247
+ 50072abaf61c5a46.eb961e83edc02ffa.57cb79e901fcadd7.0937b3956de6fb92
+ eceb6d96051ea483.b6eda1c0a42fcdfa.1909fe37e7b37195.066d50e6f2fb4792
+ 656f27a1a7bbc398.727e8a02b5bb9511.dbbd140db245d8e8.270ecc3cebbd43a2
+ 0d4312973a16fac0
+
+VPUNPCKLBW_256(reg)
+ before
+ fd0f238763c9b9d1.76aaa13e475e17e0.b2d6d57a7db0e953.5f056177dd93e04f
+ 52bffb790361bc82.06a61431e6f4cfcd.692a2afdae04a39e.34e7a802b90e2f84
+ 6a9d96d7b56b3f7e.f02dfb66a188a88b.f4c785f8e443fea0.362f659862c280b3
+ a0f5f10f15717d72.120cd2c993275e44.b0f9e0d5b9fa3702.41a91527f6b99009
+ 302032998e011bb2
+ after
+ f0062da6fb146631.a1e688f4a8cf8bcd.36342fe765a89802.62b9c20e802fb384
+ 52bffb790361bc82.06a61431e6f4cfcd.692a2afdae04a39e.34e7a802b90e2f84
+ 6a9d96d7b56b3f7e.f02dfb66a188a88b.f4c785f8e443fea0.362f659862c280b3
+ a0f5f10f15717d72.120cd2c993275e44.b0f9e0d5b9fa3702.41a91527f6b99009
+ 302032998e011bb2
+VPUNPCKLBW_256(mem)
+ before
+ e1613adc48a6dcd9.5015078bc002b309.470f1546d9dbad27.f70c3901ccb48a72
+ 2f38a8db40b290ab.d648d4b952a71df1.6a0141c98eb2505e.264b8be9b6fd329c
+ f571f9829134f354.8dd9540466eef7d3.59b0d13fcfb80416.9a04d2f816626c2c
+ 11d8a7bd5735c0ff.d31583d898627c5e.efe64192b7f7857a.ad810a9a856e74cd
+ bc0f303ba1ad862b
+ after
+ e1613adc48a6dcd9.5015078bc002b309.470f1546d9dbad27.f70c3901ccb48a72
+ 2f38a8db40b290ab.d648d4b952a71df1.6a0141c98eb2505e.264b8be9b6fd329c
+ 50d6154807d48bb9.c05202a7b31d09f1.f7260c4b398b01e9.ccb6b4fd8a32729c
+ 11d8a7bd5735c0ff.d31583d898627c5e.efe64192b7f7857a.ad810a9a856e74cd
+ bc0f303ba1ad862b
+
+VPUNPCKHBW_256(reg)
+ before
+ 23fa3e4706acddf4.5d393078afc3b5d8.03485ea08590e93c.07700db0637e8eb7
+ 3e8e322a4ff6b6d1.b75f0f9fb4e98c0d.78bee0cbc8037a19.7f1bb183ee56dcf9
+ 6917085019174d71.f918c11e83b301c8.90c305c2fe476aa2.31b0aaf9758d2b6b
+ 00e0ba25ff9cdd7e.012ec0e2372ed235.a6a3c9f2c2e8f683.fbfe73fd132e3739
+ b7d0887be445bb91
+ after
+ 693e178e0832502a.194f17f64db671d1.9078c3be05e0c2cb.fec847036a7aa219
+ 3e8e322a4ff6b6d1.b75f0f9fb4e98c0d.78bee0cbc8037a19.7f1bb183ee56dcf9
+ 6917085019174d71.f918c11e83b301c8.90c305c2fe476aa2.31b0aaf9758d2b6b
+ 00e0ba25ff9cdd7e.012ec0e2372ed235.a6a3c9f2c2e8f683.fbfe73fd132e3739
+ b7d0887be445bb91
+VPUNPCKHBW_256(mem)
+ before
+ 42f1655f05df749c.5f3646169d10a4a4.a96e8ad5ed65b981.15a929c7b1735a67
+ 792f879592071e89.e266a78d90ffdc91.cea49ae5c06573d8.3b2220ae6674d2fb
+ 36546909a6ca7482.e5bad9f874f6c1ee.4d9b6cfdcd38bc65.725aaa117e7599eb
+ 562d87a75d3333b4.c47fd8c1e480916a.00217c082fed4f55.189dc35e9404ece2
+ 8737670045ac078c
+ after
+ 42f1655f05df749c.5f3646169d10a4a4.a96e8ad5ed65b981.15a929c7b1735a67
+ 792f879592071e89.e266a78d90ffdc91.cea49ae5c06573d8.3b2220ae6674d2fb
+ 4279f12f65875f95.0592df07741e9c89.a9ce6ea48a9ad5e5.edc06565b97381d8
+ 562d87a75d3333b4.c47fd8c1e480916a.00217c082fed4f55.189dc35e9404ece2
+ 8737670045ac078c
+
+VPUNPCKHBW_256(reg)
+ before
+ 1c7493622cfa2597.b6855d5cd44e174a.db00a0567c2a86af.c40047f4038de9d3
+ 349f42f2e67983ac.302a67122627dc71.868b2e22d97fdd69.760648ac6426460c
+ 2906701b0eb55d7a.a1e722b770cb3d54.216a7d91960bd145.f0fdfb1c6ec3212c
+ 58f31949403befab.e5870936cd45f720.08eb890f505a9fef.0fb2dc303e71375e
+ aff067d5f03b44cf
+ after
+ 2934069f70421bf2.0ee6b5795d837aac.21866a8b7d2e9122.96d90b7fd1dd4569
+ 349f42f2e67983ac.302a67122627dc71.868b2e22d97fdd69.760648ac6426460c
+ 2906701b0eb55d7a.a1e722b770cb3d54.216a7d91960bd145.f0fdfb1c6ec3212c
+ 58f31949403befab.e5870936cd45f720.08eb890f505a9fef.0fb2dc303e71375e
+ aff067d5f03b44cf
+VPUNPCKHBW_256(mem)
+ before
+ ac8519f59f2d04ab.1eb33ae9199674ec.d8d7987a5aa2c601.96584f08a2f98312
+ e23b6d7d6753321d.d592cd65355229e8.56a34b7132ed6522.29fec9e82973b95b
+ 2de0df5a65ba8b51.dadbd02a2efc4a4c.3cb79f06723292b0.1c28f51c80557c76
+ 6a3eec76b56ecb74.89dc3ea5a31f12c3.64df0e25357e07d6.cb24ce0e442a090e
+ 913d502c107e9cd0
+ after
+ ac8519f59f2d04ab.1eb33ae9199674ec.d8d7987a5aa2c601.96584f08a2f98312
+ e23b6d7d6753321d.d592cd65355229e8.56a34b7132ed6522.29fec9e82973b95b
+ ace2853b196df57d.9f672d530432ab1d.d856d7a3984b7a71.5a32a2edc6650122
+ 6a3eec76b56ecb74.89dc3ea5a31f12c3.64df0e25357e07d6.cb24ce0e442a090e
+ 913d502c107e9cd0
+
+VPUNPCKHBW_256(reg)
+ before
+ ccbe78e080dd7167.73220ebf7179adb2.3edf14402e48bffa.abe616bb98dc80c1
+ d6f4419831d4c380.2458c320b8e9ef36.55324c696b018a9d.ed9a32b2b658bb9d
+ 0d2ba7bfbfefcfc7.5bab8685a4c94b2d.2a1fe48bf7d8b257.06c5dff7abfe7295
+ cbafa6c1c5b8d1e7.f3e9d3da51267dc3.19f3d7116d5971d5.d234977794db61d6
+ 2cb3d81c8dfb468b
+ after
+ 0dd62bf4a741bf98.bf31efd4cfc3c780.2a551f32e44c8b69.f76bd801b28a579d
+ d6f4419831d4c380.2458c320b8e9ef36.55324c696b018a9d.ed9a32b2b658bb9d
+ 0d2ba7bfbfefcfc7.5bab8685a4c94b2d.2a1fe48bf7d8b257.06c5dff7abfe7295
+ cbafa6c1c5b8d1e7.f3e9d3da51267dc3.19f3d7116d5971d5.d234977794db61d6
+ 2cb3d81c8dfb468b
+VPUNPCKHBW_256(mem)
+ before
+ f20e1dd4b168dbe1.6ecc3a09dfbd048c.c8dc260bdc0b4323.7ef922696a0f05c2
+ ff10e3891c30dd04.50cd6006aa89a564.b651fc046084577a.b57fbffe8986a7cb
+ 2f87a429eb5f081f.cfff1221c2a9f018.9914d0b1f99e76f3.1acfac3d674a969c
+ 5e3dde9f39ff175e.45af4ec7c2a82157.4df11effc5645bbb.0937e4909fe80ce0
+ de016364cdeb4644
+ after
+ f20e1dd4b168dbe1.6ecc3a09dfbd048c.c8dc260bdc0b4323.7ef922696a0f05c2
+ ff10e3891c30dd04.50cd6006aa89a564.b651fc046084577a.b57fbffe8986a7cb
+ f2ff0e101de3d489.b11c6830dbdde104.c8b6dc5126fc0b04.dc600b844357237a
+ 5e3dde9f39ff175e.45af4ec7c2a82157.4df11effc5645bbb.0937e4909fe80ce0
+ de016364cdeb4644
+
+VPABSD_256(reg)
+ before
+ f57a25258fdf8073.67ff0cd7231ec7ef.10271064461273cb.adb462d8dde2c3fe
+ aaee27407e51f51a.2899aabdc5c8d4fc.8ab45265eb742321.9729192a5f256ae7
+ 59a8632038cce2e4.7cd7343d3907fab1.10a112344c596d04.e61bbedf67380ca3
+ 5df6d73059dd837e.3e8527449ee9f43b.ff3c4b3f064d8c21.7557cde51027645d
+ 22a9c22776ff3042
+ after
+ f57a25258fdf8073.67ff0cd7231ec7ef.10271064461273cb.adb462d8dde2c3fe
+ 59a8632038cce2e4.7cd7343d3907fab1.10a112344c596d04.19e4412167380ca3
+ 59a8632038cce2e4.7cd7343d3907fab1.10a112344c596d04.e61bbedf67380ca3
+ 5df6d73059dd837e.3e8527449ee9f43b.ff3c4b3f064d8c21.7557cde51027645d
+ 22a9c22776ff3042
+VPABSD_256(mem)
+ before
+ c8dd1991b6cb297d.14227fde7c0f1494.4c6efdbc0d7a7fc6.b1cff9f1b4ddbe23
+ 42bf4f0fec980e3b.d97955953deed0d2.81603593a4c5577d.83a818b6f3943cb7
+ 6e1bdf8d327099a8.084857c13907f4e2.b82548b37fd6378d.d111a5f95efe4589
+ 26bc45f7a76187ef.fcd880ce0be4bb73.cf8ab30ab9b9dc22.f7579b2891a81344
+ 51c6f6af2a1de395
+ after
+ c8dd1991b6cb297d.14227fde7c0f1494.4c6efdbc0d7a7fc6.b1cff9f1b4ddbe23
+ 3722e66f4934d683.14227fde7c0f1494.4c6efdbc0d7a7fc6.4e30060f4b2241dd
+ 6e1bdf8d327099a8.084857c13907f4e2.b82548b37fd6378d.d111a5f95efe4589
+ 26bc45f7a76187ef.fcd880ce0be4bb73.cf8ab30ab9b9dc22.f7579b2891a81344
+ 51c6f6af2a1de395
+
+VPABSD_256(reg)
+ before
+ 3ca9b2f8c2eaf127.4870fd3a6577943d.1378cc285014632f.a05bf3836f7b0267
+ 124ecb70f79979a7.ae01844088bd7bbe.a773373ba32026c3.09648309bc276589
+ 30ff3e8365b8b6c1.363c54f62d3ffa9d.1614be74a19641da.e470df8abcc9c0b3
+ f209069ea7d3e520.baedeb496f09ca07.baa85b3de501ef21.0e4d83f18c6ed012
+ 64c5ec2b482151d1
+ after
+ 3ca9b2f8c2eaf127.4870fd3a6577943d.1378cc285014632f.a05bf3836f7b0267
+ 30ff3e8365b8b6c1.363c54f62d3ffa9d.1614be745e69be26.1b8f207643363f4d
+ 30ff3e8365b8b6c1.363c54f62d3ffa9d.1614be74a19641da.e470df8abcc9c0b3
+ f209069ea7d3e520.baedeb496f09ca07.baa85b3de501ef21.0e4d83f18c6ed012
+ 64c5ec2b482151d1
+VPABSD_256(mem)
+ before
+ c0a594220beffe1d.b4b81f2b59754171.17dfc4246b28aa27.f17c0c040cee6e43
+ ffb9f9c3f1e39422.d2588598182a085f.2ae05c723ca7542a.15dacc33b1e8f8ee
+ fecd97fa1709cf0b.a73535507f7e7497.cdba2d21fe93853b.840e9838717bc9cb
+ 97ade8b4986d6b05.919b29bf2bfec2c5.dd3bb51ccef7f987.98666b7ee7341f88
+ ae2d4071b09e34d1
+ after
+ c0a594220beffe1d.b4b81f2b59754171.17dfc4246b28aa27.f17c0c040cee6e43
+ 3f5a6bde0beffe1d.4b47e0d559754171.17dfc4246b28aa27.0e83f3fc0cee6e43
+ fecd97fa1709cf0b.a73535507f7e7497.cdba2d21fe93853b.840e9838717bc9cb
+ 97ade8b4986d6b05.919b29bf2bfec2c5.dd3bb51ccef7f987.98666b7ee7341f88
+ ae2d4071b09e34d1
+
+VPABSD_256(reg)
+ before
+ 23ae157d67454552.a7246adc911c233b.ebd55f51b7352d94.362d6f4fc8df6c3a
+ 5136e60ea8b68eb6.0aff985d1d21b4da.1130d272c0b0f3b1.b55dd7a60757997f
+ 9511ad90107c4aa9.9c0bee255989da0e.5ff87f8ee1fa4dc7.34966a0ea86c3d83
+ 4c8b686f3a23b6d9.3a12e81f605f5002.30796011b79f7a83.90a6a371c6291371
+ a557fdbc7d9bd976
+ after
+ 23ae157d67454552.a7246adc911c233b.ebd55f51b7352d94.362d6f4fc8df6c3a
+ 6aee5270107c4aa9.63f411db5989da0e.5ff87f8e1e05b239.34966a0e5793c27d
+ 9511ad90107c4aa9.9c0bee255989da0e.5ff87f8ee1fa4dc7.34966a0ea86c3d83
+ 4c8b686f3a23b6d9.3a12e81f605f5002.30796011b79f7a83.90a6a371c6291371
+ a557fdbc7d9bd976
+VPABSD_256(mem)
+ before
+ 4f77f7dceacd49be.d0f01218c3380ef0.bee102374fafd4e3.e2ff7367dd2bb590
+ 6ad00abc28cb1f74.7e8ba7f547468d9a.0543b959418620dc.d0d6b3fdf02b399c
+ d22fb34754a219c5.b2aa237461d97084.eb06887153eff01a.56491d3d8b2a4350
+ 63606f6b895df1dc.c89783ffad7ef35a.4cf4eb6ba0f602c9.cfa6ab954bb50e5b
+ 99375b70cb57d766
+ after
+ 4f77f7dceacd49be.d0f01218c3380ef0.bee102374fafd4e3.e2ff7367dd2bb590
+ 4f77f7dc1532b642.2f0fede83cc7f110.411efdc94fafd4e3.1d008c9922d44a70
+ d22fb34754a219c5.b2aa237461d97084.eb06887153eff01a.56491d3d8b2a4350
+ 63606f6b895df1dc.c89783ffad7ef35a.4cf4eb6ba0f602c9.cfa6ab954bb50e5b
+ 99375b70cb57d766
+
+VPACKUSWB_256(reg)
+ before
+ 0e492839a79cda20.f92eb913e40864e6.1c9fc204c8c052c7.04da5f3444a81014
+ 8c280e5e7c115333.70670d2b81b02e0f.0a0edcee4d2cc878.ef855eb65c10d628
+ 6d1f094ae6417d4c.a4d5e89f7a600a82.ee30cd29d94c9218.e8bf66df043a1230
+ 0f7c166980b89616.7145c55bed24b56c.2450922107afec54.cd54f29957327e59
+ 79127ed27105d7cf
+ after
+ ffff0000ff000000.00ffffffffff00ff.ff00ff000000ffff.ff00ff0000ffff00
+ 8c280e5e7c115333.70670d2b81b02e0f.0a0edcee4d2cc878.ef855eb65c10d628
+ 6d1f094ae6417d4c.a4d5e89f7a600a82.ee30cd29d94c9218.e8bf66df043a1230
+ 0f7c166980b89616.7145c55bed24b56c.2450922107afec54.cd54f29957327e59
+ 79127ed27105d7cf
+VPACKUSWB_256(mem)
+ before
+ c8c387756fbfd9bd.cc893028e602d73e.b2831f4bf609ebf8.08bc254274de12d8
+ 9635886e6d6a3f50.029353f1b5ac7f6f.455b745cb01a6853.f6be84f8bb673f4f
+ be32fda98514c6b3.0be77b318842c856.059940783863e7a8.4aa3aaaf78d5b065
+ 1e876212d6c92a13.44cea455fc4eef9f.ce09fd8da9f12525.60b794d448b4a0c8
+ 94463cd1c7914d22
+ after
+ c8c387756fbfd9bd.cc893028e602d73e.b2831f4bf609ebf8.08bc254274de12d8
+ 9635886e6d6a3f50.029353f1b5ac7f6f.455b745cb01a6853.f6be84f8bb673f4f
+ 0000ff0000ff0000.0000ffffffff00ff.00ff0000ffffffff.ffff00ff000000ff
+ 1e876212d6c92a13.44cea455fc4eef9f.ce09fd8da9f12525.60b794d448b4a0c8
+ 94463cd1c7914d22
+
+VPACKUSWB_256(reg)
+ before
+ 419ca01490f7f11f.910033957a94279b.0a97cbc7ac5e30f5.7b7629851fcfdef3
+ c504bb084073c96c.f268ed1e8d817879.b78debf535fec705.eaad3f4eb709cd41
+ 7bcc8918719010b5.1f8d0a9a2b9cdad6.a8fb004a32b8ef7b.f67abbd38dacaf39
+ bf3e07b2c2da04a6.f33908f372f209e1.392f0631401ae502.7aa91a00bcc34007
+ 5406d6c1605a3bd8
+ after
+ 00ff00ff00ffffff.0000ff00000000ff.ffffff00ffff00ff.0000ff0000ff0000
+ c504bb084073c96c.f268ed1e8d817879.b78debf535fec705.eaad3f4eb709cd41
+ 7bcc8918719010b5.1f8d0a9a2b9cdad6.a8fb004a32b8ef7b.f67abbd38dacaf39
+ bf3e07b2c2da04a6.f33908f372f209e1.392f0631401ae502.7aa91a00bcc34007
+ 5406d6c1605a3bd8
+VPACKUSWB_256(mem)
+ before
+ 5e5d6d02967e5ed8.eca72f41cddddee9.493a63177b8ec0c3.c773fa18fab0e446
+ 76795aaf7a3a6332.6053ff312e26dd2d.ff5a95f0647cbcab.ac14d76afd052af4
+ 762819b5269b0613.768d72ee82413c1c.ef651c6c49c9b9c3.455d9993e4a5f1b8
+ 3c3427feb9ab05a7.89a385e564b83663.f729737645807338.ee9c3c004c1c753e
+ 031cbc1bd0f7f431
+ after
+ 5e5d6d02967e5ed8.eca72f41cddddee9.493a63177b8ec0c3.c773fa18fab0e446
+ 76795aaf7a3a6332.6053ff312e26dd2d.ff5a95f0647cbcab.ac14d76afd052af4
+ ffff00ff00ff0000.ffffffffff00ff00.ffffff0000000000.0000ff00000000ff
+ 3c3427feb9ab05a7.89a385e564b83663.f729737645807338.ee9c3c004c1c753e
+ 031cbc1bd0f7f431
+
+VPACKUSWB_256(reg)
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+ 4f764588d0158833.cd1c203a3edd7a52.9b877bb77e0fce84.2b7e1a6eea9715e2
+ 43f43eb269a11eef.6f5df4580476fe15.c947e188f225fba0.cba393991642f012
+ e6f3a0a57d8b0bb2
+VPADDUSW_256(mem)
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+ fd4867146e28f4f5.76db8efa7a8c7e19.0a204d47c8605d1a.278154bc0d107047
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+ 50db4f1b9ccfb00a.c9f644af6c35b5a9.298bd0f8923b179a.ed553385d2a045fc
+ 1d18e1cf5b84e96a
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+ fd4867146e28f4f5.76db8efa7a8c7e19.0a204d47c8605d1a.278154bc0d107047
+ ffffffffaaa6ffff.fe82e659ffffffff.4490ffffffffbdb8.ffff8021a65cffff
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+ 1d18e1cf5b84e96a
+
+VPADDUSW_256(reg)
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+ 41078bca0492c5a6.2941027233b9202c.4f455ede773e287b.72d7d019b8471c89
+ 7529b7bfc397e477
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+ df37fbf8712136a0
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+VPMULHUW_256(reg)
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+ ebaa72e2dc772733
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+ 86ff9089fca3cac1
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+VPMULHUW_256(reg)
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+ bb8a37610426c3e4
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+VPMULHUW_256(reg)
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+VPMULHUW_256(mem)
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+ f0f16952fe5f22d7
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+VPADDUSB_256(reg)
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+ 9a87e0aecdb528fb
+VPADDUSB_256(mem)
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+ 1abdfbb76d0b4548
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+VPADDUSB_256(reg)
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+ 32c57f72207cc825.1a2c277faa8c7dfb.9ceee356a12df7f2.ccf41687fe6b6844
+ efa9f2064667303b
+VPADDUSB_256(mem)
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+ be89e66fb0620f95.8a5b559f1ba1665b.910ae00a5c40e9f9.ea499d7b50735f43
+ f778a7d83e836d98
+
+VPADDUSB_256(reg)
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+ 2c2e6dd27b8f0f27
+VPADDUSB_256(mem)
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+ 6a64c4bc1ef07876
+
+VPUNPCKLWD_256(reg)
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+ e83e02d199dcc7c7.001d73c0f085c6f8.ed62aaa3d0bc8048.499b55733db3f2da
+ 260819460804169b
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+ f74603b517463e55.656554181c3df232.4141abf98de8837e.2835678a50a47ef5
+ 362189c698dc26f0
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+VPUNPCKLWD_256(reg)
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+ 8f8a9df9690074d5
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+ 00b20dbe172f1771
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+VPUNPCKLWD_256(reg)
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+ 4b7848c9e734cbc9
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+VPUNPCKHWD_256(reg)
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+ d486c05060334f93.b036e5cc76f58690.3b6c42f286950f5f.dc3471d4a000137e
+ dda6294ff4555270
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+ 7a35126b3395a025
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+VPUNPCKHWD_256(reg)
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+ 89c4e1fd7500922d
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+ d109228b0759d612
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+VPUNPCKHWD_256(reg)
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+VPSLLD_0x05_256(reg)
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+VPSLLD_0x05_256(reg)
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+VPSLLD_0x05_256(reg)
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+VPSRLD_0x05_256(reg)
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+VPSRLD_0x05_256(reg)
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+VPSRLW_0x05_256(reg)
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+VPSLLW_0x05_256(reg)
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+VPSLLW_0x05_256(reg)
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+VPADDW_256(reg)
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+ aee47bc1ea967203
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+VPADDW_256(reg)
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+ 7d9db9f252e24845
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+ 5d4b2274ebe468fb
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+VPADDW_256(reg)
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+ 48387a3e59326169
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+ 6fb5da129769aa95
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+VPACKSSDW_256(reg)
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+VPMULUDQ_256(reg)
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+VPMULDQ_256(reg)
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+VPMULDQ_256(reg)
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+VPSLLQ_0x05_256(reg)
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+VPSLLQ_0x05_256(reg)
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+VPSLLQ_0x05_256(reg)
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+VPMAXUD_256(reg)
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+VPMAXSB_256(reg)
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+ f7f4879bdef5c3e7
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+VPSRAW_0x05_256(reg)
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+VPSRAW_0x05_256(reg)
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+VPCMPGTB_256(reg)
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+VPCMPGTB_256(reg)
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+ 3d319bc49e218468
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+VPCMPGTB_256(reg)
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+ 689b5f952fa2ddad
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+ 712e41e3990e63cc.b5aafe218c8958bf.ea26120001953acf.b0903f27a0e1bdeb
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+ 0eb7dbc218bbd435.f8d343de25c151c4.fd9961c9266924c4.d04588fad5b38ef7
+ ed1e84a6c60d399d
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+VPCMPGTW_256(reg)
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+ edefe2ad6b86f0d4
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+ a6e45890fd5fafee.07bc40e88fcaa39d.1ee1c17fda0c69ee.4f94c12f0ae997c8
+ 0000ffffffff0000.000000000000ffff.ffffffffffffffff.00000000ffff0000
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+ e55dfb09a5e82636
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+VPCMPGTW_256(reg)
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+ 073056f2e7dc2ae1
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+VPCMPGTW_256(reg)
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+ 163acdc6177206ab
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+VPCMPGTD_256(reg)
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+ 1097ddff360ee844.31087302533ba9c3.9b001a24d2c183a6.8fc184f01a463464
+ 98be9576d28a8e3a
+ after
+ 00000000ffffffff.ffffffffffffffff.ffffffff00000000.0000000000000000
+ c7a3c660b975f038.3bffd66b2efa059a.3d67881701f6bbbb.fed0fd2189c14140
+ 2b2590198ea9cc39.a8de8ab5d33be766.a2af6e820706ee76.50b525220b085975
+ 1097ddff360ee844.31087302533ba9c3.9b001a24d2c183a6.8fc184f01a463464
+ 98be9576d28a8e3a
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+ 73bdbe5bb04dad49.d176f0026d9cd02f.0271d05156a5c1df.b9ebb1bd2568c118
+ fe58cd910de5eada.647caef734dd1366.03473d2c11278ef5.961e958ce66de3b2
+ c2157f3083b29702.e9a1e0ca3d7f8658.8f99ceb917982b4c.768a2d42da4d5770
+ b77b774b9f955801
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+ 73bdbe5bb04dad49.d176f0026d9cd02f.0271d05156a5c1df.b9ebb1bd2568c118
+ ffffffff00000000.00000000ffffffff.ffffffffffffffff.ffffffffffffffff
+ c2157f3083b29702.e9a1e0ca3d7f8658.8f99ceb917982b4c.768a2d42da4d5770
+ b77b774b9f955801
+
+VPCMPGTD_256(reg)
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+ c81b0e070b8af447.6523ba552d182cc6.39788db58718eb1f.b8e14e997675c86d
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+ aa5f3b2009ac97e3.3c494d2a8cdf4bf4.a259d7262cc6e0e5.5da82e51539b789f
+ 8459b82c76682dcd
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+ 00000000ffffffff.ffffffffffffffff.ffffffff00000000.00000000ffffffff
+ c81b0e070b8af447.6523ba552d182cc6.39788db58718eb1f.b8e14e997675c86d
+ 51635492ea4f0754.fc0d3ab397ca8cba.bcc101a70026564c.0d6e34c407f9408e
+ aa5f3b2009ac97e3.3c494d2a8cdf4bf4.a259d7262cc6e0e5.5da82e51539b789f
+ 8459b82c76682dcd
+VPCMPGTD_256(mem)
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+ b6bd34179f329114.5c50d2e53af9719f.065bfe66ec13ab10.3abfc21302e3f4eb
+ 6d554da7cd8da1b2
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+ c7536e7db4b0fe30.3ba6dcf4785c2136.27e619108168d6ed.02a69e7a0aea4309
+ 00000000ffffffff.ffffffffffffffff.ffffffff00000000.00000000ffffffff
+ b6bd34179f329114.5c50d2e53af9719f.065bfe66ec13ab10.3abfc21302e3f4eb
+ 6d554da7cd8da1b2
+
+VPCMPGTD_256(reg)
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+ 348b3f039d2cf808.175e73a3006180e4.cd4e3c9d327ce734.1f4a93e4a34bb754
+ fc4296b05904d7c6
+ after
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+ cc13407b10facd46.30f5eb58184dc7db.edbdfc532de4697e.b806dc8dad3eacbd
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+ fc4296b05904d7c6
+VPCMPGTD_256(mem)
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+ 90fe9f3796fcd137.9b2fe6b01361cb98.a73c76d097f6fa3e.fe5a7a45f234f9a2
+ 9a8a255fcb043fea
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+ 54dd5623c418f6d1.84202c9f53840259.4955ac5535cf9c90.de6371232921cc20
+ ffffffffffffffff.00000000ffffffff.00000000ffffffff.ffffffffffffffff
+ 90fe9f3796fcd137.9b2fe6b01361cb98.a73c76d097f6fa3e.fe5a7a45f234f9a2
+ 9a8a255fcb043fea
+
+VPMOVZXBD_256(reg)
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+ ef748ce07a22a5ea.3fc167a419cdd15b.3f003745f13998d7.f1c9ce82ec1ea0c9
+ 13dfc32e1d376be0.34584cc0eab93691.a24040ae322b1961.67583c9f67f00021
+ 51ea76b695b95981
+VPMOVZXBD_256(mem)
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+ a44b0946826a26c8.0b01f5aef560f270.e74f9c4b563c07d5.48bf4dfef88be364
+ 843ab759a5047337
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+VPMOVZXBD_256(reg)
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+ 7d1627647491eb19.720583927a0be916.c41d24d422415704.3d12b557bd2b51db
+ 2675985a60364086.eee7b6c6ebff26b6.1905b98c423da133.79ae13c33e91135d
+ 4de89ad947f65b87
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+VPMOVZXBD_256(reg)
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+ bbde0452f0756342.6424142171b246f8.b3826317aa7d596c.3b5fd641155f5056
+ 431fbb00ebaf8a95
+VPMOVZXBD_256(mem)
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+ f07e901fb4c74b9f.dabf4809cfe82211.800f877d3972cac1.695054f63fcbf934
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+ 28ad55e70c78af8c.6962c03de1a88756.7130f3aa58b47815.d64a8379cf50c81b
+ f87547867ba4f728
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+VPMOVSXBD_256(reg)
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+ abeed036fada0807.bdf932f0e426df8d.5673d1991992c7c4.4e9a35f4173bd6da
+ e76e108f9b843688
+VPMOVSXBD_256(mem)
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+ ffffff95ffffffa8.00000004ffffffc3.ffffff84ffffffb2.0000002dffffffb0
+ fa62db00ae485e49.3d621e7251f65865.3e5c42aa5ca5227a.50ab3a3e28769e67
+ a08426c43fabe15a.7e548cb8a125149f.0102521a73ba1c98.831235669830228c
+ 6a221465ed3627c5
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+VPMOVSXBD_256(reg)
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+ 66913adc2a38aa6e
+
+VPMOVSXBD_256(reg)
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+ a72d008e0f214495
+VPMOVSXBD_256(mem)
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+ 1b07e5a4bdfbc3bf.043680eec62a1940.ed8e7711ddff8020.b115070b62c3a128
+ 193906a08fa7b01f.e704a4320fa0113f.7b3d00a487b866d8.b8121adcdfdea11b
+ 8ec4cfaf9c912090
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+VPALIGNR_256_1of3(reg)
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+ 0aa0cc88aabce58b
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+VPALIGNR_256_1of3(reg)
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+ c798a9ca7d199220.ebcf7e719230bee4.cb48b61ded21a917.4d8f6c611e59fbb6
+ 136c0e7bdf618c50
+VPALIGNR_256_1of3(mem)
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+ 555a05642dd2c1d3
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+VPALIGNR_256_1of3(reg)
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+ 16040f1eca6a0845
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+ 9ba036af846d8cb0
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+VPALIGNR_256_2of3(reg)
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+ 4739f58468910925
+VPALIGNR_256_2of3(mem)
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+ 5c70f42e7fc5887b
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+VPALIGNR_256_2of3(reg)
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+ b93cc92492ee1f0f
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+VPALIGNR_256_2of3(reg)
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+VPALIGNR_256_3of3(reg)
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+ 0d52b6c85c932554
+VPALIGNR_256_3of3(mem)
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+ 5b9382af10a1170d.d4b9ca25543b9c4e.cc1c33c2e8186835.8336bdd54fb5aa9d
+ 04c68b339503f95c
+
+VPALIGNR_256_3of3(reg)
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+ ad2ef2bf73fac319.1a5251773b54d490.9e4260a554edbc62.ba81101462ac7a44
+ 76a93f9713ee95cb
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+ 306b600362d16516.35444cdd39c6474f.478e2421deac5ddc.68170a575b15b78f
+ 954beab5d0f372a8
+
+VPALIGNR_256_3of3(reg)
+ before
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+ 1e904d3a3b362220.dbef76419b551e5c.1d60e532a34ce0e8.98eb9fbbed473d1e
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+ f6f9c59cb825586e.390a65b00abae18b.9d079a8ce76888ff.e448faadf9aab1f2
+ 2f54933584a61881
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+ 1e904d3a3b362220.dbef76419b551e5c.1d60e532a34ce0e8.98eb9fbbed473d1e
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+ f6f9c59cb825586e.390a65b00abae18b.9d079a8ce76888ff.e448faadf9aab1f2
+ 2f54933584a61881
+VPALIGNR_256_3of3(mem)
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+ 592304ff316bebc5.ffe6313a2723f5f2.2b1d0cb08e608f05.94994d4ae4791ef4
+ f17fd41a8b4ed0d1.fbab994e7fc54136.e2617c145f0a34ec.6399fb3c2f1c5950
+ b0e205920ceb020b.17b67375688eda0c.92874da009a8082a.e477dccc7cdf8428
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+ 592304ff316bebc5.ffe6313a2723f5f2.2b1d0cb08e608f05.94994d4ae4791ef4
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+ b0e205920ceb020b.17b67375688eda0c.92874da009a8082a.e477dccc7cdf8428
+ 7280ec656751da27
+
+VPBLENDW_256_0x00(reg)
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+ 2a438b62896bfa4d.12f0784df5833cb3.20c969ac5bc6e41d.4ca807e059f12c59
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+ aa6419f9edb49c74
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+ 2a438b62896bfa4d.12f0784df5833cb3.20c969ac5bc6e41d.4ca807e059f12c59
+ 0a95119ef82c3bcb.6d33b2689597bc7a.c4697e949d4dcfb0.0e3ce76c38b4f4a2
+ 6942b69376cb9821.60ae3c91cc95781e.f87ff43fdf2bf684.3ae119d05f9cdbf2
+ aa6419f9edb49c74
+VPBLENDW_256_0x00(mem)
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+ ca347546a8a49fc1.10db4f590cd09503.797b30bd708097ab.8039f48fd61eefa2
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+ 4e0bdab348e6dde8.ff7034132bdbd253.3fb73531c2a57abb.985649fb1efeafd6
+ 002869c987c58f06
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+ ca347546a8a49fc1.10db4f590cd09503.797b30bd708097ab.8039f48fd61eefa2
+ ca347546a8a49fc1.10db4f590cd04dfa.797b30bd708097ab.8039f48fd61e9846
+ 4e0bdab348e6dde8.ff7034132bdbd253.3fb73531c2a57abb.985649fb1efeafd6
+ 002869c987c58f06
+
+VPBLENDW_256_0x00(reg)
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+ 54ce82b4eebe7df0.154a27a1afda364a.16614622b54a2d72.91c32b4ea363ffac
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+ 3b4c1a976771f202
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+ 54ce82b4eebe7df0.154a27a1afda364a.16614622b54a2d72.91c32b4ea363ffac
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+ 3b4c1a976771f202
+VPBLENDW_256_0x00(mem)
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+ 7f425f9d7e53422e.1b75a18e22a69db6.f07dfc7e4e54b83c.3bd471bc86dac09b
+ 8d83735757f51f90.172d6e47f345f205.0f21d1eb70985743.bb00657ddb14c68d
+ 5e58241b331ec50c.4e36683eaf579052.c332442d479ca18c.091649088ebbb865
+ 816418c73b5bd1d2
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+ 7f425f9d7e53422e.1b75a18e22a69db6.f07dfc7e4e54b83c.3bd471bc86dac09b
+ 7f425f9d7e53422e.1b75a18e22a657b8.f07dfc7e4e54b83c.3bd471bc86da6ae6
+ 5e58241b331ec50c.4e36683eaf579052.c332442d479ca18c.091649088ebbb865
+ 816418c73b5bd1d2
+
+VPBLENDW_256_0x00(reg)
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+ 16dcbd26ef99c8e7
+VPBLENDW_256_0x00(mem)
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+ 1ab591a46e7ac078
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+VPBLENDW_256_0xFE(reg)
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+ cdfd4b05eced5b47
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+VPBLENDW_256_0xFE(reg)
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+ d51de64a76e91690
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+VPBLENDW_256_0xFE(reg)
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+ f2d9bfcc57d4f472
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+VPBLENDW_256_0x30(reg)
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+ 05335191def182da
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+ cb0fc95c3bba514a
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+VPBLENDW_256_0x30(reg)
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+ f4750d330725c6b1
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+ 8c82b2c657db1841
+
+VPBLENDW_256_0x30(reg)
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+ 1a89675e8542090b.73faad03ad8fae91.55f4f502099bcf7b.e641993069145607
+ c129b82782fc0831
+VPBLENDW_256_0x30(mem)
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+ 6c4654fb6d4c6c27.48fdd0475b407610.7a19a25c535df34f.acb056c888fbdb3e
+ 9af45191d8dea882
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+VPBLENDW_256_0x21(reg)
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+ c37a8a7ecd9282da.b4f91209bbc7c496.c992bb320756ff0f.65bfb898fad7388e
+ 793952bc28f90e0d.260093d170613c06.15dfec82d7d25f4d.b1765b58318fc397
+ c0c19a226bce17b8
+VPBLENDW_256_0x21(mem)
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+ caa25f1fa7f8eea4.d74ce698ff0ad032.f05876a88a3c78ce.812ebc0ffcfbc3c5
+ 37855ea1c9ce429d
+
+VPBLENDW_256_0x21(reg)
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+ e1982424132176ca.3842035231eba625.c6f3d8f9ce7f83ae.2bceb484b0642eba
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+ 240dd939be56a303
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+ e1982424132176ca.3842035231eba625.c6f3d8f9ce7f83ae.2bceb484b0642eba
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+ 43d5274b57a9d815.c381a77ed94710d9.b52d0e265e11edf0.c94dfc80bcdd1f80
+ 240dd939be56a303
+VPBLENDW_256_0x21(mem)
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+ 3d8a72ba47fd7024.3d9e467775c74ade.4abf2d027f6d0e1f.845a69809020ee58
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+ e9ffc4cbe6e52890.af5363074cdaaa85.ac5d743e04bc7e57.13dbca66450d6647
+ 88b8713c1514047f
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+ e9ffc4cbe6e52890.af5363074cdaaa85.ac5d743e04bc7e57.13dbca66450d6647
+ 88b8713c1514047f
+
+VPBLENDW_256_0x21(reg)
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+ 023f7ee156ad3c2f
+ after
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+ 9a2a9dc8b00132cb.09cbaecd7a6faba7.78535c5bbe42da6b.caba5b93469441e2
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+ 023f7ee156ad3c2f
+VPBLENDW_256_0x21(mem)
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+ de8e8a75062eab0b.f193dcd82c1726f7.e1fbc334ba95b6a8.a4d735b36d3b0153
+ 8f6e0107887aef75
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+ 8adf6bb7c780020c.6f37f236dca2e3a8.25e9ce2104e79253.93b565d1ee932572
+ 8adf6bb7c780416f.6f37f2362cc3e3a8.25e9ce2104e7e64a.93b565d152112572
+ de8e8a75062eab0b.f193dcd82c1726f7.e1fbc334ba95b6a8.a4d735b36d3b0153
+ 8f6e0107887aef75
+
+VPBLENDW_256_0xD7(reg)
+ before
+ 8dc461d906b92cf2.1a29c15938d40bc5.ba61933e05c554f1.8d0f6972b492a54d
+ f82551938286f577.ddacb97bf214188c.03531b96cf792f5d.91e5d1b8e6642428
+ 2eddcba3996d86b0.04e3edc74ffb8d8c.28b5714e24c1f5e6.ca4878f16f16ed66
+ 8938cd74e6f81a48.699ad92a6c9427f0.85d58fd1a329e039.1506d80b68b5bd33
+ 4ce96ff1ef4c50ba
+ after
+ 2eddcba3828686b0.ddacedc74ffb8d8c.28b5714ecf79f5e6.91e578f16f16ed66
+ f82551938286f577.ddacb97bf214188c.03531b96cf792f5d.91e5d1b8e6642428
+ 2eddcba3996d86b0.04e3edc74ffb8d8c.28b5714e24c1f5e6.ca4878f16f16ed66
+ 8938cd74e6f81a48.699ad92a6c9427f0.85d58fd1a329e039.1506d80b68b5bd33
+ 4ce96ff1ef4c50ba
+VPBLENDW_256_0xD7(mem)
+ before
+ 4cbeb88f20e76227.6681527205b5eeec.e99cfa8e65eca1e5.76fe738ae63c2d02
+ f1512fd11692aea8.22055609942f3e48.60b7cae1540eb996.577b18e7898617ec
+ 176e51a4ed5af166.1711d5a52cf34607.aab5c70e58062930.83997a532993dba4
+ 9ae098f2c24ae690.a2efcbb26b8c41d5.a4636c008ae0addf.58a5953b61f0b5d5
+ 31e86609ce28e12c
+ after
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+ f1512fd11692aea8.22055609942f3e48.60b7cae1540eb996.577b18e7898617ec
+ f151b88f20e7aea8.66815272942f3e48.60b7fa8e65ecb996.76fe738a898617ec
+ 9ae098f2c24ae690.a2efcbb26b8c41d5.a4636c008ae0addf.58a5953b61f0b5d5
+ 31e86609ce28e12c
+
+VPBLENDW_256_0xD7(reg)
+ before
+ 6ab1e82a0bc89a55.577582a8b16f4b50.1fec359cec876c5f.288d35a509a903ce
+ 5e4b170bb55b1dfb.28f78ab3d5d4dad2.eb530ed04c6e0351.13ff9fe8ee6de52a
+ 6b01ef16676da6cb.ea332dfd4a855044.607252b827cf4157.418525b55736101e
+ eb216db9bd8b7170.79f5e5742d8f68cf.db93fec21836641c.8eeb43f9601240d7
+ d6fc759e240c3081
+ after
+ 6b01ef16b55ba6cb.28f72dfd4a855044.607252b84c6e4157.13ff25b55736101e
+ 5e4b170bb55b1dfb.28f78ab3d5d4dad2.eb530ed04c6e0351.13ff9fe8ee6de52a
+ 6b01ef16676da6cb.ea332dfd4a855044.607252b827cf4157.418525b55736101e
+ eb216db9bd8b7170.79f5e5742d8f68cf.db93fec21836641c.8eeb43f9601240d7
+ d6fc759e240c3081
+VPBLENDW_256_0xD7(mem)
+ before
+ f5853791c0319d47.3cf58b5e543fb997.b109300399fddfa2.b8030c58bb2da64c
+ c75206bf4f8c4356.b9ca4773c818bbeb.6e3b8996abdb71e7.530f7ae8ad424395
+ 282f5d12ed29ddd9.bdec9d63b49fb319.8c566c197e36daca.080043dd890179a0
+ f3e8b878b71529fd.a6a6879ab462dccd.e62856782f19d578.332563a3ecf5821c
+ 30c9d7a671aa9ab3
+ after
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+ c75206bf4f8c4356.b9ca4773c818bbeb.6e3b8996abdb71e7.530f7ae8ad424395
+ c7523791c0314356.3cf58b5ec818bbeb.6e3b300399fd71e7.b8030c58ad424395
+ f3e8b878b71529fd.a6a6879ab462dccd.e62856782f19d578.332563a3ecf5821c
+ 30c9d7a671aa9ab3
+
+VPBLENDW_256_0xD7(reg)
+ before
+ 5b379952b5acff11.064993dbc95be1ee.ce46028465ed73b2.5a7bc19fd9901f1d
+ 10bda7135388ebe3.3c1d6a293d07c1d7.93160b8d63cab475.c31c2b7a99a874e5
+ aba5fd56e7c99bd5.7132ba4d322687e5.4f649d214987dbc2.fdd70ff68a6c90fa
+ 883c95850efc4b93.8152fe33c2c3ed43.5f7ab5adb3af2344.e477eafdc9e82e8b
+ 53ca367d71290bc2
+ after
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+ 10bda7135388ebe3.3c1d6a293d07c1d7.93160b8d63cab475.c31c2b7a99a874e5
+ aba5fd56e7c99bd5.7132ba4d322687e5.4f649d214987dbc2.fdd70ff68a6c90fa
+ 883c95850efc4b93.8152fe33c2c3ed43.5f7ab5adb3af2344.e477eafdc9e82e8b
+ 53ca367d71290bc2
+VPBLENDW_256_0xD7(mem)
+ before
+ 289a71609e3ae3cc.03ce6c0d64ab36c8.474ab2c709eab01e.20a54d9b3ecfc9a7
+ 3eb516946d2771d4.77a67f5b84659920.a1e652f524a88ba1.ec30635985720999
+ 70e5a104fafd7207.4212c9da0bb3b048.6af15baa2e083bfa.2069f25125241ec3
+ 9cf78f9c60c7a291.bf5c46f59323b7ec.7d3948d044167c52.189af6f1b97246d4
+ 31116ba4dee7ba76
+ after
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+ 3eb516946d2771d4.77a67f5b84659920.a1e652f524a88ba1.ec30635985720999
+ 3eb571609e3a71d4.03ce6c0d84659920.a1e6b2c709ea8ba1.20a54d9b85720999
+ 9cf78f9c60c7a291.bf5c46f59323b7ec.7d3948d044167c52.189af6f1b97246d4
+ 31116ba4dee7ba76
+
+VPBLENDW_256_0xB5(reg)
+ before
+ c5184ed62f10b956.9cb75a48bb91bd9d.4ad1f31abb40e9b7.b888955581df0ad8
+ 31fc99f348777d1f.4ef080f428687e57.3ebdcbb41d978356.f5abbe23026ea1b5
+ d1094a67c6aa437e.8c707c8cc257a2ed.f96cc92f55b3c075.126e3f28e2d0fc18
+ 018a5d9e4535471e.3401cafca66ae589.d52aecf70020debf.e99d954f3d0fd82b
+ 58043b83303af01b
+ after
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+ 31fc99f348777d1f.4ef080f428687e57.3ebdcbb41d978356.f5abbe23026ea1b5
+ d1094a67c6aa437e.8c707c8cc257a2ed.f96cc92f55b3c075.126e3f28e2d0fc18
+ 018a5d9e4535471e.3401cafca66ae589.d52aecf70020debf.e99d954f3d0fd82b
+ 58043b83303af01b
+VPBLENDW_256_0xB5(mem)
+ before
+ 396fadb2d75a0113.1dcdcc0560a2c5ac.2070e731efae0257.30432d79b96a17e1
+ 6aa967c74d7dc740.811c9506b480f8d4.2e894e15ba2eb684.6502891f1d1ea886
+ c57fe6afaeaefecd.89c4b20edc581d41.38187a9622f7bd3c.cfb4fd57c7c8cc5b
+ 27bea55417f962e7.9111228a74b870a0.1ce9ea9f4414d3aa.cca5848b54f2c10b
+ b6211a295f2ac143
+ after
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+ 6aa967c74d7dc740.811c9506b480f8d4.2e894e15ba2eb684.6502891f1d1ea886
+ 6aa9adb24d7dc740.1dcd950660a2f8d4.2e89e731ba2eb684.3043891fb96aa886
+ 27bea55417f962e7.9111228a74b870a0.1ce9ea9f4414d3aa.cca5848b54f2c10b
+ b6211a295f2ac143
+
+VPBLENDW_256_0xB5(reg)
+ before
+ ea74bc9b85fb08af.6d2f20a3a46baeba.f54fdee5192b2c9c.b4c7171b3b91b3fb
+ c5ea644f61f2d4fa.71a1d3886f0f9f71.11cae38a663d8ee2.dd807ff8247a1a5a
+ a1ce10b08f9a5fd1.10df3af097f2f039.41ce2ee7f87bd21d.73de9c211adcc4f4
+ db6ebb2aac7fe6e0.26b4d2c6361f5f3e.e1a6ba676a7033fb.53aeec8239c26cf5
+ 57bceb079f39cf88
+ after
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+ c5ea644f61f2d4fa.71a1d3886f0f9f71.11cae38a663d8ee2.dd807ff8247a1a5a
+ a1ce10b08f9a5fd1.10df3af097f2f039.41ce2ee7f87bd21d.73de9c211adcc4f4
+ db6ebb2aac7fe6e0.26b4d2c6361f5f3e.e1a6ba676a7033fb.53aeec8239c26cf5
+ 57bceb079f39cf88
+VPBLENDW_256_0xB5(mem)
+ before
+ 5cd4139d654ca9da.d0146229542ea5d2.8fee16f568a2a6ab.4d9f837659a9ef25
+ 3ec1e22ea907b616.da0dff192232d753.2857826b4a8881ac.e005868060b1404a
+ d951d3a78677b169.56a59067b217b910.cbbc9213f7dcae6e.f824bdf21c146214
+ 094e62f519a757ff.a027107da16a87b5.55e9c3d98baae71d.f0482636285e932f
+ 24bdbcb9211c0d48
+ after
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+ 3ec1e22ea907b616.da0dff192232d753.2857826b4a8881ac.e005868060b1404a
+ 3ec1139da907b616.d014ff19542ed753.285716f54a8881ac.4d9f868059a9404a
+ 094e62f519a757ff.a027107da16a87b5.55e9c3d98baae71d.f0482636285e932f
+ 24bdbcb9211c0d48
+
+VPBLENDW_256_0xB5(reg)
+ before
+ efce7be8a2d90d0b.aa850b037ea36403.15e17bc88bb67cee.a2aa8fa924fee9e5
+ afc8602d4822ce23.98c24bbcd07794a2.0f1dcdb50b88d566.8eca746fdbe570f1
+ bef866f6ae828d3d.afd19d0e2b30a207.eb2903afbd6acec9.f517ee17ce6b376d
+ 7aa888ae70858605.cb7e7ce4acda4b5f.054f18213eeaa3c5.b35b778e199afb86
+ a4638dbed7807868
+ after
+ bef8602dae828d3d.98c29d0ed077a207.eb29cdb5bd6acec9.8ecaee17dbe5376d
+ afc8602d4822ce23.98c24bbcd07794a2.0f1dcdb50b88d566.8eca746fdbe570f1
+ bef866f6ae828d3d.afd19d0e2b30a207.eb2903afbd6acec9.f517ee17ce6b376d
+ 7aa888ae70858605.cb7e7ce4acda4b5f.054f18213eeaa3c5.b35b778e199afb86
+ a4638dbed7807868
+VPBLENDW_256_0xB5(mem)
+ before
+ a4fbaa952428693e.3d24c5c12bb8f526.c894672a6e7f4ad6.b9dc087929948f03
+ 8eef4cfd1d9f8c35.65ba169b7ba6164c.82e1d7cc8e2d5d97.631bcf221bf3cf32
+ 400aefe4def09b79.4cb579a8fbdb2425.d52f4ab627f03ecf.5f5a6988af939ffc
+ 951a0d3582275235.5060e85447e45c5b.9d4b3bd456d2aaa9.09e4d31782003b0d
+ bd04083c2fc7de12
+ after
+ a4fbaa952428693e.3d24c5c12bb8f526.c894672a6e7f4ad6.b9dc087929948f03
+ 8eef4cfd1d9f8c35.65ba169b7ba6164c.82e1d7cc8e2d5d97.631bcf221bf3cf32
+ 8eefaa951d9f8c35.3d24169b2bb8164c.82e1672a8e2d5d97.b9dccf222994cf32
+ 951a0d3582275235.5060e85447e45c5b.9d4b3bd456d2aaa9.09e4d31782003b0d
+ bd04083c2fc7de12
+
+VPBLENDW_256_0x85(reg)
+ before
+ d70704615273c5b7.69e924dc25516f96.cb08610bfc4cf99a.b501261336e15c52
+ b339c3f388902ba8.9844afc5e479acc7.1bf9e03ab59f388f.fb1c875de32911f6
+ ace6425f6dab4e90.fdf72adcdaabc6f5.9a7f5f4b0f6955e6.4a6adba07ab485c0
+ 205a7c0f9c4f681b.76ce110d24f4784c.a5e6dcaca5378c4a.7eb59cc6179074dd
+ 72cb48bdd5c99978
+ after
+ ace6c3f388902ba8.98442adce479c6f5.9a7fe03ab59f388f.fb1cdba0e32985c0
+ b339c3f388902ba8.9844afc5e479acc7.1bf9e03ab59f388f.fb1c875de32911f6
+ ace6425f6dab4e90.fdf72adcdaabc6f5.9a7f5f4b0f6955e6.4a6adba07ab485c0
+ 205a7c0f9c4f681b.76ce110d24f4784c.a5e6dcaca5378c4a.7eb59cc6179074dd
+ 72cb48bdd5c99978
+VPBLENDW_256_0x85(mem)
+ before
+ 04765a70d069b2be.6ae06d71b109b6f6.de95e144dd5f7ff7.997a52c714951968
+ 0e834fcb257e78da.e6c511f0496473cd.1017156e22f99722.d086bd0af70e37eb
+ 6ebea2baf014aaf9.ef5664f800ecdd4b.ea2229750ecc7cfb.a75719e0eb2e2380
+ fff2ce294c360247.e3dd63f5712e2e1d.46809947bee6eaac.7a3a63b58b8118d3
+ a57995f57494548f
+ after
+ 04765a70d069b2be.6ae06d71b109b6f6.de95e144dd5f7ff7.997a52c714951968
+ 0e834fcb257e78da.e6c511f0496473cd.1017156e22f99722.d086bd0af70e37eb
+ 04765a70257eb2be.6ae06d71496473cd.de95e14422f97ff7.997a52c7f70e37eb
+ fff2ce294c360247.e3dd63f5712e2e1d.46809947bee6eaac.7a3a63b58b8118d3
+ a57995f57494548f
+
+VPBLENDW_256_0x85(reg)
+ before
+ 8460ad0c41f21161.9ced510455f03def.1da7095338b4a2ef.02fee1ce4d539c61
+ 743da7668e278cf4.2279a738284e171e.f8ff527ef20d776c.f8687ef8d71e4f47
+ cf5b7d6ff8c000f5.6e634aafe05d4b00.d2333ae23ac2e740.068aebb07953be8a
+ f2052d941b48aa10.5a77b8569a2897c0.058dbeebad612f19.062fa4e24ffea655
+ d625257a742cc3d5
+ after
+ cf5ba7668e278cf4.22794aaf284e4b00.d233527ef20d776c.f868ebb0d71ebe8a
+ 743da7668e278cf4.2279a738284e171e.f8ff527ef20d776c.f8687ef8d71e4f47
+ cf5b7d6ff8c000f5.6e634aafe05d4b00.d2333ae23ac2e740.068aebb07953be8a
+ f2052d941b48aa10.5a77b8569a2897c0.058dbeebad612f19.062fa4e24ffea655
+ d625257a742cc3d5
+VPBLENDW_256_0x85(mem)
+ before
+ 5036eb6404e8d136.3988b23f924bc6f0.c4816c1a71bcb48a.ef5bd906e6758aa1
+ 512f718c1c3f8ca3.003008def9569042.864de2e68223618c.eae7879d828b3584
+ b6dc33dfd83baf48.a3492bdbedf443b1.7da696a5e86c58f0.547ec41e1c2e6d6f
+ 5909ad4753ebf752.7d1f17a40ab21cea.865a0545bfa056e2.876c8cf451ea6b0e
+ e1fcdc8bbc4c6e0c
+ after
+ 5036eb6404e8d136.3988b23f924bc6f0.c4816c1a71bcb48a.ef5bd906e6758aa1
+ 512f718c1c3f8ca3.003008def9569042.864de2e68223618c.eae7879d828b3584
+ 5036eb641c3fd136.3988b23ff9569042.c4816c1a8223b48a.ef5bd906828b3584
+ 5909ad4753ebf752.7d1f17a40ab21cea.865a0545bfa056e2.876c8cf451ea6b0e
+ e1fcdc8bbc4c6e0c
+
+VPBLENDW_256_0x85(reg)
+ before
+ bc7caf4ef9dfb016.17815bb2a9581fed.ecfdc9a4eb1b5799.7b33aab125cd178f
+ 753601aba52f6ed7.cc12ba0af790e545.4b313c472cbb3069.39fe01d533fe5723
+ 6977ce0d5cc9e3fd.5586453d589e0385.f6056cf96a1ee207.9c87869d0740d1c9
+ f28b13e1b9384d31.8cab7836e98f35d9.49c6562640d1aa1e.809ab5f6bd9d42ae
+ c2020bca702465fd
+ after
+ 697701aba52f6ed7.cc12453df7900385.f6053c472cbb3069.39fe869d33fed1c9
+ 753601aba52f6ed7.cc12ba0af790e545.4b313c472cbb3069.39fe01d533fe5723
+ 6977ce0d5cc9e3fd.5586453d589e0385.f6056cf96a1ee207.9c87869d0740d1c9
+ f28b13e1b9384d31.8cab7836e98f35d9.49c6562640d1aa1e.809ab5f6bd9d42ae
+ c2020bca702465fd
+VPBLENDW_256_0x85(mem)
+ before
+ 3c8d03063cdef8e3.6dbeca915808e621.4e4bcfe1c56e396f.9fc0f43a4b5fc35b
+ cb0519973ed9b58c.365cf18ad6c6ea79.7732c7290947c970.563f44a226556b6a
+ 4b37ca6891205923.a9b08339cffd97e5.e32edafdd027a20b.c98e41c86d3edcf6
+ 98ef906452c09fd5.23087d08de392710.6e0a86463618806a.53fbe71abea653ab
+ 52d03302b2190b37
+ after
+ 3c8d03063cdef8e3.6dbeca915808e621.4e4bcfe1c56e396f.9fc0f43a4b5fc35b
+ cb0519973ed9b58c.365cf18ad6c6ea79.7732c7290947c970.563f44a226556b6a
+ 3c8d03063ed9f8e3.6dbeca91d6c6ea79.4e4bcfe10947396f.9fc0f43a26556b6a
+ 98ef906452c09fd5.23087d08de392710.6e0a86463618806a.53fbe71abea653ab
+ 52d03302b2190b37
+
+VPBLENDW_256_0x29(reg)
+ before
+ 215a20eee7244244.8ef9e9799dc444cd.feaed9659f07d7a6.f49146f158291eb9
+ 1be5aa49f953327e.092150928c380438.97ef95bbaff2e354.519097ea52633926
+ 9ebdcd7f83301792.e532419b3e299b42.4a17ac76a98786c6.61d3f31e3fd48dda
+ 042e85fc21492f2c.fdfa3980cca2c416.73721b022a50fda8.0026d8773c88d504
+ 0a55c1e36489cfce
+ after
+ 1be5aa498330327e.e53250928c389b42.97ef95bba987e354.61d397ea52638dda
+ 1be5aa49f953327e.092150928c380438.97ef95bbaff2e354.519097ea52633926
+ 9ebdcd7f83301792.e532419b3e299b42.4a17ac76a98786c6.61d3f31e3fd48dda
+ 042e85fc21492f2c.fdfa3980cca2c416.73721b022a50fda8.0026d8773c88d504
+ 0a55c1e36489cfce
+VPBLENDW_256_0x29(mem)
+ before
+ 5a2c2b4dd3e53564.ab83cf2c7029b4f7.2f43b22d55af3ce1.6e4bdccbcddc84a5
+ ce7690a0a6a8c3f3.ed0aa67b0c5de3a0.56da2a8ff25dbfce.97f0ed3d2eb45669
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+VPHADDW_256(reg)
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+VPHADDW_256(reg)
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+VPHADDD_256(reg)
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+VPHADDSW_256(reg)
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+VPHSUBW_256(reg)
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+VPHSUBD_256(reg)
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+VPHSUBD_256(reg)
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+VPHSUBD_256(reg)
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+VPHSUBSW_256(reg)
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+VPHSUBSW_256(reg)
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+VPHSUBSW_256(reg)
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+ e7e87cb2a3ff00fb
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+VPABSB_256(reg)
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+ 5959df5a31b91852
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+VPABSB_256(reg)
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+ d2f818ac6f6ebf4a
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+ f62ac7ec2de84aea
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+VPABSB_256(reg)
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+ cf87f61e4564b9d8
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+ 1706046cbbaa4e02
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+VPABSW_256(reg)
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+ aebfa53f4036f220
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+VPABSW_256(reg)
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+VPABSW_256(reg)
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+VPMOVSXBQ_256(reg)
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+ 0000000000000048.000000000000002d.0000000000000045.ffffffffffffff8b
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+ 0000000000000061.000000000000001f.0000000000000052.ffffffffffffffbb
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+VPMOVSXBQ_256(reg)
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+VPMOVSXBQ_256(reg)
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+VPMOVSXWQ_256(reg)
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+ 0000000000000687.ffffffffffffcfdb.0000000000003a54.0000000000001506
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+VPMOVSXWQ_256(reg)
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+ 0000000000003520.ffffffffffffc77a.0000000000001b9c.0000000000005c9f
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+ 40a755e611d3621b
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+ 000000000000364d.ffffffffffffc38d.ffffffffffffe850.0000000000006121
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+ 612b6d7f8e97fe01.fa590c3ae3edbb02.1a8f9dfd6be6bfb1.da119c04c70cf214
+ 93d4f4344b126ceb
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+VPMOVSXWQ_256(reg)
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+ 00000000000025aa.ffffffffffffd8f4.ffffffffffff885f.00000000000036cc
+ 4fcbf4c8081efa6a.568ffc251e8d746a.02a2916f0a5f8c8c.25aad8f4885f36cc
+ f0a9390cb54852d0.12cca99aa3a08651.367adc526a4b94c9.3782c26d4bbcb799
+ 131710d99a4849e7
+VPMOVSXWQ_256(mem)
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+ 9ea3c8364a1a8fb4.6f0193bbdd20a87b.d0382468d72e73d1.8f9488dd4c922fe2
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+ a4afe16b7735e894.4dcb921626f414cd.528b073650eefa0b.9089e13c18be694a
+ 563384e91c48f729
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+ 97333e22900ea8e1.324c70e4721a7847.476b37b782274710.9bb1db534cd80c02
+ ffffffffffff9bb1.ffffffffffffdb53.0000000000004cd8.0000000000000c02
+ 03332affe378bc8c.0412a0fd8fe41d19.8bffea99bdc2c5c1.6d6de15c07053a16
+ a4afe16b7735e894.4dcb921626f414cd.528b073650eefa0b.9089e13c18be694a
+ 563384e91c48f729
+
+VPACKUSDW_256(reg)
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+ 1ab9c6cfaf302160.5be36865235cd2f9.a67a65723edcc943.03aaf72badbecedc
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+ f0632011d48f9ec9.a3c5b6dfccc7530a.a93bfe529f16b1e4.22688a549482592e
+ 0ec59ae22f5c00d1
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+ 3765a45b6b01239a.059b3bd903f934e6.6b6a167e72277726.78263465ef3ffc5f
+ 0b8518f7ef473984.7fa2d6b33219cb88.f8e69fa45e615c22.8fcc3cce337c41c1
+ f0632011d48f9ec9.a3c5b6dfccc7530a.a93bfe529f16b1e4.22688a549482592e
+ 0ec59ae22f5c00d1
+VPACKUSDW_256(mem)
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+ cefecb632bff3dc7
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+ 62f6f1c580bce96c.618cda6b37524817.5d9032deb4ff2561.e7a02cf28f23a26a
+ ffffffffffff0000.ffff0000ffffffff.ffff000000000000.ffff000000000000
+ 69bf21d908feddf0.6a40b0ca74ab00e3.12598e3499ff894a.05f87ebe20ad2a15
+ cefecb632bff3dc7
+
+VPACKUSDW_256(reg)
+ before
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+ 9f379847d37a2b40.057e0a7ea682bdbf.eadf848d6af9a88e.a482ac445c2a6025
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+ 81543bc64d626050.14958b1239a76739.c3ca3414fb9c1e77.f16a6a6bdddd8b53
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+ 6003115da8ba7f5f.7079f914e37adab1.5e4522e2119acb24.85b8f97ff70c0d9c
+ 81543bc64d626050.14958b1239a76739.c3ca3414fb9c1e77.f16a6a6bdddd8b53
+ c4647cf62ba89577
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+VMPSADBW_256_0x0(reg)
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+ f8a5ea36fdf3d1ad.620553c4e231ee31.71468e0a5ff0609e.5c8484ac532d9f03
+ ba478ca5b279f2b2.2841f179cf321667.07884ff5f78bba87.986158a3902d9e8b
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+ b509ca3a82c9640f.f34b381a2d1e77b4.dfd590a0647503eb.c73b1226a0c656fb
+ 72d0f189ad77863b
+ after
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+ ba478ca5b279f2b2.2841f179cf321667.07884ff5f78bba87.986158a3902d9e8b
+ daa52d2d553d0fef.6414bf9d347d5ad9.0d9e510370df3213.1daf5ed2f5b19d79
+ b509ca3a82c9640f.f34b381a2d1e77b4.dfd590a0647503eb.c73b1226a0c656fb
+ 72d0f189ad77863b
+VMPSADBW_256_0x0(mem)
+ before
+ fa3c75e837d0e965.a5c05d38d6ab2cbe.b1b3daded4212924.d879093872db6abe
+ 3c491c305add3aa6.0716e493ed6fa4a9.7a1621d447932c54.56d6b637339ca336
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+ 597ac127dd46991c.92cebb11d1ca93e3.9dff8a0600f213a6.4deba11b446179c6
+ 7f3ad6d8cb7c8f37
+ after
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+ 597ac127dd46991c.92cebb11d1ca93e3.9dff8a0600f213a6.4deba11b446179c6
+ 7f3ad6d8cb7c8f37
+
+VMPSADBW_256_0x0(reg)
+ before
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+ 5d46b378dfb2c126
+ after
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+ 6589f8e96cd2cf0a.0e81f486e69ad7a6.cec120fa871fffb0.37b15f53ccecfae2
+ 5d46b378dfb2c126
+VMPSADBW_256_0x0(mem)
+ before
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+ 4652636324b69e3c.409598ec48b12a65.671743ae2b46777b.40bb6d2519da3a05
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+ ba2d04f7f8531e35.8b646c6b55de2b36.94e58ba7c57441db.6ae1f8f4a5caa577
+ 6aa2ea284e54224a
+ after
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+ 4652636324b69e3c.409598ec48b12a65.671743ae2b46777b.40bb6d2519da3a05
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+ ba2d04f7f8531e35.8b646c6b55de2b36.94e58ba7c57441db.6ae1f8f4a5caa577
+ 6aa2ea284e54224a
+
+VMPSADBW_256_0x0(reg)
+ before
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+ 0bfd14417549d77e.9b37769339e92171.265756c774b8b4de.744bacd096831624
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+ 95732b70c6626b41.c7d09998c8d9874e.f0ce355f859fa3bc.e9a786897dd4d6b8
+ 20d04e0abe1244ec
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+ 95732b70c6626b41.c7d09998c8d9874e.f0ce355f859fa3bc.e9a786897dd4d6b8
+ 20d04e0abe1244ec
+VMPSADBW_256_0x0(mem)
+ before
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+ d61401f069f9e904.e6650f122001bef2.1f594d648582302e.cb28e89468f4d930
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+ 503f1dd75b1128d6.e0329f896486b0f2.8332725a4f45fb71.95c550c4fd16369b
+ daeade6ad0d2091b
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+ d61401f069f9e904.e6650f122001bef2.1f594d648582302e.cb28e89468f4d930
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+ 503f1dd75b1128d6.e0329f896486b0f2.8332725a4f45fb71.95c550c4fd16369b
+ daeade6ad0d2091b
+
+VMPSADBW_256_0x39(reg)
+ before
+ 2f054e5224659a5c.7d4a28d8730d58f3.a148dec3a4bc1a9d.a09945d1a02d84c5
+ f1619ae9945c240b.6eb2821d72bae2c2.613abc357250209f.d3b9e7d70881ca75
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+ 8f608975e5705f6b
+ after
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+ f1619ae9945c240b.6eb2821d72bae2c2.613abc357250209f.d3b9e7d70881ca75
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+ 270abbd539a41662.10cc0f248f54f729.4ade47752abff05c.ef508e3d8f967b9d
+ 8f608975e5705f6b
+VMPSADBW_256_0x39(mem)
+ before
+ b75745ecc3e4ef46.53f08702a70cf662.78153cbee55afa18.2b28eb1a4cb2316d
+ 41023d8c44ffe95a.5c47208da009bf7f.16eda64c9240476a.7b7d1ea96c33fe86
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+ efa3d2fba25805db.7277aa72aaebffc3.5f7625f45adeb2e6.d4772231180d2b7f
+ 95b5eb03dc7e03b7
+ after
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+ 41023d8c44ffe95a.5c47208da009bf7f.16eda64c9240476a.7b7d1ea96c33fe86
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+ efa3d2fba25805db.7277aa72aaebffc3.5f7625f45adeb2e6.d4772231180d2b7f
+ 95b5eb03dc7e03b7
+
+VMPSADBW_256_0x39(reg)
+ before
+ 342d336e0ead57a6.ca3266a1b5aea0a0.37e993a3f1e9ee41.c4bf32e6afad4767
+ 0d2cf6de4a2463fa.78a42722ddda944e.48fb39e335abb68d.cdc66e7cc98c18fb
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+ after
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+ deefde7e5320917a.bd641e62d6e67714.bd32ad4022a8c43d.3e3d5f44bdad580c
+ 5e450d4fd00540e0
+VMPSADBW_256_0x39(mem)
+ before
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+ b9ec3f4cb1834dfb.e65d8442d5d06e9a.9e44951a6cda8c8c.b37de6ea51420834
+ ac22bc17b8c1ea9b.4573731f6aeb94f3.4f1d77b199ea3f59.a32703c9a7089597
+ 48aacaf94863e582.07d7c58ab197dab7.fba36daa8119b417.083ac440a1da64d1
+ 3d0327badc43b08c
+ after
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+ b9ec3f4cb1834dfb.e65d8442d5d06e9a.9e44951a6cda8c8c.b37de6ea51420834
+ 00ed00b60172013f.007c016201b70134.00fa0139014501c1.00f90040010c01a2
+ 48aacaf94863e582.07d7c58ab197dab7.fba36daa8119b417.083ac440a1da64d1
+ 3d0327badc43b08c
+
+VMPSADBW_256_0x39(reg)
+ before
+ 9dcc27a3f4cfb674.694fe7e07e75fbdb.86d677ed47607c93.7ea0f3f24171a5f1
+ 86e1c066840ab236.ebdf8fb77504e8d2.1fbc84b6c7d2b533.b4e18673f400cf14
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+ 20335f8cda6bf8e8
+ after
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+ 5f24ae2f7dc07af7.82eb6ce518c6354d.0f6ca027f7e3df6e.a95fc0d4a4f1bce3
+ 20335f8cda6bf8e8
+VMPSADBW_256_0x39(mem)
+ before
+ ba7cfb2e734b5de5.07e8fb0d1f51bf4e.4f009a15fc120e28.1ecfa7a7df994860
+ 52040ea68b9ea607.a729d175a9c2ea2f.ec2f42e4110aad52.b748f93d212938c6
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+ f1048ec8aacad768.40520897e672e03c.0b0bf113402f3142.f6af6e562405a09e
+ 55358ab31e698f66
+ after
+ ba7cfb2e734b5de5.07e8fb0d1f51bf4e.4f009a15fc120e28.1ecfa7a7df994860
+ 52040ea68b9ea607.a729d175a9c2ea2f.ec2f42e4110aad52.b748f93d212938c6
+ 01d601b600f800cd.01b300e2025300d7.009b017b00fd01dc.0144027101ba0137
+ f1048ec8aacad768.40520897e672e03c.0b0bf113402f3142.f6af6e562405a09e
+ 55358ab31e698f66
+
+VMPSADBW_256_0x32(reg)
+ before
+ ae02e0d4e2d6f653.ae14f34ae9bc37ff.f0d26228d1c924c2.444fef4b91748c60
+ 5d616e270dd8110f.db94bf5217506b6b.09ff35f515303d80.bddd58d384959f7c
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+ 5d616e270dd8110f.db94bf5217506b6b.09ff35f515303d80.bddd58d384959f7c
+ bda0301739fc1b47.534f70cd519330d8.e5247d694d316825.5481a796359f24c3
+ 2c09201005cd52a6.f11381a5b28f4271.e18e36ef165ae15b.e3075982bf9dd861
+ 483be8823e9b7681
+VMPSADBW_256_0x32(mem)
+ before
+ 5de9d282cfa6bc4f.05e93c7e0bd8f0d9.93aa6ec857525c63.59895df50b37e4ce
+ 00dc926f8dc964f9.a38c7fcde7a8318c.13e1b4205be83bda.aa61ede6c852ac2c
+ 0be2a53395112aa8.643ee56936c9536a.4f84cd9bda5c9b01.2e62e22eeb39761e
+ 5cc585bb0288cc8b.a34a6abe93c8901f.215f3724f1ba3805.42d8383a0d787e53
+ 420eeb74cc9a0075
+ after
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+ 00dc926f8dc964f9.a38c7fcde7a8318c.13e1b4205be83bda.aa61ede6c852ac2c
+ 00ac011d009b0167.00d90114008d0101.016d00f4016a0176.019401a7015800f8
+ 5cc585bb0288cc8b.a34a6abe93c8901f.215f3724f1ba3805.42d8383a0d787e53
+ 420eeb74cc9a0075
+
+VMPSADBW_256_0x32(reg)
+ before
+ 8a52f849c42b3730.cd52b0f4f13d04cc.bbfe0b389b2f2559.673d6da7bc0ecd11
+ 76ee5a2690b76032.3c55a1c87d398f98.0aa4c244e98d4dc2.fbecec1056651752
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+ aa610da415f277b5.7fecc5f6de3b8d7f.b9f968bec9574ad2.81e8b144684ab921
+ 2acef0e719ef8a08
+ after
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+ aa610da415f277b5.7fecc5f6de3b8d7f.b9f968bec9574ad2.81e8b144684ab921
+ 2acef0e719ef8a08
+VMPSADBW_256_0x32(mem)
+ before
+ 92b4672108c8fed3.aad0571e06b8dd8f.0d18f127eb5978f2.d1404d0593dd95d2
+ 966693dc54ded4af.bec7e54f3caa255e.07ebd3a405eea5a0.8faa3a8d138765b1
+ 10afee06173fc6c7.4194b5a352538ad0.4a2fe7594909d2b5.508229c1e5e3f41c
+ dd5cf68a6df69148.9181c386e540498e.b2b1a932d2b3b95c.6e15190fa77d7fbe
+ 46b003e3f2df4144
+ after
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+ 966693dc54ded4af.bec7e54f3caa255e.07ebd3a405eea5a0.8faa3a8d138765b1
+ 01340154016900b0.0146013100fa0154.00da00ec016b0150.015401b50140015a
+ dd5cf68a6df69148.9181c386e540498e.b2b1a932d2b3b95c.6e15190fa77d7fbe
+ 46b003e3f2df4144
+
+VMPSADBW_256_0x32(reg)
+ before
+ 359de4a76497785a.d93a26537310f15e.09db096490fc9e47.1b3c951bbcfa17c2
+ 9528b9c898315eab.e013fb4f4498a234.05ee85a9f013c5a5.629e280024e9a812
+ c39f7db22b372fe4.ceb4ef69fc9a5ff7.e00631c1a011f954.61a1ddce258d2779
+ 1b4d2cd2b93729b1.7fe8808db923e5d3.f86e0b193d837801.f513306fdcf15123
+ fabe9dd16521e23b
+ after
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+ 9528b9c898315eab.e013fb4f4498a234.05ee85a9f013c5a5.629e280024e9a812
+ c39f7db22b372fe4.ceb4ef69fc9a5ff7.e00631c1a011f954.61a1ddce258d2779
+ 1b4d2cd2b93729b1.7fe8808db923e5d3.f86e0b193d837801.f513306fdcf15123
+ fabe9dd16521e23b
+VMPSADBW_256_0x32(mem)
+ before
+ 4c6fa1dfdb2a95ee.f97dc392ddbd86bd.cf7d29a8943deff2.a8740f1b62f57b58
+ c7f2b7845a162867.b97c3c60335383b4.9a3d66a4abf73b83.4b623735acf14104
+ 47125baefff454d3.b79695a758875c43.bcf5b36e1a5a83b0.3f8581d2b60504b2
+ a89d0948e5cdd85e.4f17c9d3e7e54c16.11728df3fc7484a6.de29e85d1cbc010e
+ 869a68447ba374c3
+ after
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+ c7f2b7845a162867.b97c3c60335383b4.9a3d66a4abf73b83.4b623735acf14104
+ 0149019101cc0189.012a018601ce015b.017801d3016701e3.013800a901810268
+ a89d0948e5cdd85e.4f17c9d3e7e54c16.11728df3fc7484a6.de29e85d1cbc010e
+ 869a68447ba374c3
+
+VMPSADBW_256_0x2b(reg)
+ before
+ 9124fdf26f45987d.c55d3d3e29af6e33.dd4bd4507df890d9.757e6f1d6d51f990
+ 5d12a4d3932eaaea.7c1f747de6a6d47f.bd7eb38ab54c6437.c4e5d5da8afb9f9b
+ 44b2585383ebe6b4.a8af29ef39bcc36d.4bfb60ed2c6d03dc.da753b146f8032f3
+ a44e15dfdc078887.25d9d8813dfffa2a.e310d9e57de8ab75.93f81db937ec6ec3
+ ca3cf8b4fe490e38
+ after
+ 01a701530091011c.01b3016000fa0179.00ea014900e80117.019d00e301e900d0
+ 5d12a4d3932eaaea.7c1f747de6a6d47f.bd7eb38ab54c6437.c4e5d5da8afb9f9b
+ 44b2585383ebe6b4.a8af29ef39bcc36d.4bfb60ed2c6d03dc.da753b146f8032f3
+ a44e15dfdc078887.25d9d8813dfffa2a.e310d9e57de8ab75.93f81db937ec6ec3
+ ca3cf8b4fe490e38
+VMPSADBW_256_0x2b(mem)
+ before
+ 5d0b47f1e1a5d07d.d733d7e1390ecb10.cf69fd200e7b33e2.e10719de444896ae
+ 2732865cfb0c6dbf.3aad9ac7378decfb.812b15b6c93a2bc0.a12d1d451e1a0032
+ 047d32e16988a42a.2a085bfb710f27f3.19ea9b318a4a9ef0.7fcedf84a7e827ae
+ cfb7c56d46272fe9.018f15eb8420b7a5.72730b7c6cb747a0.d7355d097a4145ce
+ 04b0923e33ae973d
+ after
+ 5d0b47f1e1a5d07d.d733d7e1390ecb10.cf69fd200e7b33e2.e10719de444896ae
+ 2732865cfb0c6dbf.3aad9ac7378decfb.812b15b6c93a2bc0.a12d1d451e1a0032
+ 018d0173028200d7.01c401c70090016e.01910164011a016f.01a801bb01d8020f
+ cfb7c56d46272fe9.018f15eb8420b7a5.72730b7c6cb747a0.d7355d097a4145ce
+ 04b0923e33ae973d
+
+VMPSADBW_256_0x2b(reg)
+ before
+ 64897a916fbd58a8.66aebdeaaff5cb28.1c90c4010b4ddabc.6792e1828b8ce3fa
+ 520d126dcaf9c5ba.a32c9546bffd3415.d85564aba321cae5.d613993104d52e2a
+ 2a88543edfef1a20.64ffc96b934b25da.8f2bf254e728c3cc.9ac2b074f39ee45d
+ 47463e704a2a9386.83f1d64746eb5ba3.9e5e696874ef021c.8e6ba13773f4c0bf
+ 90d9e867a0e27f7b
+ after
+ 01ff017300c800bf.0116010b0179016b.019c0152022500db.01fb017f00c80223
+ 520d126dcaf9c5ba.a32c9546bffd3415.d85564aba321cae5.d613993104d52e2a
+ 2a88543edfef1a20.64ffc96b934b25da.8f2bf254e728c3cc.9ac2b074f39ee45d
+ 47463e704a2a9386.83f1d64746eb5ba3.9e5e696874ef021c.8e6ba13773f4c0bf
+ 90d9e867a0e27f7b
+VMPSADBW_256_0x2b(mem)
+ before
+ 7ada01ee9774ddbe.0793cb6fa8366b97.decf36c5f4ea929d.613ac553e501c482
+ 293868b973b795b4.c4bbf8a7949fe0ff.4f6467d0ba5386f4.340b0281d6ea42a9
+ 7ac09ab551b66488.dc09bf85abf22b6c.b47ee456b432f2d3.731c1c5fe537bb3e
+ 473e12cc4c7e0666.a9ca1e7388bb8b88.e7e72a42fd949367.7abb1057ab7369ed
+ a532d9d7c62b8961
+ after
+ 7ada01ee9774ddbe.0793cb6fa8366b97.decf36c5f4ea929d.613ac553e501c482
+ 293868b973b795b4.c4bbf8a7949fe0ff.4f6467d0ba5386f4.340b0281d6ea42a9
+ 00720127010c010b.011e01020177014a.02230139019f01e6.01fc01ef019b004b
+ 473e12cc4c7e0666.a9ca1e7388bb8b88.e7e72a42fd949367.7abb1057ab7369ed
+ a532d9d7c62b8961
+
+VMPSADBW_256_0x2b(reg)
+ before
+ 50ce7349d1e95747.6e7d4cec811a377c.894a10dfc8843aff.c66db381b18425db
+ d7dbda1b693b0e4a.c94bc5000b96b2f4.d6d5913306db757e.2bdafdfded0f635d
+ 96a40bb82aadeb17.3572f7f407fe34fa.eeb79edddf4b78b1.f3fb83a3cd400b16
+ e977008bafca2a5a.8ec060b4905f79bb.2b3c3148ee617e43.fa9bc15f6c23d634
+ 1d88341ee6c483e3
+ after
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+ d7dbda1b693b0e4a.c94bc5000b96b2f4.d6d5913306db757e.2bdafdfded0f635d
+ 96a40bb82aadeb17.3572f7f407fe34fa.eeb79edddf4b78b1.f3fb83a3cd400b16
+ e977008bafca2a5a.8ec060b4905f79bb.2b3c3148ee617e43.fa9bc15f6c23d634
+ 1d88341ee6c483e3
+VMPSADBW_256_0x2b(mem)
+ before
+ 368d56cb5830cc4f.2c9eb702941e06be.b1ff7b2cc2c43c63.eaaf48e0cfa8c5e1
+ 2275a551dd726ea3.ba672c887635bdf0.78fcc448ba3a3b1d.885ede111fac8736
+ bd0d9c9e9297250b.f11c598af09c899b.c082b8f494cc2f16.5f93ef477afa00ef
+ e321b79d92aaadb5.2c0a3c729fdea66c.655fd11c6b86d779.cc9b78ee7b1d6db8
+ 2cc27472bea10a3c
+ after
+ 368d56cb5830cc4f.2c9eb702941e06be.b1ff7b2cc2c43c63.eaaf48e0cfa8c5e1
+ 2275a551dd726ea3.ba672c887635bdf0.78fcc448ba3a3b1d.885ede111fac8736
+ 0191015c011501c7.014200af010d01d6.01f5019701da0148.00eb01f7020c00fb
+ e321b79d92aaadb5.2c0a3c729fdea66c.655fd11c6b86d779.cc9b78ee7b1d6db8
+ 2cc27472bea10a3c
+
+VMPSADBW_256_0x24(reg)
+ before
+ d953df40e0131328.707d733afab7c1ca.c77ccfad1e88520f.435d8dad5b74ed73
+ 309cb5c27dfec428.40ed4b61e5cb1e79.1dc011a80925c72f.364a679181a32f30
+ 8de7f26630ef58e7.2f3cbbfe6ff17fec.8c21fbcdfe414278.1af0dcb6f81f56db
+ 4c82939695700c11.19383ffdb635a24f.6fea8a8a9669fe98.cb1c6607ddf221a1
+ 259a83704c2a4aad
+ after
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+ 309cb5c27dfec428.40ed4b61e5cb1e79.1dc011a80925c72f.364a679181a32f30
+ 8de7f26630ef58e7.2f3cbbfe6ff17fec.8c21fbcdfe414278.1af0dcb6f81f56db
+ 4c82939695700c11.19383ffdb635a24f.6fea8a8a9669fe98.cb1c6607ddf221a1
+ 259a83704c2a4aad
+VMPSADBW_256_0x24(mem)
+ before
+ 0435aedc5fd28e2c.c9b793c0490f1b53.daab534bd3a341cf.2168bb496f273839
+ 44bb633935f7a94a.60d3ee4fe758c359.4e6274d2e4481998.00e78978250a2c07
+ c1f61f72e7a45632.6d21a0af0cd63ecf.51291d800530e5d6.66b3f082539b16af
+ 57b35c7494e55211.4cefa54c5315c960.bfccca3f516562b4.b118ecd3956832dd
+ 3b617ad788fcbb3c
+ after
+ 0435aedc5fd28e2c.c9b793c0490f1b53.daab534bd3a341cf.2168bb496f273839
+ 44bb633935f7a94a.60d3ee4fe758c359.4e6274d2e4481998.00e78978250a2c07
+ 0102010201680193.0184016001a501b2.019f016b01500114.00ce01ad014f01bf
+ 57b35c7494e55211.4cefa54c5315c960.bfccca3f516562b4.b118ecd3956832dd
+ 3b617ad788fcbb3c
+
+VMPSADBW_256_0x24(reg)
+ before
+ 62dc95fac8e4ee79.e2be982955c75912.5987fa9259a19fb8.7416f7fde4f54c5e
+ 80d339a9efab063f.3de34e7e48552662.f0379aedb907fd84.4cd520a5dbec5f01
+ f293624e9cdd403c.46eefb60899b772c.6d4981ca0fd21f70.22d3c223515456c9
+ 15680d566907d819.d8ab19b933a6069d.2c0aab93f88f4127.d4dd5863633befe1
+ 3dbf5e512cade376
+ after
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+ 80d339a9efab063f.3de34e7e48552662.f0379aedb907fd84.4cd520a5dbec5f01
+ f293624e9cdd403c.46eefb60899b772c.6d4981ca0fd21f70.22d3c223515456c9
+ 15680d566907d819.d8ab19b933a6069d.2c0aab93f88f4127.d4dd5863633befe1
+ 3dbf5e512cade376
+VMPSADBW_256_0x24(mem)
+ before
+ 394550d9c9b4f1b4.439e342ef2b40a84.cfe5267763818fe1.89c615b510c89e56
+ a33babe7555fd3c6.d980d541d4701229.06699d853438d024.dfc8ba9df20c73a9
+ 596cea68edb746d9.345cebfaaac82bb4.5b03facfc2d88390.8c5e96b63ae4fccb
+ 35a68946acca0618.ae7c73c7104792d0.a97fba402a6c6554.ebd2a56c85de7569
+ 5872e32a6f85192e
+ after
+ 394550d9c9b4f1b4.439e342ef2b40a84.cfe5267763818fe1.89c615b510c89e56
+ a33babe7555fd3c6.d980d541d4701229.06699d853438d024.dfc8ba9df20c73a9
+ 01cc00ea010e01fd.01c301040118015b.00bf015801e90118.0133021700b90132
+ 35a68946acca0618.ae7c73c7104792d0.a97fba402a6c6554.ebd2a56c85de7569
+ 5872e32a6f85192e
+
+VMPSADBW_256_0x24(reg)
+ before
+ 2e884d5e936625c7.15b3046fafa3ceb0.a42d6713a4798229.cba957c68701319a
+ cb61de738d0cd5e0.d360d8cd114e5bcc.72bbc54affeb396d.9f4d4f4df6a1a58f
+ 8a4892d6fa036424.4d797f4eefd86999.747288d8bf28f145.ff361dbf935b7b5e
+ c68b65f175d70f3f.5dca77dd644cb443.069dac2980bde760.c9323d0978386f34
+ d70b2c17c4463f3c
+ after
+ 00aa0127016001e1.019700c5005c0137.016401540182014d.00c900a100a70057
+ cb61de738d0cd5e0.d360d8cd114e5bcc.72bbc54affeb396d.9f4d4f4df6a1a58f
+ 8a4892d6fa036424.4d797f4eefd86999.747288d8bf28f145.ff361dbf935b7b5e
+ c68b65f175d70f3f.5dca77dd644cb443.069dac2980bde760.c9323d0978386f34
+ d70b2c17c4463f3c
+VMPSADBW_256_0x24(mem)
+ before
+ 068e65d69090a5a3.dd7454319b1512df.e11e3b668cb7f7f5.848a2daadd345668
+ 33876331fb225e95.29515a030749a9ae.b34347d58423efdc.4a8308c5721b7b09
+ 38c1a5131e09253d.086c73d156fd0f58.b1031816689e5824.b4d638e7dcfe92f1
+ f20aa46a1850b8c8.d4129b0923bf818a.b52b29155334edf8.1ecdb97db768d7c9
+ e4b487f29ee58540
+ after
+ 068e65d69090a5a3.dd7454319b1512df.e11e3b668cb7f7f5.848a2daadd345668
+ 33876331fb225e95.29515a030749a9ae.b34347d58423efdc.4a8308c5721b7b09
+ 009d01fa01e10103.01fb016200de01d2.014801aa01120177.021900e100a4018d
+ f20aa46a1850b8c8.d4129b0923bf818a.b52b29155334edf8.1ecdb97db768d7c9
+ e4b487f29ee58540
+
+VMPSADBW_256_0x1d(reg)
+ before
+ 62d99fb12d01d900.3e2cde210204d162.eb8ece150b1a3bf0.9c87f6bf61f06c84
+ f487fc2801490fb5.f6f5cd24fa302c36.a72e0963a99b7835.42e3fbfeafde8ef6
+ f6099ac2b548630c.f72fef5f1ce08770.653d475e99cd7506.840bb4c0580a1277
+ c4ac75ebe68b10b1.1da7c0be83209c3e.82068472783c6e0e.3cca9eef7981b236
+ 47ee34792d4f2b5d
+ after
+ 01020222019401bd.0173013602c30125.00c001030120017c.018100cb00f0019f
+ f487fc2801490fb5.f6f5cd24fa302c36.a72e0963a99b7835.42e3fbfeafde8ef6
+ f6099ac2b548630c.f72fef5f1ce08770.653d475e99cd7506.840bb4c0580a1277
+ c4ac75ebe68b10b1.1da7c0be83209c3e.82068472783c6e0e.3cca9eef7981b236
+ 47ee34792d4f2b5d
+VMPSADBW_256_0x1d(mem)
+ before
+ 8141f249917e3919.babc890f2f9d5350.4528ba2d4bfd28c9.58d6bc0be2759ffa
+ c690544ac01c9895.3385d39b2d0a6793.49805b999182e740.44f9ec9572034376
+ f2a7d76ad73403fe.8d534ef97b5e8a29.06791eec71bc94cd.a2bb0e7dc472972d
+ e151f595f1d3377f.2372f696b626f6bc.58e17f1306b6ec9c.cf68202d754fd7cc
+ 254b1d1321253eff
+ after
+ 8141f249917e3919.babc890f2f9d5350.4528ba2d4bfd28c9.58d6bc0be2759ffa
+ c690544ac01c9895.3385d39b2d0a6793.49805b999182e740.44f9ec9572034376
+ 012f016601190103.010901b001340160.014c00e2019c00ed.00f0028b01c800f1
+ e151f595f1d3377f.2372f696b626f6bc.58e17f1306b6ec9c.cf68202d754fd7cc
+ 254b1d1321253eff
+
+VMPSADBW_256_0x1d(reg)
+ before
+ 01b2029962800a71.705c2cb52b04ef45.502dc7df79ede8f9.1b82fafb6c7cabdb
+ bfe7c92dd7ed75ce.7892f8b7a0d3e97b.72d2bd3f61409b8b.2b290c8fc01b8cb3
+ bb3770391af7bbc3.d8c1d3876c4ddf4f.e4abd52109aa4d1f.64a230bb1d9e4d53
+ 51eef22bc72b1afc.6bb33b12ac7d8eea.01050af30db73861.a2b8e26ba011a7e5
+ c1399e8a64815995
+ after
+ 010d013e013501a4.0198018701800172.00f2016800960100.011600e501540102
+ bfe7c92dd7ed75ce.7892f8b7a0d3e97b.72d2bd3f61409b8b.2b290c8fc01b8cb3
+ bb3770391af7bbc3.d8c1d3876c4ddf4f.e4abd52109aa4d1f.64a230bb1d9e4d53
+ 51eef22bc72b1afc.6bb33b12ac7d8eea.01050af30db73861.a2b8e26ba011a7e5
+ c1399e8a64815995
+VMPSADBW_256_0x1d(mem)
+ before
+ 9defe00786f91d90.dd584b6e7b13cc25.0d35aa427c6fb17b.272c58200af498fc
+ 11a725cb2185b102.bbc0786ed13e0de9.9a129e05f730052c.b06bbc149cecab9c
+ fb2de8c35232ce17.4774749765351bf4.ee18934639cb4629.fa10303b5e2babef
+ 364da5db340b33fa.ddbe3b56d58630f3.e51103f05f4c309f.5f65b201ec3ed59e
+ 3cb83dd2e3af6458
+ after
+ 9defe00786f91d90.dd584b6e7b13cc25.0d35aa427c6fb17b.272c58200af498fc
+ 11a725cb2185b102.bbc0786ed13e0de9.9a129e05f730052c.b06bbc149cecab9c
+ 01e801df0160011c.01d600ec00f5029a.01b1014d01300133.00ec00c501380138
+ 364da5db340b33fa.ddbe3b56d58630f3.e51103f05f4c309f.5f65b201ec3ed59e
+ 3cb83dd2e3af6458
+
+VMPSADBW_256_0x1d(reg)
+ before
+ ee53cd1bde0d96c7.9ed3d800e41c9ad7.d9ebc915babc8992.5bcb6cf184c07eba
+ cf835f467ae1a598.0e8bfe1c7d72c0db.97471a41b263627c.2b104934c532eea6
+ 3c93edc152b9cd76.6440911d1b186132.731e2b475908f65e.33ad16a53eae398d
+ 92d175f603214c0e.7bbf0feedb1a3807.c8bcf6914a3682e4.4e6e4f3109411e9e
+ 571e71c245f65703
+ after
+ 01bf0183018000ec.01cf01f800b200a9.00df016300a3013e.015b010a012d0149
+ cf835f467ae1a598.0e8bfe1c7d72c0db.97471a41b263627c.2b104934c532eea6
+ 3c93edc152b9cd76.6440911d1b186132.731e2b475908f65e.33ad16a53eae398d
+ 92d175f603214c0e.7bbf0feedb1a3807.c8bcf6914a3682e4.4e6e4f3109411e9e
+ 571e71c245f65703
+VMPSADBW_256_0x1d(mem)
+ before
+ 2c8bf7450bd9a1e9.2b87f25328a35c0b.2ed4f47bd9850287.f46c798d217a42b9
+ a77f5da779f7b87b.640361435ecd3a1a.5b4bbab030647bde.527cb0a67b5f728a
+ a6c81fd2ab5b57e6.998fbc32402b22e7.ddf0df79fcc35f37.3d369548f4714d02
+ 0430b9b4bc113b56.2678018c6b484f1d.8f8fddc25aaf69be.13e726df273d10ce
+ 2fdb5ed7b04df79a
+ after
+ 2c8bf7450bd9a1e9.2b87f25328a35c0b.2ed4f47bd9850287.f46c798d217a42b9
+ a77f5da779f7b87b.640361435ecd3a1a.5b4bbab030647bde.527cb0a67b5f728a
+ 0193017101860158.0120019e0079015c.018b00f000a7011f.013f012300560102
+ 0430b9b4bc113b56.2678018c6b484f1d.8f8fddc25aaf69be.13e726df273d10ce
+ 2fdb5ed7b04df79a
+
+VMPSADBW_256_0x16(reg)
+ before
+ ec5e399c2c303d11.9c84a838c92620f6.680a2bbd7ab0fe69.4ff33277653356a1
+ a8bbb39a366f1fdf.4b8f674aeda5c2f2.b990363109ef6b76.f7ea5a843a5ce20a
+ be40c83d6b98d9b2.ee1f72d6449bdc78.76581f54b592d1f1.653ecfd6f434c825
+ 893775f26636a634.5ffe45c8eb122bb1.fbace0931a246d86.73bc0f57b0cac51f
+ fe3095f589279524
+ after
+ 00ea014401560103.011f007300ba00e6.020901aa01b101ea.00c200930154017e
+ a8bbb39a366f1fdf.4b8f674aeda5c2f2.b990363109ef6b76.f7ea5a843a5ce20a
+ be40c83d6b98d9b2.ee1f72d6449bdc78.76581f54b592d1f1.653ecfd6f434c825
+ 893775f26636a634.5ffe45c8eb122bb1.fbace0931a246d86.73bc0f57b0cac51f
+ fe3095f589279524
+VMPSADBW_256_0x16(mem)
+ before
+ e365dd9a9c59f45f.66edb523c4d6c411.7cfa5d0cfe196bcc.a4d97758d3317be0
+ fc296334046b9dfd.b2ae843e20036df6.1fdd358e98b957f3.cd2bdf117c4637ac
+ 2646a4aede694d29.c7c6dfae1749dd8f.2574493ad500ad53.d2ee1429b2eedc95
+ 3e8a1bf44560c010.0380c0df44355287.6b8b15fdd2f92617.0f6e130b11b6a848
+ dff6d7253328d471
+ after
+ e365dd9a9c59f45f.66edb523c4d6c411.7cfa5d0cfe196bcc.a4d97758d3317be0
+ fc296334046b9dfd.b2ae843e20036df6.1fdd358e98b957f3.cd2bdf117c4637ac
+ 00d10136012500fc.01320163019601f0.0094017e01b20141.010c028401120172
+ 3e8a1bf44560c010.0380c0df44355287.6b8b15fdd2f92617.0f6e130b11b6a848
+ dff6d7253328d471
+
+VMPSADBW_256_0x16(reg)
+ before
+ a0d45ce2b7d39fbb.1ebf44f2565cb1de.c02a253c4352068b.cbed15c1aab1816c
+ ad529eae364043d3.a3b29b942c67debe.5b0e0933b12c3646.2268c6747a32787d
+ 62bd99f54ffdfd64.a92e9dc6e38f00dd.317969302a501e65.4cc6a3005d8bc877
+ 1b614a249b95091b.0c01c47598dfd667.9cb73f9d4949f994.25d4285370c52d86
+ 895ed158ceee63d5
+ after
+ 013200de01600131.0166018902260132.00c4010a00a700e2.0087001d00f500d7
+ ad529eae364043d3.a3b29b942c67debe.5b0e0933b12c3646.2268c6747a32787d
+ 62bd99f54ffdfd64.a92e9dc6e38f00dd.317969302a501e65.4cc6a3005d8bc877
+ 1b614a249b95091b.0c01c47598dfd667.9cb73f9d4949f994.25d4285370c52d86
+ 895ed158ceee63d5
+VMPSADBW_256_0x16(mem)
+ before
+ 54301bfb94112591.338aaca5b995a2a3.a8f58e8b67641a87.f91489e7aaa3047e
+ 63168028dd3b30e5.0884bbe5428805aa.59d876f66a298a69.a4dc427aeaeb7bd0
+ 90db7ecbc6773ffe.f59a7351d4fa6ed9.fb74f9a0c03adf3a.fa5b66c3a5ac9935
+ b84d90d16ad11008.5519d0530b7719df.6a96917783a3d826.55dcf12c75729b5a
+ 12ace023f9cabdeb
+ after
+ 54301bfb94112591.338aaca5b995a2a3.a8f58e8b67641a87.f91489e7aaa3047e
+ 63168028dd3b30e5.0884bbe5428805aa.59d876f66a298a69.a4dc427aeaeb7bd0
+ 01c1016200e301e9.01c9012101710102.017c014f00a700cc.00d00107014900ea
+ b84d90d16ad11008.5519d0530b7719df.6a96917783a3d826.55dcf12c75729b5a
+ 12ace023f9cabdeb
+
+VMPSADBW_256_0x16(reg)
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+VBROADCASTI128(reg)
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+VEXTRACTI128_0x0(reg)
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+VEXTRACTI128_0x0(reg)
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+VEXTRACTI128_0x0(mem)
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+VEXTRACTI128_0x0(reg)
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+ 0000000000000000.0000000000000000.e0326326fcfa54a3.bd603c39d7a99922
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+VEXTRACTI128_0x0(mem)
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+ 0d62e8cc8c0619cb.7ef608e4454435a0.8937bf4399f070e5.af74b1ee10195cec
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+VEXTRACTI128_0x1(reg)
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+ 0000000000000000.0000000000000000.cf037028c1b0bf6b.bf821f3bfda564ee
+ ec365d94028b62f0
+VEXTRACTI128_0x1(mem)
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+VEXTRACTI128_0x1(reg)
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+ 0000000000000000.0000000000000000.4b45e215c0dc9436.6af6ccb1d2947f31
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+VEXTRACTI128_0x1(mem)
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+VEXTRACTI128_0x1(reg)
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+ 0000000000000000.0000000000000000.9f5edea1fe53d69c.7a1ed84411381737
+ 7632c66d8b220670
+VEXTRACTI128_0x1(mem)
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+VINSERTI128_0x0(reg)
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+ 57ace2e02e17497d
+VINSERTI128_0x0(mem)
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+ f194345aacd9990c
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+VINSERTI128_0x0(reg)
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+ c6f05728ea7e4d6f
+VINSERTI128_0x0(mem)
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+VINSERTI128_0x0(reg)
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+VINSERTI128_0x1(reg)
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+ c6fd74754da43c45
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+VINSERTI128_0x1(reg)
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+ fdd58fe124901dbd
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+VINSERTI128_0x1(reg)
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+VPERM2I128_0x00(reg)
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+VPERM2I128_0x00(mem)
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+VPERM2I128_0x00(reg)
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+ a6d07759aa55bc8f
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+VPERM2I128_0x00(reg)
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+ 15655a90a961c3d1
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+VPERM2I128_0xFF(reg)
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+ f077d14df6967fda
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+ 6b6d6b67ff7ca396
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+VPERM2I128_0xFF(reg)
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+ 3ba49c12d289d4c8.832e7892771af6d8.144c2a5f19a03125.a49c1b9b15997c3e
+ 216a1ba18963e1ed
+VPERM2I128_0xFF(mem)
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+ 91e9ee00cb51216a.3ea9d8463b877b76.86a2bc08bb7bab4d.9069a654fa042bc7
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+ 8b2901e457d13a8d
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+VPERM2I128_0xFF(reg)
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+ e4822445b98ab9cb.5ebd70dfc0e013b3.dd65f74a6a5446de.4e98378d0aa71e7e
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+ a6545620c8000472.a525bb8a62059a8b.a8bf34224238e6db.a26906da4105fafa
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+ c2b72a01e942bdac
+VPERM2I128_0xFF(mem)
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+ 3ee58e61ee2873d0.94ef3b6cc255dd99.3a2f94c0cc3671e5.1c8ec9a140b68c7f
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+ 393b526d3de848c4
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+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ f55112593218fcc6.acc3edf12a2741ea.7d3374226b1ab806.67dc65fb3a2f4eb5
+ 393b526d3de848c4
+
+VPERM2I128_0x30(reg)
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+ 671c768a50c8fe01.9869ff93f29406aa.bc8401c21e820e3f.11b12ea53a37d636
+ 86afa404906c4555
+VPERM2I128_0x30(mem)
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+ 19a577c71cab6da7
+
+VPERM2I128_0x30(reg)
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+ 0103119eda7a8785
+VPERM2I128_0x30(mem)
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+ e76a21ed77083ef0.2581fa299f982e8c.1058c92005415e97.2dd0974af8688694
+ adc7671741642804
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+VPERM2I128_0x30(reg)
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+ a7c4da260367733a
+VPERM2I128_0x30(mem)
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+ 5964fae4d5bcd908
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+VPERM2I128_0x21(reg)
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+ cb654451278cd8d2
+VPERM2I128_0x21(mem)
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+ 619de612e6bcbe42
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+VPERM2I128_0x21(reg)
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+ a0b779333fa3660a
+VPERM2I128_0x21(mem)
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+ c20c259dec5e95f7.33520d47143f1a09.af8c43532f5d1cf0.089938d71758fc0b
+ e8f3c4e75ecff99f
+
+VPERM2I128_0x21(reg)
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+ 3aea7f4429c4adff
+VPERM2I128_0x21(mem)
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+ d37dac8fbe50261a.6c761212df09ceb6.75d0a8b5cc6475ce.83bd03c2e01864b6
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+ d37dac8fbe50261a.6c761212df09ceb6.75d0a8b5cc6475ce.83bd03c2e01864b6
+ f2490c0808bd886c
+
+VPERM2I128_0x12(reg)
+ before
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+ f2bae4c8ad670be6.52dd0c11bddd37db.e5ff2a94fd19a424.740b3644dbe9d91d
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+ 8d923d58a0691c2e
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+ da46a89c7b376def.1ccc1dfc0ac3ab3f.8e0b37520c36e1c8.063e7e64ffb027b7
+ 8d923d58a0691c2e
+VPERM2I128_0x12(mem)
+ before
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+ 61ac5ea489c64e4c.894d3ae5548c8de6.12abbfae856262a5.46fb18adedc16502
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+ f9ade8f0b8541b24.e030790216c64d2b.14d9d28a0e1a3b6d.ee2eae047f191033
+ 63df137c91b04a56
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+ 61ac5ea489c64e4c.894d3ae5548c8de6.12abbfae856262a5.46fb18adedc16502
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+ f9ade8f0b8541b24.e030790216c64d2b.14d9d28a0e1a3b6d.ee2eae047f191033
+ 63df137c91b04a56
+
+VPERM2I128_0x12(reg)
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+ 57ebfd215370b30c.35f5bb9d0d736416.bf4f4454a2468c1f.02b735ed844c18f8
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+ 6b9e7ca43e6d0277
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+ 57ebfd215370b30c.35f5bb9d0d736416.bf4f4454a2468c1f.02b735ed844c18f8
+ 8fde7a273ab15bf8.96325605ecd70c87.c8b255fe9a5e9188.3846dba03f511d34
+ 6b2a4c33f6edf429.f5e5b70a68830783.06087c39d86b2921.bca4ca39c957d7a5
+ 6b9e7ca43e6d0277
+VPERM2I128_0x12(mem)
+ before
+ 22016fcebb9c59d5.471b6fb323b1ba4c.2cda5a969e841035.d79db772f9fa9195
+ bb971ea15bf299eb.7ffddf115c88eb0c.18dcbb97a9e5e5ca.95bd011398960592
+ 132c050a3b7a7ee7.6f1c99bb3dffc116.96b957f8a6b3406e.9eb4578a52cbc1c1
+ 068ea1f67741c4f2.72c4971c63a17816.803ba9a5b0f9dd4c.4cceb342c22601d0
+ fd5613a78432006b
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+ bb971ea15bf299eb.7ffddf115c88eb0c.18dcbb97a9e5e5ca.95bd011398960592
+ bb971ea15bf299eb.7ffddf115c88eb0c.2cda5a969e841035.d79db772f9fa9195
+ 068ea1f67741c4f2.72c4971c63a17816.803ba9a5b0f9dd4c.4cceb342c22601d0
+ fd5613a78432006b
+
+VPERM2I128_0x12(reg)
+ before
+ 0b9a7225357bfb3e.71876c4f2951263b.e640d7a069fa4eb7.b32f2d8ae3c37a90
+ d3e4cd28718e2df4.2ee5e40370b961ec.26dd54b3ec967da6.0b615f935c1dd168
+ b1811e1cd3f6d439.1a7284fd65823131.8ee70bc18702428e.649dbbac37149ffd
+ 02bd636df73f2abb.11fbc82927ba5238.7aaaf636d7c9d91c.9aaebec28fb49f7e
+ 8a62e3bf80078f15
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+ d3e4cd28718e2df4.2ee5e40370b961ec.26dd54b3ec967da6.0b615f935c1dd168
+ b1811e1cd3f6d439.1a7284fd65823131.8ee70bc18702428e.649dbbac37149ffd
+ 02bd636df73f2abb.11fbc82927ba5238.7aaaf636d7c9d91c.9aaebec28fb49f7e
+ 8a62e3bf80078f15
+VPERM2I128_0x12(mem)
+ before
+ 0e83a691271b29ee.20e497887af66b24.ef4c2d73cf6c7f2a.4572137f77787dfb
+ 03de8322a0fb2a37.6841b6d7f8a6d520.90312ec77ca57536.4d8b5d06049a6bd9
+ 453ff76005b44d19.3621bcc80bdba25c.d07547114770ef86.ed40d13919bbdf5f
+ b0727d3675514fc3.e6d1a6c552220f84.8be6f43d4ed9ab46.80de69825368153c
+ 64b2234f4d2b4819
+ after
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+ 03de8322a0fb2a37.6841b6d7f8a6d520.90312ec77ca57536.4d8b5d06049a6bd9
+ 03de8322a0fb2a37.6841b6d7f8a6d520.ef4c2d73cf6c7f2a.4572137f77787dfb
+ b0727d3675514fc3.e6d1a6c552220f84.8be6f43d4ed9ab46.80de69825368153c
+ 64b2234f4d2b4819
+
+VPERM2I128_0x03(reg)
+ before
+ f306fa0ba393b5a5.204391900adeec5f.d49b6f3c67065843.9d4eb137aded63a4
+ 8b27ea22f229988a.707daf5ae068e019.5ccc1398e613b846.e27afbec7fb7d4c9
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+ 42ff0611ea14ae11.2560faeec1a0bb9a.aa92ddaf94dab0c6.754e2333ed9ecf1f
+ 7b8df99ec2d3d2a6
+ after
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+ 8b27ea22f229988a.707daf5ae068e019.5ccc1398e613b846.e27afbec7fb7d4c9
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+ 42ff0611ea14ae11.2560faeec1a0bb9a.aa92ddaf94dab0c6.754e2333ed9ecf1f
+ 7b8df99ec2d3d2a6
+VPERM2I128_0x03(mem)
+ before
+ 24c14b737aee7ea6.194e2ac1ca815a0b.41a01f9003671bb9.28c0fa42faacbf9c
+ 4bb4969e31fc8e4b.699a577c134d6c0e.ae7a3e53f85ac2a5.b084e36a3cd6d765
+ ce33550b0408bfc1.8c2f89ae60041fc7.48b9d321b9856b8d.9e2b9394f3e731cd
+ 880a04a60e1ecd32.df59bcc44e33b0e2.ea2b5be864f5d39b.4e01072abd680c82
+ 1c52399a36e7a32e
+ after
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+ 4bb4969e31fc8e4b.699a577c134d6c0e.ae7a3e53f85ac2a5.b084e36a3cd6d765
+ ae7a3e53f85ac2a5.b084e36a3cd6d765.24c14b737aee7ea6.194e2ac1ca815a0b
+ 880a04a60e1ecd32.df59bcc44e33b0e2.ea2b5be864f5d39b.4e01072abd680c82
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+VBROADCASTSS_256(reg)
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+VBROADCASTSS_256(reg)
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+VBROADCASTSS_256(reg)
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+VBROADCASTSD_256(reg)
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+VBROADCASTSD_256(reg)
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+VBROADCASTSD_256(reg)
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+ b51a22817e217d4d
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+VPERMD(reg)
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+VPERMD(mem)
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+VPERMD(reg)
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+ e96c4e04f2c6607c
+VPERMD(mem)
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+VPERMD(reg)
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+VPERMD(mem)
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+VPERMQ_0x00(reg)
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+VPERMQ_0x29(reg)
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+VPERMQ_0x29(reg)
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+VPERMPS(reg)
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+VPERMPS(reg)
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+VPERMPS(reg)
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+VPERMPD_0x00(reg)
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+VPERMPD_0x00(reg)
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+VPERMPD_0x00(reg)
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+VPERMPD_0xFE(reg)
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+ d7e9e89e8dec0a19.0e563506a4844532.efeaa4680f7b1e4e.a0728f9a9d7f7bad
+ d15a5f7f19fcc813.5a26c603d67447d2.99c6b7b19aacd059.be2f5244bbfa914c
+ 6dc5504fc9e22efa
+ after
+ d7e9e89e8dec0a19.d7e9e89e8dec0a19.d7e9e89e8dec0a19.0e563506a4844532
+ 264f7c931c769453.a6ba60b395bb2c4a.a1ffdfff905dd5e1.36c38a63566430f1
+ d7e9e89e8dec0a19.0e563506a4844532.efeaa4680f7b1e4e.a0728f9a9d7f7bad
+ d15a5f7f19fcc813.5a26c603d67447d2.99c6b7b19aacd059.be2f5244bbfa914c
+ 6dc5504fc9e22efa
+VPERMPD_0xFE(mem)
+ before
+ 8a0104a6e5420ee2.71eedea15b3009ec.64f68f964896ee58.fbdf1245cd7c28ad
+ efafea352b26ed30.14f06070ef160a51.09910dac15f7f6ed.7180b390457862f6
+ 799b7ee8b69b8611.14aee158723907ed.25c5ba305aa11ac0.56f795fe9d2bb9e1
+ 04913caca2ab96b1.ce725dc580263c6d.955c140d32a317fb.088eb4fb72226b1a
+ e2920cf35fe8b24c
+ after
+ 8a0104a6e5420ee2.71eedea15b3009ec.64f68f964896ee58.fbdf1245cd7c28ad
+ efafea352b26ed30.14f06070ef160a51.09910dac15f7f6ed.7180b390457862f6
+ 8a0104a6e5420ee2.8a0104a6e5420ee2.8a0104a6e5420ee2.8a0104a6e5420ee2
+ 04913caca2ab96b1.ce725dc580263c6d.955c140d32a317fb.088eb4fb72226b1a
+ e2920cf35fe8b24c
+
+VPERMPD_0xFE(reg)
+ before
+ 404f9a520109ca24.6c5da16b0c65d83c.9f89d123b468e47d.33239631ba06a9ca
+ 7e115984f311f14e.8dca281210d20add.e13f38deaa8c3cc8.dce6bd870dd88b5b
+ f72445f6d28d6175.43a54d8ec900e6c0.f1df8d62ff1c80fb.6c7103fb48247bd7
+ 09d35a1239095746.6abb8cca53fa2913.2bb7cf1c4fa6ebc1.bf90e67986f7336d
+ b10fe1ede45c6f47
+ after
+ f72445f6d28d6175.f72445f6d28d6175.f72445f6d28d6175.43a54d8ec900e6c0
+ 7e115984f311f14e.8dca281210d20add.e13f38deaa8c3cc8.dce6bd870dd88b5b
+ f72445f6d28d6175.43a54d8ec900e6c0.f1df8d62ff1c80fb.6c7103fb48247bd7
+ 09d35a1239095746.6abb8cca53fa2913.2bb7cf1c4fa6ebc1.bf90e67986f7336d
+ b10fe1ede45c6f47
+VPERMPD_0xFE(mem)
+ before
+ 1eb970437d5fed91.0e6b9546c50f0e6c.ded662b1cbcd8eff.eb11f77635b6bac7
+ e25b0f686d0d6779.6438f0fd112dc394.7bc24a314c84d2b3.8e3b03de4dd629b9
+ d9c13b46d1719928.668669a2b9eeb269.1d4dc035f32bb159.6e7fedbf34947442
+ dfb76fcbc59741cd.6fa1fba35adf1799.a04240a9dbcfe71d.e82ab385857cd60f
+ 5887519cdd198ccb
+ after
+ 1eb970437d5fed91.0e6b9546c50f0e6c.ded662b1cbcd8eff.eb11f77635b6bac7
+ e25b0f686d0d6779.6438f0fd112dc394.7bc24a314c84d2b3.8e3b03de4dd629b9
+ 1eb970437d5fed91.1eb970437d5fed91.1eb970437d5fed91.1eb970437d5fed91
+ dfb76fcbc59741cd.6fa1fba35adf1799.a04240a9dbcfe71d.e82ab385857cd60f
+ 5887519cdd198ccb
+
+VPERMPD_0xFE(reg)
+ before
+ 1ae4c170d7f7d223.d00927e1648c1992.ddd5a36b908b2ecd.e06c4679217b2f2c
+ 8a8b016d0fa2e4c3.8783df76ca5bdea3.0a6e5b66f67e32b4.b9984f91e03b46b2
+ 03ca0cff23a7fd56.e2f0137514104c2d.54b72101284560f7.0792d6dd351ce8da
+ e3ebde92ac915a89.bc1d40ca5db81e5c.15fdf0a6c36bf345.a626574a3b29d1d1
+ 71204ec20f6ebcc3
+ after
+ 03ca0cff23a7fd56.03ca0cff23a7fd56.03ca0cff23a7fd56.e2f0137514104c2d
+ 8a8b016d0fa2e4c3.8783df76ca5bdea3.0a6e5b66f67e32b4.b9984f91e03b46b2
+ 03ca0cff23a7fd56.e2f0137514104c2d.54b72101284560f7.0792d6dd351ce8da
+ e3ebde92ac915a89.bc1d40ca5db81e5c.15fdf0a6c36bf345.a626574a3b29d1d1
+ 71204ec20f6ebcc3
+VPERMPD_0xFE(mem)
+ before
+ 464b3833ccf866db.853b739348ed3707.f1d7e161c25e115b.aa8cc4c2627c2848
+ 007590878ed28b46.4506c86c9345cf7d.5ce872265f0ee157.70b09ac2a2053bad
+ 7a68d2ac7208e62f.7f97d88b28285f97.db1c70054ed54a7c.c1b56d101e91681f
+ 92f17a8d94a734c3.8f3c9f5aa31f2300.494155eaaebe07f5.fae7381a73aceb4b
+ 7791fa4a3ce3ffdc
+ after
+ 464b3833ccf866db.853b739348ed3707.f1d7e161c25e115b.aa8cc4c2627c2848
+ 007590878ed28b46.4506c86c9345cf7d.5ce872265f0ee157.70b09ac2a2053bad
+ 464b3833ccf866db.464b3833ccf866db.464b3833ccf866db.464b3833ccf866db
+ 92f17a8d94a734c3.8f3c9f5aa31f2300.494155eaaebe07f5.fae7381a73aceb4b
+ 7791fa4a3ce3ffdc
+
+VPERMPD_0x30(reg)
+ before
+ 9500ac0e16c1e17f.23dc04160fba312e.d03f1947a1b85665.81229fc298d5d5ef
+ ae804bd19cd2cce0.08f5ed33ff4d999b.a0ed42bdbe7e3671.618ac9772a277095
+ 1f5dd4ff6ba3feaa.1f08b0d0816d2736.5a93172895fefdd1.c4464ff780bf9314
+ 44e342041ebfb18a.42e0c9d9b025982d.597a93f4c2c3e730.8522ae2cb5a9fb97
+ 82ea6004e6f2644c
+ after
+ c4464ff780bf9314.1f5dd4ff6ba3feaa.c4464ff780bf9314.c4464ff780bf9314
+ ae804bd19cd2cce0.08f5ed33ff4d999b.a0ed42bdbe7e3671.618ac9772a277095
+ 1f5dd4ff6ba3feaa.1f08b0d0816d2736.5a93172895fefdd1.c4464ff780bf9314
+ 44e342041ebfb18a.42e0c9d9b025982d.597a93f4c2c3e730.8522ae2cb5a9fb97
+ 82ea6004e6f2644c
+VPERMPD_0x30(mem)
+ before
+ 956ae36a2ea58a5c.795e914d51b2222b.4f4ab43ba982a8aa.fbf1b28de259323c
+ 9b6eb24aa9cf28f5.1a19be44a1098c3a.2013ede0878f12d9.9a437060904c189e
+ 71c14a90747bfb43.8362c356aa4f2c63.9305f1b5675893e7.94bbcad76929d605
+ f1302528abb5bf72.10839ef007103e51.82ec3ba764e9e700.44a6bb5f087ca71a
+ 05513f650acfc98c
+ after
+ 956ae36a2ea58a5c.795e914d51b2222b.4f4ab43ba982a8aa.fbf1b28de259323c
+ 9b6eb24aa9cf28f5.1a19be44a1098c3a.2013ede0878f12d9.9a437060904c189e
+ fbf1b28de259323c.fbf1b28de259323c.fbf1b28de259323c.956ae36a2ea58a5c
+ f1302528abb5bf72.10839ef007103e51.82ec3ba764e9e700.44a6bb5f087ca71a
+ 05513f650acfc98c
+
+VPERMPD_0x30(reg)
+ before
+ 340652530ab07605.f987c1fe69892fad.1dc94a7c54d9feb1.ca9647a19b4fca4f
+ 2e11f097a5aaea32.639299ffca040820.0680c4682e35a72e.48ce928e2795f701
+ 4dc0169c764a63be.0c1d2915eb3106f9.27f4061f31b17675.d65f965c25c82b41
+ ef5ebfce191b1b56.d0f4ee2ee71de562.dc700e0df7d8a732.5116d1f6b0f2223c
+ 95bfbe48e522971e
+ after
+ d65f965c25c82b41.4dc0169c764a63be.d65f965c25c82b41.d65f965c25c82b41
+ 2e11f097a5aaea32.639299ffca040820.0680c4682e35a72e.48ce928e2795f701
+ 4dc0169c764a63be.0c1d2915eb3106f9.27f4061f31b17675.d65f965c25c82b41
+ ef5ebfce191b1b56.d0f4ee2ee71de562.dc700e0df7d8a732.5116d1f6b0f2223c
+ 95bfbe48e522971e
+VPERMPD_0x30(mem)
+ before
+ 7e26d93edf614712.6e36e7992ba94fa5.8ce26234dbd36087.8142d79e1f367610
+ e9179fc5babdee45.27958a6948813a58.1ab50315e25f3495.72b45d3e43571ebc
+ b05e8ac7934148e2.76c7a4aa0b2e1a1b.57374cbc19cd1db8.0a139d59ffc8dce1
+ b0c6183186fa1016.b81832c8103c2999.1f35b9149b2ad61b.a7ab915bef14eb2c
+ a4c837b0b1c88948
+ after
+ 7e26d93edf614712.6e36e7992ba94fa5.8ce26234dbd36087.8142d79e1f367610
+ e9179fc5babdee45.27958a6948813a58.1ab50315e25f3495.72b45d3e43571ebc
+ 8142d79e1f367610.8142d79e1f367610.8142d79e1f367610.7e26d93edf614712
+ b0c6183186fa1016.b81832c8103c2999.1f35b9149b2ad61b.a7ab915bef14eb2c
+ a4c837b0b1c88948
+
+VPERMPD_0x30(reg)
+ before
+ 5db58ac5de6ff0e2.c51cc4f0adf3030d.47d42f30f438a37f.4e7bc70b85821deb
+ 2dc0860414955da6.cb2d0bef2738ddf2.8046974c53adc678.c0d4f18df2dfac53
+ 723328dbefc60b40.9ec367190ed65af2.bfbc678ac728cc31.510eb384ff4f3f80
+ 865b6ab40a8f385a.1aaa565c7ed83538.60809954ef33f256.ddf389ddc7dd949e
+ 4051ef84669665d8
+ after
+ 510eb384ff4f3f80.723328dbefc60b40.510eb384ff4f3f80.510eb384ff4f3f80
+ 2dc0860414955da6.cb2d0bef2738ddf2.8046974c53adc678.c0d4f18df2dfac53
+ 723328dbefc60b40.9ec367190ed65af2.bfbc678ac728cc31.510eb384ff4f3f80
+ 865b6ab40a8f385a.1aaa565c7ed83538.60809954ef33f256.ddf389ddc7dd949e
+ 4051ef84669665d8
+VPERMPD_0x30(mem)
+ before
+ 56f26266f9856e5b.c7844afd027c1ea3.1bb053a3944a2bf1.bfdf2b18655c7492
+ fba35d6d9cb66d52.8ffac4217217f9c5.7da0dada6b38f749.38251841c52f8d92
+ 0b305c876a361cea.3c09d28cf6ee076d.1c4568ed20af576b.279e5c3bac377a01
+ 6264db9f7f10384e.28fc72aa2b8c8246.d46c77c8cebb0584.e895f472b500778c
+ d758db527c16bfdf
+ after
+ 56f26266f9856e5b.c7844afd027c1ea3.1bb053a3944a2bf1.bfdf2b18655c7492
+ fba35d6d9cb66d52.8ffac4217217f9c5.7da0dada6b38f749.38251841c52f8d92
+ bfdf2b18655c7492.bfdf2b18655c7492.bfdf2b18655c7492.56f26266f9856e5b
+ 6264db9f7f10384e.28fc72aa2b8c8246.d46c77c8cebb0584.e895f472b500778c
+ d758db527c16bfdf
+
+VPERMPD_0x21(reg)
+ before
+ 50310c479f0690a5.db0d56a0f8507dac.b1219ee7ac7ea7fd.80e185589266bebf
+ af6d86beb75b248b.54f54a78f103a62d.31c254b0164fb13d.fe700d8787be3d49
+ 5058422162a1b73c.a8e9321284347000.062c906f058bdeb3.29e58c42c9cf3f4e
+ 8f3e3dde3c658765.b3b58a5ad0ef974f.8aab4c9113bf680b.dd0b7c7675a380f9
+ f5b05b0ea749bc77
+ after
+ 29e58c42c9cf3f4e.a8e9321284347000.29e58c42c9cf3f4e.062c906f058bdeb3
+ af6d86beb75b248b.54f54a78f103a62d.31c254b0164fb13d.fe700d8787be3d49
+ 5058422162a1b73c.a8e9321284347000.062c906f058bdeb3.29e58c42c9cf3f4e
+ 8f3e3dde3c658765.b3b58a5ad0ef974f.8aab4c9113bf680b.dd0b7c7675a380f9
+ f5b05b0ea749bc77
+VPERMPD_0x21(mem)
+ before
+ 4f9ea4f57acaaff3.c86b745fe032ceb2.5025ce3def41d746.1a8b8683df768bf0
+ c6a2d3190a34149a.562ae212ea95c9ce.5d057ba5fd35eb12.131739b0023c850f
+ 358865657492a797.97c98362f719b366.b4200c7f16d790df.cf9d61831b9e9014
+ 7a1cd4c5d4f02617.e69254baa34ac925.3344fdb8583482d8.ab67fa6ac327e9aa
+ 03c201d09963cc7d
+ after
+ 4f9ea4f57acaaff3.c86b745fe032ceb2.5025ce3def41d746.1a8b8683df768bf0
+ c6a2d3190a34149a.562ae212ea95c9ce.5d057ba5fd35eb12.131739b0023c850f
+ 1a8b8683df768bf0.5025ce3def41d746.1a8b8683df768bf0.c86b745fe032ceb2
+ 7a1cd4c5d4f02617.e69254baa34ac925.3344fdb8583482d8.ab67fa6ac327e9aa
+ 03c201d09963cc7d
+
+VPERMPD_0x21(reg)
+ before
+ 33fa702136df743a.6f2a9e25455b4b46.9ed2508889b547b8.b53bca3adc577c2a
+ 975b45c938261e8d.f27d3e71e3ded34f.1dd5723845e469ca.15d2f0f3c04d3b01
+ 8c317c343bc50622.dde23096cb857a5f.bee6b93474666a08.31d5e9ce20207b88
+ 6cc70fcfda4667a4.0e26f17e185dfba2.dc531ee9b1c4881e.e30f33b717def8eb
+ 084e499ac2936d58
+ after
+ 31d5e9ce20207b88.dde23096cb857a5f.31d5e9ce20207b88.bee6b93474666a08
+ 975b45c938261e8d.f27d3e71e3ded34f.1dd5723845e469ca.15d2f0f3c04d3b01
+ 8c317c343bc50622.dde23096cb857a5f.bee6b93474666a08.31d5e9ce20207b88
+ 6cc70fcfda4667a4.0e26f17e185dfba2.dc531ee9b1c4881e.e30f33b717def8eb
+ 084e499ac2936d58
+VPERMPD_0x21(mem)
+ before
+ 7d5da7633c4a97f9.946bfc04b1377ebf.5f13fc17e7711443.d5669ec3998cfcb7
+ 1c07cafea10f32fa.60673d415d248720.ad75cc4b53ce7f6e.036d362fc7490580
+ c3192d570eeef988.2c08d1f07a98be73.d51ae008797ff851.c4b2e197d888dd25
+ 4c5f4c5a9ef4a9cf.539ab17fa31f5e64.b1cdb13974903c16.72829b6967d4c151
+ 6b29611011b9edb1
+ after
+ 7d5da7633c4a97f9.946bfc04b1377ebf.5f13fc17e7711443.d5669ec3998cfcb7
+ 1c07cafea10f32fa.60673d415d248720.ad75cc4b53ce7f6e.036d362fc7490580
+ d5669ec3998cfcb7.5f13fc17e7711443.d5669ec3998cfcb7.946bfc04b1377ebf
+ 4c5f4c5a9ef4a9cf.539ab17fa31f5e64.b1cdb13974903c16.72829b6967d4c151
+ 6b29611011b9edb1
+
+VPERMPD_0x21(reg)
+ before
+ 09f22df771c49cf0.94a5a3f46e2cfefa.3368da597445a59e.1e59bdc9610d07e9
+ a92bfd8c23800cbb.77b6ae0f9aa3b436.27c049e98a97cccd.f98b7ea65b0315f7
+ a81ecc3ac47977bd.d260ea993c6486ae.8becf99d80a0129e.1c2f72bb7e7d226c
+ 6018976df03c19a3.7f6dd27c737b318f.bb3ae6e0f3edb1bd.641115f5e788e973
+ adfde13eb22f2739
+ after
+ 1c2f72bb7e7d226c.d260ea993c6486ae.1c2f72bb7e7d226c.8becf99d80a0129e
+ a92bfd8c23800cbb.77b6ae0f9aa3b436.27c049e98a97cccd.f98b7ea65b0315f7
+ a81ecc3ac47977bd.d260ea993c6486ae.8becf99d80a0129e.1c2f72bb7e7d226c
+ 6018976df03c19a3.7f6dd27c737b318f.bb3ae6e0f3edb1bd.641115f5e788e973
+ adfde13eb22f2739
+VPERMPD_0x21(mem)
+ before
+ d3bf5483fa7e97e9.2e65589242542f19.5baae2a658f57105.13f40d1f7e09e6d5
+ b222e9b1db82f7b0.6f510d13564df5ca.42e396020adc013b.ee6768c4be80ed93
+ 26f31cb2724501ba.7d28b15dc9b4a763.10e46b7ca23f9f5e.aadef53c4ede01a3
+ 0cff6974dbd67232.b53540dd3714818f.a179dc003e270599.a2a7aff3cbb05fb0
+ 310d9256d0814367
+ after
+ d3bf5483fa7e97e9.2e65589242542f19.5baae2a658f57105.13f40d1f7e09e6d5
+ b222e9b1db82f7b0.6f510d13564df5ca.42e396020adc013b.ee6768c4be80ed93
+ 13f40d1f7e09e6d5.5baae2a658f57105.13f40d1f7e09e6d5.2e65589242542f19
+ 0cff6974dbd67232.b53540dd3714818f.a179dc003e270599.a2a7aff3cbb05fb0
+ 310d9256d0814367
+
+VPERMPD_0xD7(reg)
+ before
+ b55b9bd0f9dee973.3e104de1303e0545.73c6b6fd3af9befb.d16e647afaa2ef19
+ 89dec5cce4528c81.98f243e7908b771e.1325102b71f09b53.7c8e82d7f1bb1b0a
+ 08e20cb82a69693c.f873c77114c984ea.f19f49d275845342.7ea6af01407f4397
+ 90b36cff69b0bc51.395e556bdb02e8d5.69805d5de5422475.b38269e502f923ed
+ f7ee2a7053357937
+ after
+ 08e20cb82a69693c.f19f49d275845342.f19f49d275845342.08e20cb82a69693c
+ 89dec5cce4528c81.98f243e7908b771e.1325102b71f09b53.7c8e82d7f1bb1b0a
+ 08e20cb82a69693c.f873c77114c984ea.f19f49d275845342.7ea6af01407f4397
+ 90b36cff69b0bc51.395e556bdb02e8d5.69805d5de5422475.b38269e502f923ed
+ f7ee2a7053357937
+VPERMPD_0xD7(mem)
+ before
+ 26b6708c5040ffa2.7b9de10d3db2c06c.377e69c1fe445e0a.d714483a5ab44897
+ 1ca6b7271525725a.27eb684e40fbb238.cea0805f9c9aa3b6.97a706d47369fc55
+ b489792cbcf08e8a.eeebfb2e1117ce62.da901532ce117304.05849497c9ea7b5b
+ cc2c348764ae0e5f.2ee798194a935096.371aa424b2b48a21.7df8edf0fac50254
+ 5b4f0d49a285cded
+ after
+ 26b6708c5040ffa2.7b9de10d3db2c06c.377e69c1fe445e0a.d714483a5ab44897
+ 1ca6b7271525725a.27eb684e40fbb238.cea0805f9c9aa3b6.97a706d47369fc55
+ 377e69c1fe445e0a.7b9de10d3db2c06c.26b6708c5040ffa2.d714483a5ab44897
+ cc2c348764ae0e5f.2ee798194a935096.371aa424b2b48a21.7df8edf0fac50254
+ 5b4f0d49a285cded
+
+VPERMPD_0xD7(reg)
+ before
+ fbd5f10f5cb618d1.3f5c6324276aaf04.412c3b7c87fb737f.c00aa922648fa338
+ b9d693afc5e51ead.e9e382ef21302da6.8406dec165d974c9.532ba119ffaf7b77
+ f09ef193789d1c2d.a58d0dd46f0d4470.54c07f567fbb8f22.cb4b06f4a01fce07
+ fe780629116b4efc.512881bf2c0caf8f.0ba819a5722dff34.0334569e62ec5717
+ d9b30d056120d3d0
+ after
+ f09ef193789d1c2d.54c07f567fbb8f22.54c07f567fbb8f22.f09ef193789d1c2d
+ b9d693afc5e51ead.e9e382ef21302da6.8406dec165d974c9.532ba119ffaf7b77
+ f09ef193789d1c2d.a58d0dd46f0d4470.54c07f567fbb8f22.cb4b06f4a01fce07
+ fe780629116b4efc.512881bf2c0caf8f.0ba819a5722dff34.0334569e62ec5717
+ d9b30d056120d3d0
+VPERMPD_0xD7(mem)
+ before
+ 2894a514bac9fe61.3eb2cedc2ddaf0c7.c87f599d753a2b2f.0609a81cd9b901ab
+ cba39cb788f394f4.0c96461868763d39.e55d115865a1747b.a12e282651edd134
+ a0ac6cdae8a950b6.c37168495ccc72ff.868f25de184f45a0.3864962f7555ab7b
+ 817a9369f6f7efd2.c18f32dba866cbc4.85e1111aac505bca.28f7eca3e27cca2b
+ cb3328ee33ee6bf1
+ after
+ 2894a514bac9fe61.3eb2cedc2ddaf0c7.c87f599d753a2b2f.0609a81cd9b901ab
+ cba39cb788f394f4.0c96461868763d39.e55d115865a1747b.a12e282651edd134
+ c87f599d753a2b2f.3eb2cedc2ddaf0c7.2894a514bac9fe61.0609a81cd9b901ab
+ 817a9369f6f7efd2.c18f32dba866cbc4.85e1111aac505bca.28f7eca3e27cca2b
+ cb3328ee33ee6bf1
+
+VPERMPD_0xD7(reg)
+ before
+ 7e63467c0437ca78.4cda8d51cde92d75.613c9f3ae6d38335.c01f52f73aaf7224
+ 9dd540baf2e4236d.db99d47c898cc5ca.fec3abd2b29cd7fe.11156363e07846db
+ 84d314129980b17c.0c81e6d847eb74fe.f6725310a94f03ca.568fc049bab7921a
+ 8faabdf19497b150.b95e3e4f2212f63d.a393925e66774346.6958e595e379130e
+ 273d4f3377c985e2
+ after
+ 84d314129980b17c.f6725310a94f03ca.f6725310a94f03ca.84d314129980b17c
+ 9dd540baf2e4236d.db99d47c898cc5ca.fec3abd2b29cd7fe.11156363e07846db
+ 84d314129980b17c.0c81e6d847eb74fe.f6725310a94f03ca.568fc049bab7921a
+ 8faabdf19497b150.b95e3e4f2212f63d.a393925e66774346.6958e595e379130e
+ 273d4f3377c985e2
+VPERMPD_0xD7(mem)
+ before
+ 6d0a790f93b4a3c3.1aa737c47fb65e96.bffe58cf360e07b2.6373642a86a1d21e
+ 158bdf1653442add.81137ef6f768f6f9.fb2cb043a1ea628a.905ec5dea458edfd
+ fc8cfd32d188d65b.203d8ef2973ab326.47b3c3967cb3c4f1.87a0b1e85c28d090
+ fed94f512c89636a.53706426fcb6d2c9.80600cb6e574e912.a58525b34c9eb682
+ 44581cab0d45dc80
+ after
+ 6d0a790f93b4a3c3.1aa737c47fb65e96.bffe58cf360e07b2.6373642a86a1d21e
+ 158bdf1653442add.81137ef6f768f6f9.fb2cb043a1ea628a.905ec5dea458edfd
+ bffe58cf360e07b2.1aa737c47fb65e96.6d0a790f93b4a3c3.6373642a86a1d21e
+ fed94f512c89636a.53706426fcb6d2c9.80600cb6e574e912.a58525b34c9eb682
+ 44581cab0d45dc80
+
+VPERMPD_0xB5(reg)
+ before
+ c266923c3da97e35.f83d525d7e558c35.75f7fbfdc26b8e8d.82ff078ef8398c19
+ 79fc83d27857d84e.c4868144e3f70ee9.e41f4fe383e2241e.2a5c300bd00e6a34
+ c664ecd959da2577.3f7e58f1787ca5b2.fb345d44dea9d02a.5243041789003f8c
+ 05eac7bd7cbea25b.45f2535058ef0cbb.16821f8d6c4bce5b.d780fd9f401bc750
+ 95de99901169bdaa
+ after
+ 3f7e58f1787ca5b2.c664ecd959da2577.fb345d44dea9d02a.fb345d44dea9d02a
+ 79fc83d27857d84e.c4868144e3f70ee9.e41f4fe383e2241e.2a5c300bd00e6a34
+ c664ecd959da2577.3f7e58f1787ca5b2.fb345d44dea9d02a.5243041789003f8c
+ 05eac7bd7cbea25b.45f2535058ef0cbb.16821f8d6c4bce5b.d780fd9f401bc750
+ 95de99901169bdaa
+VPERMPD_0xB5(mem)
+ before
+ 682a53d417f8dec6.93dc12ea7e908ba7.b2aeef4d9f5c0131.90559328cc55595d
+ 2c31a8596ed3e6d2.ca85c8cdfadb1b06.627ea6d46bcf3e3f.c7f9b4829752aedd
+ bdbd1209330791f7.0730e6d18d2b9025.312df6d1d5557f12.16b97f086bce0987
+ f79a0fd2819f9a64.a62a6661d30d24b0.fb895a30fbfa82d6.d8e3ee24e455a606
+ 6bc1ff449d74c007
+ after
+ 682a53d417f8dec6.93dc12ea7e908ba7.b2aeef4d9f5c0131.90559328cc55595d
+ 2c31a8596ed3e6d2.ca85c8cdfadb1b06.627ea6d46bcf3e3f.c7f9b4829752aedd
+ b2aeef4d9f5c0131.90559328cc55595d.93dc12ea7e908ba7.93dc12ea7e908ba7
+ f79a0fd2819f9a64.a62a6661d30d24b0.fb895a30fbfa82d6.d8e3ee24e455a606
+ 6bc1ff449d74c007
+
+VPERMPD_0xB5(reg)
+ before
+ 2aa0add332b69436.b6961a9f75a7be43.03bf46eb660c1352.9c5c4fddf9c801b6
+ 70ccf43d40a85e3e.d67caf5c2a2cb8c0.7a3b81dae5b59bb8.f0734fc5eacdb8df
+ 9b90d0ee63d559cc.33174bf5bd394609.67ea149ae992f68d.d39ad8d2ea14657c
+ 053a3e5236c9c28b.a934685649da2247.2618f9971131607e.219d65f216aac2ba
+ b64773108a9a8cc5
+ after
+ 33174bf5bd394609.9b90d0ee63d559cc.67ea149ae992f68d.67ea149ae992f68d
+ 70ccf43d40a85e3e.d67caf5c2a2cb8c0.7a3b81dae5b59bb8.f0734fc5eacdb8df
+ 9b90d0ee63d559cc.33174bf5bd394609.67ea149ae992f68d.d39ad8d2ea14657c
+ 053a3e5236c9c28b.a934685649da2247.2618f9971131607e.219d65f216aac2ba
+ b64773108a9a8cc5
+VPERMPD_0xB5(mem)
+ before
+ 6d667c1861f07fc8.0b1439d55511d528.139f846ceb1c09a9.13102e3df61e1737
+ 24c4fef6b7b956f0.0a6cbde35d38ce4e.4f241a21be0ab659.8a20aef836e45563
+ b62e7496a900ce68.5c8cc6e9eacae8aa.388fa662dfb0e683.e79275346d0f57af
+ ff705ae452d2a35d.5fc15051965460e8.aaaba51c691b5554.86b37f5e362b59c6
+ c2cfc9e02ec59655
+ after
+ 6d667c1861f07fc8.0b1439d55511d528.139f846ceb1c09a9.13102e3df61e1737
+ 24c4fef6b7b956f0.0a6cbde35d38ce4e.4f241a21be0ab659.8a20aef836e45563
+ 139f846ceb1c09a9.13102e3df61e1737.0b1439d55511d528.0b1439d55511d528
+ ff705ae452d2a35d.5fc15051965460e8.aaaba51c691b5554.86b37f5e362b59c6
+ c2cfc9e02ec59655
+
+VPERMPD_0xB5(reg)
+ before
+ f9314d28f0684b08.da562ccccf3991fb.6d565889006172b3.8046923a7856bff8
+ 862709a118a1b48a.25ac673a3b43536d.e399d9fbc17d59b8.982ae9a7296ddf9a
+ c5fbf9b643fb0d88.bb3d861ab3fca6df.1dd4cf15783553a2.cd242651986d7367
+ 11fa17d50d0291ad.77d70559526e467f.78553642be14991f.fa00c523e061348b
+ fd8a43091d55e131
+ after
+ bb3d861ab3fca6df.c5fbf9b643fb0d88.1dd4cf15783553a2.1dd4cf15783553a2
+ 862709a118a1b48a.25ac673a3b43536d.e399d9fbc17d59b8.982ae9a7296ddf9a
+ c5fbf9b643fb0d88.bb3d861ab3fca6df.1dd4cf15783553a2.cd242651986d7367
+ 11fa17d50d0291ad.77d70559526e467f.78553642be14991f.fa00c523e061348b
+ fd8a43091d55e131
+VPERMPD_0xB5(mem)
+ before
+ b08e1bef6c563485.c870616910427da6.374460e135a7ee77.4e660bee31a66ad8
+ f1d7c9c2e86feab5.45a9d2deeb480d1e.d55113a077b35bf3.fc5449856d78007b
+ 9a32c96caeadbfeb.e3f166a038a07cc2.2fca9b81349d4920.de6bec730d1599b4
+ 896c98dad91a6e53.0094191c93d4073e.1f7b73708971742a.50f6f024ae096e2f
+ ae435104ebe1be97
+ after
+ b08e1bef6c563485.c870616910427da6.374460e135a7ee77.4e660bee31a66ad8
+ f1d7c9c2e86feab5.45a9d2deeb480d1e.d55113a077b35bf3.fc5449856d78007b
+ 374460e135a7ee77.4e660bee31a66ad8.c870616910427da6.c870616910427da6
+ 896c98dad91a6e53.0094191c93d4073e.1f7b73708971742a.50f6f024ae096e2f
+ ae435104ebe1be97
+
+VPERMPD_0x85(reg)
+ before
+ 549c0c806028c398.984fb0f986c5b51a.f6dde8bc9972ea3d.832f1759923b973c
+ 9e4e1c02aa6bbadf.a5a78fb3d0b74d6c.2319cdede505606c.35b403286a086f83
+ e8a57df86534df18.8a42b0f6d4fef574.e194c61c141aa777.12d4b4c92de3b82a
+ 8eed2bcc2c126dee.24eb90adada5675f.8e9acfb3c13cf909.f75ca528f8d92d5e
+ be185231e7f58b4b
+ after
+ 8a42b0f6d4fef574.12d4b4c92de3b82a.e194c61c141aa777.e194c61c141aa777
+ 9e4e1c02aa6bbadf.a5a78fb3d0b74d6c.2319cdede505606c.35b403286a086f83
+ e8a57df86534df18.8a42b0f6d4fef574.e194c61c141aa777.12d4b4c92de3b82a
+ 8eed2bcc2c126dee.24eb90adada5675f.8e9acfb3c13cf909.f75ca528f8d92d5e
+ be185231e7f58b4b
+VPERMPD_0x85(mem)
+ before
+ 44d437d115438e1c.ec7223ec9b8ea10e.4f6da9c478b96058.8477e22088f793cf
+ 655bd0f29ecff2fe.5e7f5fc34f36b724.e895792750449c8c.2177fdce06d8b074
+ fe7b9a829fa6721d.4062ddbde395eadb.c92f7bc25255d727.bfe51a29d76a8da5
+ e9fe106c33d3cba4.ee659846f43778e0.cf072b8199f5cc54.bb0f379d9639660d
+ 723f5096e0d27759
+ after
+ 44d437d115438e1c.ec7223ec9b8ea10e.4f6da9c478b96058.8477e22088f793cf
+ 655bd0f29ecff2fe.5e7f5fc34f36b724.e895792750449c8c.2177fdce06d8b074
+ 44d437d115438e1c.4f6da9c478b96058.44d437d115438e1c.8477e22088f793cf
+ e9fe106c33d3cba4.ee659846f43778e0.cf072b8199f5cc54.bb0f379d9639660d
+ 723f5096e0d27759
+
+VPERMPD_0x85(reg)
+ before
+ 3ec25f8050c0fb35.03b1ae9b7763b9bf.c3d58dca1da99bde.d6e9065041323840
+ 7ce462c7828f2f4c.2860f0fd8661f79b.1dfeb6b5fb778f82.baa1871b6717d617
+ 88f054d813cc4f4b.34d7537d7dd94364.572c1174292b9278.58fa29cf27b16404
+ be34311d9e0296dd.03e2510777d85746.ccab99714453de6b.8ac16b569b0b9c33
+ 2dc3c69ee2313bd1
+ after
+ 34d7537d7dd94364.58fa29cf27b16404.572c1174292b9278.572c1174292b9278
+ 7ce462c7828f2f4c.2860f0fd8661f79b.1dfeb6b5fb778f82.baa1871b6717d617
+ 88f054d813cc4f4b.34d7537d7dd94364.572c1174292b9278.58fa29cf27b16404
+ be34311d9e0296dd.03e2510777d85746.ccab99714453de6b.8ac16b569b0b9c33
+ 2dc3c69ee2313bd1
+VPERMPD_0x85(mem)
+ before
+ 1dcab7921630fc0a.7bfaf504c0bd41af.714d68879068ef6c.dac64b1ae77ab008
+ 36a2bb1d53139c0a.19909df7158a8c6d.5ae313eae598c902.dcca21d9ae2d43fa
+ 54194d2db6e6d7fb.f540246437f4b3c2.9a71cf1a92719f35.2d04191c36f7d4ee
+ 52fae9ad5ab5690c.6b5786b6c587f15b.0dc31604b2012d31.2bbe2e4e1b649f8f
+ 30445cdbf800e08a
+ after
+ 1dcab7921630fc0a.7bfaf504c0bd41af.714d68879068ef6c.dac64b1ae77ab008
+ 36a2bb1d53139c0a.19909df7158a8c6d.5ae313eae598c902.dcca21d9ae2d43fa
+ 1dcab7921630fc0a.714d68879068ef6c.1dcab7921630fc0a.dac64b1ae77ab008
+ 52fae9ad5ab5690c.6b5786b6c587f15b.0dc31604b2012d31.2bbe2e4e1b649f8f
+ 30445cdbf800e08a
+
+VPERMPD_0x85(reg)
+ before
+ 9ae49f2f6958d38b.0e100c895c8d0d67.d720bf5958d083e3.8fa5669562543122
+ c3e9f4b60bf8b33d.632831add77a8039.95e9ccb98f5aa507.fce33ab8bc746533
+ 099e56dc7a6abd4d.2d0ed306e8867ead.01fda74203b29373.30490e58df6f8690
+ c650c10d513c2c67.488e717eaabfc3f0.77a74e60526388d2.07a25f63e5515066
+ 5cbca8c4ea247ee1
+ after
+ 2d0ed306e8867ead.30490e58df6f8690.01fda74203b29373.01fda74203b29373
+ c3e9f4b60bf8b33d.632831add77a8039.95e9ccb98f5aa507.fce33ab8bc746533
+ 099e56dc7a6abd4d.2d0ed306e8867ead.01fda74203b29373.30490e58df6f8690
+ c650c10d513c2c67.488e717eaabfc3f0.77a74e60526388d2.07a25f63e5515066
+ 5cbca8c4ea247ee1
+VPERMPD_0x85(mem)
+ before
+ 0d6165670bf6cd2c.584b31b52cfa3d36.9074840339310a2e.5334bc8018f9c1d1
+ f55e123863d3f974.19dba241a82e2c66.e08b897fb2e61092.f0f0ee0cf000791b
+ ef7f2b230fc5bee5.664c111b606635a5.16a1fde031ec9149.ac27de727705ee5d
+ d98f2d152adad7aa.9bea79b1f12e949d.0d805b11d14f487e.e2248a1c48935a43
+ ee35ed78ff37fa78
+ after
+ 0d6165670bf6cd2c.584b31b52cfa3d36.9074840339310a2e.5334bc8018f9c1d1
+ f55e123863d3f974.19dba241a82e2c66.e08b897fb2e61092.f0f0ee0cf000791b
+ 0d6165670bf6cd2c.9074840339310a2e.0d6165670bf6cd2c.5334bc8018f9c1d1
+ d98f2d152adad7aa.9bea79b1f12e949d.0d805b11d14f487e.e2248a1c48935a43
+ ee35ed78ff37fa78
+
+VPERMPD_0x29(reg)
+ before
+ 2ca403f1397c09a9.8e5c92f8d11e01f0.1500d66ef61084fa.a0f51ffdae1af25e
+ f7bfc9f291eec581.e9b0d8ba1f9cf8e2.2edb24be0c9a4269.adccc692e5594b14
+ add039e9a41968ad.c8587b45316077ad.43c8600dce580996.0ed1cabb92180fce
+ a92451420e8a2ed8.0520f58722763b7c.b01085c7d8d4172c.a1d0a964d064f9b5
+ 4094de7abb48c6f7
+ after
+ 0ed1cabb92180fce.c8587b45316077ad.c8587b45316077ad.43c8600dce580996
+ f7bfc9f291eec581.e9b0d8ba1f9cf8e2.2edb24be0c9a4269.adccc692e5594b14
+ add039e9a41968ad.c8587b45316077ad.43c8600dce580996.0ed1cabb92180fce
+ a92451420e8a2ed8.0520f58722763b7c.b01085c7d8d4172c.a1d0a964d064f9b5
+ 4094de7abb48c6f7
+VPERMPD_0x29(mem)
+ before
+ c9eae5e770d032c0.46060c676acc55af.7ed4c46a0feb007c.d1028f58c89ca6d8
+ 169f3b980a09f83c.e2c467c5546c17de.0d4063dc13ca82d9.02e97a2c373cf345
+ 057d5b7aa6fed596.d7a85cc869f5b110.90304ec84a1f7cbe.9f1042afc33f3920
+ 7050c1775fbc85fb.8300e9dd44f35ef2.e16f011ad1f7ab58.05c5e44e0831b515
+ 8e525b73a19ea3cf
+ after
+ c9eae5e770d032c0.46060c676acc55af.7ed4c46a0feb007c.d1028f58c89ca6d8
+ 169f3b980a09f83c.e2c467c5546c17de.0d4063dc13ca82d9.02e97a2c373cf345
+ 46060c676acc55af.7ed4c46a0feb007c.d1028f58c89ca6d8.46060c676acc55af
+ 7050c1775fbc85fb.8300e9dd44f35ef2.e16f011ad1f7ab58.05c5e44e0831b515
+ 8e525b73a19ea3cf
+
+VPERMPD_0x29(reg)
+ before
+ 9604a38c2a133ffb.34e6e97d524ec496.4016096e82f35c30.ddcaf9bec45dcbd3
+ 7b27b803401bc444.2e0a4f779ac04d94.6c37b8e9be80e575.610db0a13d5e975a
+ 980797467e426f57.38877051541edd20.61aef3b99426356d.4704a4ad5b05cc19
+ 49ef3ac081157cdf.2f2ac7f79b753067.7cc9b449a1728ac6.6c7b51cf385e263e
+ ad3e31f4f07561f2
+ after
+ 4704a4ad5b05cc19.38877051541edd20.38877051541edd20.61aef3b99426356d
+ 7b27b803401bc444.2e0a4f779ac04d94.6c37b8e9be80e575.610db0a13d5e975a
+ 980797467e426f57.38877051541edd20.61aef3b99426356d.4704a4ad5b05cc19
+ 49ef3ac081157cdf.2f2ac7f79b753067.7cc9b449a1728ac6.6c7b51cf385e263e
+ ad3e31f4f07561f2
+VPERMPD_0x29(mem)
+ before
+ e418c206a0573864.ea2d9fdde41f278a.f0bfd0558bd00195.1ad3f90781ef1e2a
+ eed77ef3630f68be.d70bc20944edab01.55120757413c0dd5.9517bd5ecf292e45
+ a745e4a656aaad2c.6cd69db03c0a45f3.3befe8e9d9c41054.4ae2fcba28adf5c4
+ eb2f6d0b9433c2dc.04da2e3e6902300a.7e22f0f76e74c63d.9680b3882706b153
+ d33ddd3268c09c9d
+ after
+ e418c206a0573864.ea2d9fdde41f278a.f0bfd0558bd00195.1ad3f90781ef1e2a
+ eed77ef3630f68be.d70bc20944edab01.55120757413c0dd5.9517bd5ecf292e45
+ ea2d9fdde41f278a.f0bfd0558bd00195.1ad3f90781ef1e2a.ea2d9fdde41f278a
+ eb2f6d0b9433c2dc.04da2e3e6902300a.7e22f0f76e74c63d.9680b3882706b153
+ d33ddd3268c09c9d
+
+VPERMPD_0x29(reg)
+ before
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+ 13485767676cfd95.422c0f5504d25ef6.737874211cb7aaf5.97aa187fa75c6594
+ 26b1389e5067719c.25e928f39fdddfc9.8cedc34cf26cbdd0.53636547cbfcd41b
+ f4b6475603d77626
+ after
+ c9cb2ba1120313bd.82ffe921c6ce9bf2.12f2f3508107a770.59d04d152c9f2a69
+ 3e947c0c5cfa1d5a.d5a24e88f0fbb192.e913ae1b55448d8e.623d6493fb6cebe8
+ c9cb2ba1120313bd.82ffe921c6ce9bf2.12f2f3508107a770.59d04d152c9f2a69
+ 26b1389e5067719c.25e928f39fdddfc9.8cedc34cf26cbdd0.53636547cbfcd41b
+ f4b6475603d77626
+
+VPBLENDD_256_0x30(reg)
+ before
+ d4eebb18ec798564.529c9c9d32f73398.da2593ce5caa70b8.0f3e168af470804c
+ 5056bcf9226f3e7e.73d5fe512a2600b8.bd2b4e52d8c54c6e.da36e9c63eceb095
+ c53b46663f44dc23.6528daa453029326.2a4854ebaeb9b199.c8a3b9ebea9209d6
+ 8de955c9e2849dfd.0461ac83ca97a90e.7dc8a1067a12d8e2.b54f00e717c9463c
+ 7c073ca5df7e24f2
+ after
+ 5056bcf9226f3e7e.6528daa453029326.bd2b4e52d8c54c6e.da36e9c63eceb095
+ 5056bcf9226f3e7e.73d5fe512a2600b8.bd2b4e52d8c54c6e.da36e9c63eceb095
+ c53b46663f44dc23.6528daa453029326.2a4854ebaeb9b199.c8a3b9ebea9209d6
+ 8de955c9e2849dfd.0461ac83ca97a90e.7dc8a1067a12d8e2.b54f00e717c9463c
+ 7c073ca5df7e24f2
+VPBLENDD_256_0x30(mem)
+ before
+ fb97e9115ebd5f25.06ace58fa5bcbbb9.2b4cf1dbaaeffe9d.12f7310dd95c00f8
+ 0dcb8118b193b301.8ad0f32524777202.b8b423970f184eff.4521016e67246485
+ 8e6f81a4f30bdbb1.76a17af6fc410085.8666c0a2161e545f.71920c93bff53f35
+ 594e66a241319461.266a766dc8a79fed.702e44eadb0bceea.f4954eea7d5ccdb5
+ 2978c3de3ee44cb1
+ after
+ fb97e9115ebd5f25.06ace58fa5bcbbb9.2b4cf1dbaaeffe9d.12f7310dd95c00f8
+ 0dcb8118b193b301.8ad0f32524777202.b8b423970f184eff.4521016e67246485
+ 0dcb8118b193b301.8ad0f32524777202.b8b423970f184eff.12f7310dd95c00f8
+ 594e66a241319461.266a766dc8a79fed.702e44eadb0bceea.f4954eea7d5ccdb5
+ 2978c3de3ee44cb1
+
+VPBLENDD_256_0x30(reg)
+ before
+ 6b8567db9e19f6d4.4c36abffb6129a3f.f778e3f825348ce7.54d8295a79ed75cc
+ 1809374c388708cb.41f1cca56eb9a875.4317be02ae74031f.0c30edde0cd00830
+ 8b502ea0a8bbbe42.164c468287327b2f.679302f7fff43f40.76020a62b1bf4143
+ 1fa648408b4153e4.a51394811a8acf9a.bf38ab43b53f7df7.6c19fed283c6dd30
+ cc43451b9ff19824
+ after
+ 1809374c388708cb.164c468287327b2f.4317be02ae74031f.0c30edde0cd00830
+ 1809374c388708cb.41f1cca56eb9a875.4317be02ae74031f.0c30edde0cd00830
+ 8b502ea0a8bbbe42.164c468287327b2f.679302f7fff43f40.76020a62b1bf4143
+ 1fa648408b4153e4.a51394811a8acf9a.bf38ab43b53f7df7.6c19fed283c6dd30
+ cc43451b9ff19824
+VPBLENDD_256_0x30(mem)
+ before
+ 704a5927204d2d4a.325681997ca3045e.cc12318e45cc60e2.a752b5526ce1f9ef
+ 36fbb8e423e55acf.1eaed617186f0d5b.65149c952405e932.7b2c1c91bf67eed5
+ f822dd3cc3c6d8df.41f84227fa30aa88.4ee74e82d24027b7.9714dd6a4a5c9955
+ 938a441d1dfa66a5.f581c133bf731690.6155c4416b89d69d.5754f34baa4d361a
+ 17395a9e7bc401d1
+ after
+ 704a5927204d2d4a.325681997ca3045e.cc12318e45cc60e2.a752b5526ce1f9ef
+ 36fbb8e423e55acf.1eaed617186f0d5b.65149c952405e932.7b2c1c91bf67eed5
+ 36fbb8e423e55acf.1eaed617186f0d5b.65149c952405e932.a752b5526ce1f9ef
+ 938a441d1dfa66a5.f581c133bf731690.6155c4416b89d69d.5754f34baa4d361a
+ 17395a9e7bc401d1
+
+VPBLENDD_256_0x30(reg)
+ before
+ 330f0ed158503525.e40169724c90be4e.98954fa902c38e20.7b2b7bbe0cecb10f
+ 07220c4fdd7a0fc3.c551c9266d919d06.8480e8f460ac4ee4.7935eee5d1767539
+ efbd4f83a7d0cb57.1348df279b0bbff8.178e897f74bb9187.353f99a3d432de48
+ 472ed2db51dda58c.abb02760f209e050.ab0a2db8da7b95b6.8c15f9e2342da868
+ 5a8288900b728ec5
+ after
+ 07220c4fdd7a0fc3.1348df279b0bbff8.8480e8f460ac4ee4.7935eee5d1767539
+ 07220c4fdd7a0fc3.c551c9266d919d06.8480e8f460ac4ee4.7935eee5d1767539
+ efbd4f83a7d0cb57.1348df279b0bbff8.178e897f74bb9187.353f99a3d432de48
+ 472ed2db51dda58c.abb02760f209e050.ab0a2db8da7b95b6.8c15f9e2342da868
+ 5a8288900b728ec5
+VPBLENDD_256_0x30(mem)
+ before
+ 7b53c497750d4d8a.6bbf94c2782dd80f.67561dbe8f98bb3b.9d41d00a2f78931d
+ cc5528e58f0aa1e3.b6bd8ea5b74da18b.24053e2b8ec30de5.4a806ee10f3fca67
+ 27523165747645fe.8674beeeabc83cad.be8b04940a96917a.0c1103aa155b7440
+ 69175903405cf704.36301e0aef2be420.11b2ede61f1d0525.40408ccfdd58ce56
+ 425b04bd04c31452
+ after
+ 7b53c497750d4d8a.6bbf94c2782dd80f.67561dbe8f98bb3b.9d41d00a2f78931d
+ cc5528e58f0aa1e3.b6bd8ea5b74da18b.24053e2b8ec30de5.4a806ee10f3fca67
+ cc5528e58f0aa1e3.b6bd8ea5b74da18b.24053e2b8ec30de5.9d41d00a2f78931d
+ 69175903405cf704.36301e0aef2be420.11b2ede61f1d0525.40408ccfdd58ce56
+ 425b04bd04c31452
+
+VPBLENDD_256_0x21(reg)
+ before
+ 6fad67e1262782e3.6e6f1eab11c97024.213cad662001d691.f948740bea652312
+ 2181b2a5de1053b3.1228fb4900c86f88.a5e6646cd9d64eac.521716f18779a76e
+ b524df77c80bc46f.310c6cca2b65ae5c.1d78408ab737881c.f8ec4d8211664f65
+ 87e2ecc281a310c2.a7e9ed18aeadebce.e43f3e2a55afbf8e.c79397aca437d523
+ 9bd76f5a5df8f6d3
+ after
+ 2181b2a5de1053b3.310c6cca00c86f88.a5e6646cd9d64eac.521716f111664f65
+ 2181b2a5de1053b3.1228fb4900c86f88.a5e6646cd9d64eac.521716f18779a76e
+ b524df77c80bc46f.310c6cca2b65ae5c.1d78408ab737881c.f8ec4d8211664f65
+ 87e2ecc281a310c2.a7e9ed18aeadebce.e43f3e2a55afbf8e.c79397aca437d523
+ 9bd76f5a5df8f6d3
+VPBLENDD_256_0x21(mem)
+ before
+ 5086517857b66ea1.f307d4f1a4647559.5089fb20a4abdf07.588759ba4fca30ae
+ c26abaf2af7cf8ba.55df9372cedb2ddf.08b911cf296b4936.d39c8da542141727
+ cd5024b48056514a.09b626b09a937501.aa44ab105afae385.b3cad657ca1aafa6
+ 4d040dabe651357c.6bd78818a519886a.14f845ce53636a20.525c313c826835d6
+ 0ea099c00688e564
+ after
+ 5086517857b66ea1.f307d4f1a4647559.5089fb20a4abdf07.588759ba4fca30ae
+ c26abaf2af7cf8ba.55df9372cedb2ddf.08b911cf296b4936.d39c8da542141727
+ c26abaf2af7cf8ba.55df9372a4647559.08b911cf296b4936.588759ba42141727
+ 4d040dabe651357c.6bd78818a519886a.14f845ce53636a20.525c313c826835d6
+ 0ea099c00688e564
+
+VPBLENDD_256_0x21(reg)
+ before
+ 41e00a4ff308fbfb.1d52f0c1ff78607d.d790b4148af8a3c8.219f5cf72fb29a34
+ 49698056e474b248.1b064ae3e4d78d79.a92ba911e5bc02c4.ad076a760af42eed
+ 8087f83f765647f7.22ec95feb37b799b.3cf5607b53f1e10d.94faed370134e376
+ 43866c78443cf6b3.0dcf4ffd886fdf10.ee3ad6bf70247b4d.b14560262f7e75fc
+ e2b4402fb1dfa0ab
+ after
+ 49698056e474b248.22ec95fee4d78d79.a92ba911e5bc02c4.ad076a760134e376
+ 49698056e474b248.1b064ae3e4d78d79.a92ba911e5bc02c4.ad076a760af42eed
+ 8087f83f765647f7.22ec95feb37b799b.3cf5607b53f1e10d.94faed370134e376
+ 43866c78443cf6b3.0dcf4ffd886fdf10.ee3ad6bf70247b4d.b14560262f7e75fc
+ e2b4402fb1dfa0ab
+VPBLENDD_256_0x21(mem)
+ before
+ 0212073fa2621fae.eeb1da6bebb2fa29.ba7cf3cb7ebf7d03.1a450848d7e00d30
+ ec2d33401f13af32.de563d8606429005.04bffd56b1780da1.1c64f18124b2d363
+ 7ecf3f1f43ff0c62.6dbf9234327af4f2.c664e9893ea54c16.50e18dd8f4250992
+ 92c6a7c92b31f16b.f839d3e10ae6629c.de3734504153f58d.1109d9b8e3c5ea68
+ bd28d08d8c1eb392
+ after
+ 0212073fa2621fae.eeb1da6bebb2fa29.ba7cf3cb7ebf7d03.1a450848d7e00d30
+ ec2d33401f13af32.de563d8606429005.04bffd56b1780da1.1c64f18124b2d363
+ ec2d33401f13af32.de563d86ebb2fa29.04bffd56b1780da1.1a45084824b2d363
+ 92c6a7c92b31f16b.f839d3e10ae6629c.de3734504153f58d.1109d9b8e3c5ea68
+ bd28d08d8c1eb392
+
+VPBLENDD_256_0x21(reg)
+ before
+ af8a6dc38bbda0bc.06dce829f2b61b78.db10fef92b1015b0.26045997d58cc632
+ 427bafc67d2dec91.b4de7c2ab49846b6.72900ee830864ada.7c96d44a165e7933
+ d4478f02fdfbd4be.7a97e1ba8ee52e51.1905ff1ab5d43dc6.babb215621d5cab9
+ bf390ae4a8b294ee.32d592c49ca98e74.2dbacdfc5785291f.be3dbda511fc77f3
+ 62e9222503df3a0b
+ after
+ 427bafc67d2dec91.7a97e1bab49846b6.72900ee830864ada.7c96d44a21d5cab9
+ 427bafc67d2dec91.b4de7c2ab49846b6.72900ee830864ada.7c96d44a165e7933
+ d4478f02fdfbd4be.7a97e1ba8ee52e51.1905ff1ab5d43dc6.babb215621d5cab9
+ bf390ae4a8b294ee.32d592c49ca98e74.2dbacdfc5785291f.be3dbda511fc77f3
+ 62e9222503df3a0b
+VPBLENDD_256_0x21(mem)
+ before
+ 848bcec0128ad02e.619e1dd619de68ce.ba620c34f9ef234c.08fd75f8b2254c91
+ feee3c645b0af487.14c2c346ed0c8b09.ec0cc9f6c1c3a905.0718f27b6140e0c9
+ ade0e9fcf96a6443.36f1f89ebfc73a4c.a59d47f71131dbca.865840f200632173
+ 6e2b4f7408b7da8d.2177b94c2c9bb143.c2e20121054676c7.e0095bc82c194d3b
+ 7376406881ee9ecc
+ after
+ 848bcec0128ad02e.619e1dd619de68ce.ba620c34f9ef234c.08fd75f8b2254c91
+ feee3c645b0af487.14c2c346ed0c8b09.ec0cc9f6c1c3a905.0718f27b6140e0c9
+ feee3c645b0af487.14c2c34619de68ce.ec0cc9f6c1c3a905.08fd75f86140e0c9
+ 6e2b4f7408b7da8d.2177b94c2c9bb143.c2e20121054676c7.e0095bc82c194d3b
+ 7376406881ee9ecc
+
+VPBLENDD_256_0xD7(reg)
+ before
+ 9aedea40996f50d2.1b9decb7a6fc1392.33a000bbcf152b99.1da77361b80d362a
+ b1b855bb1327a1fa.91003bb4ec45ca7e.c6b7cb5744c0e5fb.93b71aa44693d71d
+ 14257d4589a3cbf0.ac21b854f89ebc7c.370a158c28281b15.00e070d4cce314cc
+ 1f7e5e4a976e0b5f.48cbe084e614a5b9.e2e3dbc617da0992.40ecf3df6509aa64
+ 30a81eb02e115511
+ after
+ 14257d4589a3cbf0.91003bb4f89ebc7c.c6b7cb5728281b15.00e070d4cce314cc
+ b1b855bb1327a1fa.91003bb4ec45ca7e.c6b7cb5744c0e5fb.93b71aa44693d71d
+ 14257d4589a3cbf0.ac21b854f89ebc7c.370a158c28281b15.00e070d4cce314cc
+ 1f7e5e4a976e0b5f.48cbe084e614a5b9.e2e3dbc617da0992.40ecf3df6509aa64
+ 30a81eb02e115511
+VPBLENDD_256_0xD7(mem)
+ before
+ aae06e334208d0fe.2d10f537d9149df4.42cc2e30d1b24160.248f1771ac61ea1e
+ 8b605d54befad958.9c263d76ed21bc5b.74ee1e45d5854b9e.575ac7f98349fb67
+ aff469ffbdf1294a.c70e32746c22a53f.bbff2cad0f98809f.d88fe6cb391f7816
+ f2670d205bfb7f01.0913d09ef4a3944d.f3c9d4569af79c8e.037c70516a6e9cda
+ 346b61f9b0c2a55d
+ after
+ aae06e334208d0fe.2d10f537d9149df4.42cc2e30d1b24160.248f1771ac61ea1e
+ 8b605d54befad958.9c263d76ed21bc5b.74ee1e45d5854b9e.575ac7f98349fb67
+ 8b605d544208d0fe.2d10f537ed21bc5b.42cc2e30d1b24160.575ac7f98349fb67
+ f2670d205bfb7f01.0913d09ef4a3944d.f3c9d4569af79c8e.037c70516a6e9cda
+ 346b61f9b0c2a55d
+
+VPBLENDD_256_0xD7(reg)
+ before
+ c8aab62daaa8cc4b.3087c5a3b52395a9.c080135e212ec530.f819932b93af5a98
+ 19836a5bf2ab5052.451e0d74e776296d.47a2f8228e517395.a6bbe31716cb78e8
+ 844379ee24576b1b.0df962800cfff47a.f9c57a55d897db27.d97a42083d57b0ab
+ 6535df52dd395b55.64e43fb140cab5fb.343595639a8d3993.6d242ce92760be0d
+ 3d831ba6edf16039
+ after
+ 844379ee24576b1b.451e0d740cfff47a.47a2f822d897db27.d97a42083d57b0ab
+ 19836a5bf2ab5052.451e0d74e776296d.47a2f8228e517395.a6bbe31716cb78e8
+ 844379ee24576b1b.0df962800cfff47a.f9c57a55d897db27.d97a42083d57b0ab
+ 6535df52dd395b55.64e43fb140cab5fb.343595639a8d3993.6d242ce92760be0d
+ 3d831ba6edf16039
+VPBLENDD_256_0xD7(mem)
+ before
+ 27648d2bad16505c.18a798f3b8dc59aa.25ab20f5a0e4261d.523e46b870bec885
+ 0693fc6583dc4ba1.f9e4a13d51cda4c6.2e1981374858040b.b12b87c0f7b6c5a8
+ b6dce73e8a4e0c35.6437f59c46967657.5afcde6353320bf3.ab4a56e7ca026ca9
+ 130bc7a4df785044.b4ed907c30c60c06.851eb465dd7ff6fe.9de5ae99862df934
+ e4498b43c7c3a7f4
+ after
+ 27648d2bad16505c.18a798f3b8dc59aa.25ab20f5a0e4261d.523e46b870bec885
+ 0693fc6583dc4ba1.f9e4a13d51cda4c6.2e1981374858040b.b12b87c0f7b6c5a8
+ 0693fc65ad16505c.18a798f351cda4c6.25ab20f5a0e4261d.b12b87c0f7b6c5a8
+ 130bc7a4df785044.b4ed907c30c60c06.851eb465dd7ff6fe.9de5ae99862df934
+ e4498b43c7c3a7f4
+
+VPBLENDD_256_0xD7(reg)
+ before
+ dac2ea4f2751b395.f8ec19819d67d3f9.47526f4aade6a282.8b4c7e29034a825b
+ dd9cc52b456259c5.434a5ac3e0265180.78b28c7059847375.4752b89be09f6b34
+ 47221a41ba82d42e.cff20554c5c18507.a358e55ccf2bbc8b.97fcdfa7918b6db5
+ 75a2e4ff253e627c.77b0962268452db8.24927579ab68b971.56166d393119430b
+ 5f6be03ddd55aa62
+ after
+ 47221a41ba82d42e.434a5ac3c5c18507.78b28c70cf2bbc8b.97fcdfa7918b6db5
+ dd9cc52b456259c5.434a5ac3e0265180.78b28c7059847375.4752b89be09f6b34
+ 47221a41ba82d42e.cff20554c5c18507.a358e55ccf2bbc8b.97fcdfa7918b6db5
+ 75a2e4ff253e627c.77b0962268452db8.24927579ab68b971.56166d393119430b
+ 5f6be03ddd55aa62
+VPBLENDD_256_0xD7(mem)
+ before
+ 90c9b3a0b04c5ee5.c36620d01f213c5c.19508a18e4bd02bf.56aa38328ac5a5d3
+ c3fa624dc7091ac1.8dbbc82047b7a17a.8f9e5b225535c349.97ee2bf508d1be5c
+ d6cb6a2f3d999b22.30edda5b368dcb81.b766872cd8ba2a82.42a8482dc0153eb9
+ a30845342f069d33.064851ed8a2ef71e.6c7389238957f495.b2258d464e1f6196
+ 45b0f5ac4f7a659e
+ after
+ 90c9b3a0b04c5ee5.c36620d01f213c5c.19508a18e4bd02bf.56aa38328ac5a5d3
+ c3fa624dc7091ac1.8dbbc82047b7a17a.8f9e5b225535c349.97ee2bf508d1be5c
+ c3fa624db04c5ee5.c36620d047b7a17a.19508a18e4bd02bf.97ee2bf508d1be5c
+ a30845342f069d33.064851ed8a2ef71e.6c7389238957f495.b2258d464e1f6196
+ 45b0f5ac4f7a659e
+
+VPBLENDD_256_0xB5(reg)
+ before
+ 56977ccc5eb3847e.087d7147b85fdc20.6c172942df2661fc.8993ddf18218ddaf
+ 40241f101855fbe1.dff56954f4ad1317.bea85fc6d00245c8.eb900083e20aa0fc
+ 61a5d9e518ec0574.063eaa4700feff41.5845ede6f94dde2e.6f376dc6c238fba7
+ 1364a6b8fb05e0e2.5722ae0cf85d5ccd.963cd10cf79369d9.ef54a0a441afa7dc
+ 49b2150b787a63c9
+ after
+ 61a5d9e51855fbe1.063eaa4700feff41.bea85fc6f94dde2e.eb900083c238fba7
+ 40241f101855fbe1.dff56954f4ad1317.bea85fc6d00245c8.eb900083e20aa0fc
+ 61a5d9e518ec0574.063eaa4700feff41.5845ede6f94dde2e.6f376dc6c238fba7
+ 1364a6b8fb05e0e2.5722ae0cf85d5ccd.963cd10cf79369d9.ef54a0a441afa7dc
+ 49b2150b787a63c9
+VPBLENDD_256_0xB5(mem)
+ before
+ 571f48e685a5e998.b4ae82f45c2bc6d8.af6ef38ff6d6e5e5.d4d706a666612176
+ f665b621843cf675.9ece6904d8eaf302.ebeef4bc197657b6.6e62891ee14244b0
+ 0252daa8904c468d.2e1258560acfa50b.e56e2d807b486e6b.c02b54e204c30c34
+ 58b03067c6e0950c.c1c54a558e6516a0.7aba1bc53859e631.267d655d6c6fb6ae
+ fba3b7fbb4d27dc9
+ after
+ 571f48e685a5e998.b4ae82f45c2bc6d8.af6ef38ff6d6e5e5.d4d706a666612176
+ f665b621843cf675.9ece6904d8eaf302.ebeef4bc197657b6.6e62891ee14244b0
+ f665b62185a5e998.9ece6904d8eaf302.af6ef38f197657b6.d4d706a6e14244b0
+ 58b03067c6e0950c.c1c54a558e6516a0.7aba1bc53859e631.267d655d6c6fb6ae
+ fba3b7fbb4d27dc9
+
+VPBLENDD_256_0xB5(reg)
+ before
+ 9dea462879789e31.d24c344a41059e1d.b1323b6d0138836d.869d38796db47a33
+ 679f0e5056ee5594.4df1623d1dc61eed.5ba6270affd5281d.e6e502873565e79e
+ b50b0cdfe8bfde9c.a56d372c772fd0a7.1c6d0b9823c7405c.745cf4daad79e99e
+ e27d3b42ca7875f5.b68a2e046b4d7278.4ed3e183099a08d8.0dcf8a60f0fb3b5e
+ 8d0a41041bf79b0b
+ after
+ b50b0cdf56ee5594.a56d372c772fd0a7.5ba6270a23c7405c.e6e50287ad79e99e
+ 679f0e5056ee5594.4df1623d1dc61eed.5ba6270affd5281d.e6e502873565e79e
+ b50b0cdfe8bfde9c.a56d372c772fd0a7.1c6d0b9823c7405c.745cf4daad79e99e
+ e27d3b42ca7875f5.b68a2e046b4d7278.4ed3e183099a08d8.0dcf8a60f0fb3b5e
+ 8d0a41041bf79b0b
+VPBLENDD_256_0xB5(mem)
+ before
+ d0d894b24979c2d0.4c4097e399a4554c.5c16c3af142bbe8c.4e24a7384edbbc3a
+ b207ff56978e6fda.4e9f1c30f0cfba4d.73db721b8ed5700e.78ab59218e159731
+ 0f61fedd20425c55.43e8c7936b85e2a3.d7a6b833f657462b.28b6f1ac63d4d667
+ c3b40d31009f476c.8965927aa85307fb.644310e267befa0e.ba8f6c446ca5b588
+ 8a83c75442137042
+ after
+ d0d894b24979c2d0.4c4097e399a4554c.5c16c3af142bbe8c.4e24a7384edbbc3a
+ b207ff56978e6fda.4e9f1c30f0cfba4d.73db721b8ed5700e.78ab59218e159731
+ b207ff564979c2d0.4e9f1c30f0cfba4d.5c16c3af8ed5700e.4e24a7388e159731
+ c3b40d31009f476c.8965927aa85307fb.644310e267befa0e.ba8f6c446ca5b588
+ 8a83c75442137042
+
+VPBLENDD_256_0xB5(reg)
+ before
+ f5defd4a84aa423e.aacaa94054b3e94c.7a637b5040c56601.f67df616fe1649e4
+ 55ec0b91cbf7682b.a0704df438890120.742e7d81d1653b60.6922e6bad669efd9
+ 06f8eb95b6851eb3.8171753bc72e4915.d2119579f7c1c1c5.99fc5cba0cc5a718
+ 66509bc2dee1a082.289b9dff1dad7e57.ef5abda44c6436db.62d8d503bb362ece
+ a083cc7f00c64026
+ after
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+ 55ec0b91cbf7682b.a0704df438890120.742e7d81d1653b60.6922e6bad669efd9
+ 06f8eb95b6851eb3.8171753bc72e4915.d2119579f7c1c1c5.99fc5cba0cc5a718
+ 66509bc2dee1a082.289b9dff1dad7e57.ef5abda44c6436db.62d8d503bb362ece
+ a083cc7f00c64026
+VPBLENDD_256_0xB5(mem)
+ before
+ 2ec6bd1bf683994d.d03e1684e2952946.73b8412e57125c11.2853f36e6fdbd34f
+ ea7024c4ba79f46e.a00f58485b2ff6a8.3d96deb3906a9e6f.da4a3243fab1d7cc
+ af4c7e6467b20eb6.320f5d78e73b4257.62ffef7ae5c0019f.5f89769089727cff
+ 592546e9193ca251.e28a228222444bfd.bdc0f06f712041cb.155dbcbfb9abff94
+ 5611fe3e25e79c36
+ after
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+ ea7024c4ba79f46e.a00f58485b2ff6a8.3d96deb3906a9e6f.da4a3243fab1d7cc
+ ea7024c4f683994d.a00f58485b2ff6a8.73b8412e906a9e6f.2853f36efab1d7cc
+ 592546e9193ca251.e28a228222444bfd.bdc0f06f712041cb.155dbcbfb9abff94
+ 5611fe3e25e79c36
+
+VPBLENDD_256_0x85(reg)
+ before
+ 7ff33a776ab28f92.c3c8f73eed236e6b.0ccca1d0a7d64b46.2ca55d7e51971a1f
+ ec4d6bd823991353.cb02104eff712c2e.0b20d8d0127d7fdf.8a79b394a03047c8
+ fa6d8ecced276526.4b9c0a076a3499c9.3dd4c3ed00c62274.b20a6d9b7bf885f2
+ 039d9dbf63e8c0b7.216563544a787066.fd325c930d3d71b0.82220781fdf990c8
+ d48ffd3043412377
+ after
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+ ec4d6bd823991353.cb02104eff712c2e.0b20d8d0127d7fdf.8a79b394a03047c8
+ fa6d8ecced276526.4b9c0a076a3499c9.3dd4c3ed00c62274.b20a6d9b7bf885f2
+ 039d9dbf63e8c0b7.216563544a787066.fd325c930d3d71b0.82220781fdf990c8
+ d48ffd3043412377
+VPBLENDD_256_0x85(mem)
+ before
+ 861bcc9668dcfb2b.642a961d226962b1.28289621bc486f32.a787a12dd36ca840
+ 7293ee9e89d5d40f.79607452c53585c1.3bb01f5bdbb05058.961f8d2af1e103d0
+ 76c2e133c1386a50.9e8a33cae8d96593.38cb7aecc4bccf05.28461cf30127be0b
+ 6c7620432c117819.2ff6d0f128df40d2.f94323c19279aa64.b7474af59fcb149e
+ a170149c68584234
+ after
+ 861bcc9668dcfb2b.642a961d226962b1.28289621bc486f32.a787a12dd36ca840
+ 7293ee9e89d5d40f.79607452c53585c1.3bb01f5bdbb05058.961f8d2af1e103d0
+ 861bcc9668dcfb2b.79607452226962b1.28289621bc486f32.961f8d2af1e103d0
+ 6c7620432c117819.2ff6d0f128df40d2.f94323c19279aa64.b7474af59fcb149e
+ a170149c68584234
+
+VPBLENDD_256_0x85(reg)
+ before
+ 400b7455f75a837a.327928b9e76dbb97.88ee453421d5502a.5be597c762f29ba2
+ f265688ae95e141b.a29973810e57eff5.05bf90fd6e47d248.3b7d51e84f345feb
+ 11caeca9d9ef31c4.99a07f88bcdccf60.02b5acbaabc002d8.73d6cd127649b16a
+ fb86fa1d63991621.f45bc7b80d061804.db1c96d575cc1b85.e0be8830f23f4f4c
+ 5ffffc2ee022f3bd
+ after
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+ f265688ae95e141b.a29973810e57eff5.05bf90fd6e47d248.3b7d51e84f345feb
+ 11caeca9d9ef31c4.99a07f88bcdccf60.02b5acbaabc002d8.73d6cd127649b16a
+ fb86fa1d63991621.f45bc7b80d061804.db1c96d575cc1b85.e0be8830f23f4f4c
+ 5ffffc2ee022f3bd
+VPBLENDD_256_0x85(mem)
+ before
+ ca67a7f85bfd5ae8.0ae4905125e8ffdd.8d96c7fe1ee4860c.ec4048bc67f75afc
+ fec0047a7fdc3ff9.9b32a8b3b86927a5.411cfb470a7fd5a5.916dc0da1ecefbe9
+ d7d78fa069cc5f1e.0bba41aebaa8cb25.ecbbe07eeee5c0fa.26eef99b36dc39f7
+ 3277c55635d77680.b4c954aec72f2608.6b3df18ee5210438.0610ef6b49ae52d3
+ 8f1f9eb6f6cf8028
+ after
+ ca67a7f85bfd5ae8.0ae4905125e8ffdd.8d96c7fe1ee4860c.ec4048bc67f75afc
+ fec0047a7fdc3ff9.9b32a8b3b86927a5.411cfb470a7fd5a5.916dc0da1ecefbe9
+ ca67a7f85bfd5ae8.9b32a8b325e8ffdd.8d96c7fe1ee4860c.916dc0da1ecefbe9
+ 3277c55635d77680.b4c954aec72f2608.6b3df18ee5210438.0610ef6b49ae52d3
+ 8f1f9eb6f6cf8028
+
+VPBLENDD_256_0x85(reg)
+ before
+ 1c6703e8d6cbffa3.e96e2088fe0c404e.f3abde207a8c76fa.986faa650c405d8b
+ 0934196e882e0df0.d9861e23e07478b2.25acdc6e6f4bf5a9.501d87ee7e4d861e
+ b1d2dcb2a585e4ba.de8d3a11f81ddbd8.a418490543f6dfbe.6f13051558543d1e
+ 728c4822cb5bc1ae.d44df140621225ee.cd3b2152911c72e8.d11d9fc6b5613bb6
+ 5206d0edb2813f13
+ after
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+ 0934196e882e0df0.d9861e23e07478b2.25acdc6e6f4bf5a9.501d87ee7e4d861e
+ b1d2dcb2a585e4ba.de8d3a11f81ddbd8.a418490543f6dfbe.6f13051558543d1e
+ 728c4822cb5bc1ae.d44df140621225ee.cd3b2152911c72e8.d11d9fc6b5613bb6
+ 5206d0edb2813f13
+VPBLENDD_256_0x85(mem)
+ before
+ ce9c17766ac00361.a7af5a28963ddf77.9793bd9b3960111d.fc6061bff646e8d1
+ 21a9ed4ef92845cb.ab880c32a1b67cc2.032b1c0d99125d94.8dd403ba0e027e25
+ 27fad05f7cc7be7e.dc615cab8952d23a.f4e089849f34c37d.dce305ae73db7092
+ bc5b3a970fa92da5.948645ffe89e1d8c.468080eb66d3ff04.45d96206c45df9c1
+ 240216309a155661
+ after
+ ce9c17766ac00361.a7af5a28963ddf77.9793bd9b3960111d.fc6061bff646e8d1
+ 21a9ed4ef92845cb.ab880c32a1b67cc2.032b1c0d99125d94.8dd403ba0e027e25
+ ce9c17766ac00361.ab880c32963ddf77.9793bd9b3960111d.8dd403ba0e027e25
+ bc5b3a970fa92da5.948645ffe89e1d8c.468080eb66d3ff04.45d96206c45df9c1
+ 240216309a155661
+
+VPBLENDD_256_0x29(reg)
+ before
+ d5aa1e97948ec31c.bc98a9e0cdd84c6d.3145c49a5d259b64.d5d57e2e0bfacf56
+ b41c74a84b547b9e.027d9928d262d802.0de9d3e88273866d.7cacfd3aa9b5ed9f
+ 1da516cd5df4bc95.6cd5845a3b538d8f.86bd7055f3141b54.19d27bf95d11160b
+ 6c92ff7366f9bfaa.d56de86224b52641.f60e964d4d9595c5.87107358421905c5
+ a235624474d977f9
+ after
+ b41c74a84b547b9e.6cd5845ad262d802.86bd70558273866d.7cacfd3a5d11160b
+ b41c74a84b547b9e.027d9928d262d802.0de9d3e88273866d.7cacfd3aa9b5ed9f
+ 1da516cd5df4bc95.6cd5845a3b538d8f.86bd7055f3141b54.19d27bf95d11160b
+ 6c92ff7366f9bfaa.d56de86224b52641.f60e964d4d9595c5.87107358421905c5
+ a235624474d977f9
+VPBLENDD_256_0x29(mem)
+ before
+ 450cc2a7105e28d4.fd2d2c0601f0c38c.1911402ca7966043.ba28413c2c82326b
+ 4e60116f32b3d482.2cc297f3cb6403e5.138d08a4e302f7c2.2f576e8f2a652cf2
+ 98feca87f5e4362e.559f3ea55fe1ba61.a1adbcb6f103a7e9.afe718b0e6ccbf08
+ feb369da75fe0c05.d30f1c8759f324ad.9e3dd94ef0a72be6.97243a0df9432956
+ 4459d3110254a48b
+ after
+ 450cc2a7105e28d4.fd2d2c0601f0c38c.1911402ca7966043.ba28413c2c82326b
+ 4e60116f32b3d482.2cc297f3cb6403e5.138d08a4e302f7c2.2f576e8f2a652cf2
+ 450cc2a732b3d482.2cc297f301f0c38c.138d08a4e302f7c2.ba28413c2a652cf2
+ feb369da75fe0c05.d30f1c8759f324ad.9e3dd94ef0a72be6.97243a0df9432956
+ 4459d3110254a48b
+
+VPBLENDD_256_0x29(reg)
+ before
+ 10d3dc289a8d6d51.5e486a56cf0c0f33.045d2d0756277f75.e509da59f9fa40e2
+ 58df52bd5f7ac055.938c4ae61f1afee3.43d66e90f2080564.54dc3bc12b06a20c
+ 78c7323eeda6d842.784a847780359341.ebc6d98ec723f327.c58378749fda0c8e
+ ccd77717df9df2c5.eb4d94f30e688b7b.5a796c6d7403856a.16ca0d5c737f3b94
+ 217d7767c303eb4b
+ after
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+ 58df52bd5f7ac055.938c4ae61f1afee3.43d66e90f2080564.54dc3bc12b06a20c
+ 78c7323eeda6d842.784a847780359341.ebc6d98ec723f327.c58378749fda0c8e
+ ccd77717df9df2c5.eb4d94f30e688b7b.5a796c6d7403856a.16ca0d5c737f3b94
+ 217d7767c303eb4b
+VPBLENDD_256_0x29(mem)
+ before
+ c4683180aa71d8df.b05d1db2d2eb4a89.c663f647e6c0a2bb.eb3b22999334f6d8
+ d956b79344d5bd7b.80a4217c611d1b3b.e756275f2348932d.f957f87ec043831e
+ 3e15858cae3c574c.98f77de128bea287.28f3a128e20c1cfe.e21be88998bb68e7
+ cd6f185704b1627d.54a32f4ec45a1b18.6606e28c3e18f65a.00d1f024b628e1e0
+ b1c60bbdb71629b4
+ after
+ c4683180aa71d8df.b05d1db2d2eb4a89.c663f647e6c0a2bb.eb3b22999334f6d8
+ d956b79344d5bd7b.80a4217c611d1b3b.e756275f2348932d.f957f87ec043831e
+ c468318044d5bd7b.80a4217cd2eb4a89.e756275f2348932d.eb3b2299c043831e
+ cd6f185704b1627d.54a32f4ec45a1b18.6606e28c3e18f65a.00d1f024b628e1e0
+ b1c60bbdb71629b4
+
+VPBLENDD_256_0x29(reg)
+ before
+ 4f4635be36127d10.6331ebe06141993b.10f4322dd17ec29b.7e5b66795479e06c
+ 389d6b95cfa819a0.dd277a14e1f7b9b2.283683eceab5d2bb.4abda7da3f3a9461
+ c617a7ad2062380f.151d41dda1df7e0d.f8b51cf6ab8c8825.a7f9229b1b68cf64
+ 56ffe772c2ce180a.e8dfbc29bc05a479.dcbcfbb7b18d2084.72dc54a8060d4da2
+ 8530b8ed1938ca47
+ after
+ 389d6b95cfa819a0.151d41dde1f7b9b2.f8b51cf6eab5d2bb.4abda7da1b68cf64
+ 389d6b95cfa819a0.dd277a14e1f7b9b2.283683eceab5d2bb.4abda7da3f3a9461
+ c617a7ad2062380f.151d41dda1df7e0d.f8b51cf6ab8c8825.a7f9229b1b68cf64
+ 56ffe772c2ce180a.e8dfbc29bc05a479.dcbcfbb7b18d2084.72dc54a8060d4da2
+ 8530b8ed1938ca47
+VPBLENDD_256_0x29(mem)
+ before
+ bdc2cb5672f2017e.45a226505378f23d.323868e24f76e622.30991b9b9747d686
+ f65d07cf2d49af74.ed4d60b36fea0553.d0f6c0f6753d0133.5096780efa43e5d4
+ 0ccfea4465488f54.ab4a9207b1b28bf8.9ce340504b67b1d8.98000f7c750f8a1d
+ dbe3efa236fc5f4c.dbe6b7b8b55cc1d9.73cc64dbecffb13e.6323da51a536010b
+ 0f4bd7f92545854a
+ after
+ bdc2cb5672f2017e.45a226505378f23d.323868e24f76e622.30991b9b9747d686
+ f65d07cf2d49af74.ed4d60b36fea0553.d0f6c0f6753d0133.5096780efa43e5d4
+ bdc2cb562d49af74.ed4d60b35378f23d.d0f6c0f6753d0133.30991b9bfa43e5d4
+ dbe3efa236fc5f4c.dbe6b7b8b55cc1d9.73cc64dbecffb13e.6323da51a536010b
+ 0f4bd7f92545854a
+
+VPSLLVD_128(reg)
+ before
+ f7c301e192c65387.3f6492d3bd70d985.da6ccb331872e3a2.317da9857511bf91
+ 76d954738748a76e.141f4fc515b0b92d.022acae275822dff.b2c1893901aa94fd
+ ead7cd1da054bdaa.36e0a3635bc9bd70.b06ab0336918da9b.d26682e4add5efad
+ ae0a664a7a78d0e8.81730899abc69f79.40797a9090bf2722.6d360f70949e8acd
+ 5fffadcad311238a
+ after
+ 0000000000000000.0000000000000000.57100000f8000000.2c189390529fa000
+ 76d954738748a76e.141f4fc515b0b92d.022acae275822dff.b2c1893901aa94fd
+ 0000000000000000.0000000000000000.000000130000001b.000000040000000d
+ ae0a664a7a78d0e8.81730899abc69f79.40797a9090bf2722.6d360f70949e8acd
+ 5fffadcad311238a
+VPSLLVD_128(mem)
+ before
+ 848bd6df853b7310.1dbe1d65b13f1dd4.d1a3fc521fb31c75.0ea4236784034f42
+ b8a70899c628398b.953feedce036df19.023efb7cd69df090.7634a723e47090a4
+ d71ebee6b3e22f25.70d9d31aa3e85464.f00e7f03e98ed6f5.d4780230499324f7
+ bcbe75b16777120d.0cd8c98b97e1b660.77e106d177958bd1.84bb30fa52f748e5
+ e2482eed9828371a
+ after
+ 848bd6df853b7310.1dbe1d65b13f1dd4.d1a3fc5200000015.0000000700000002
+ b8a70899c628398b.953feedce036df19.023efb7cd69df090.7634a723e47090a4
+ 0000000000000000.0000000000000000.0000000012000000.1a53918091c24290
+ bcbe75b16777120d.0cd8c98b97e1b660.77e106d177958bd1.84bb30fa52f748e5
+ e2482eed9828371a
+
+VPSLLVD_128(reg)
+ before
+ 4a6df775b9b32e43.4552a7e5fff39e6d.c387cd9c58ae42ba.73810bd399bbcb4f
+ 187487fe5123690c.4da5d27097608e72.f233dab781da341d.c0ba0af56d0e529c
+ a8aadaf5fb052421.b084713d4acc9f47.f628ed49aef1c736.395a7f240f9adbe4
+ 565bedc454e49a2d.49bb003834438d19.29b200bf7c8038b1.bc2ce64a9a6a2352
+ 24fbbc552b8ae513
+ after
+ 0000000000000000.0000000000000000.67b56e0007400000.0ba0af50d0e529c0
+ 187487fe5123690c.4da5d27097608e72.f233dab781da341d.c0ba0af56d0e529c
+ 0000000000000000.0000000000000000.0000000900000016.0000000400000004
+ 565bedc454e49a2d.49bb003834438d19.29b200bf7c8038b1.bc2ce64a9a6a2352
+ 24fbbc552b8ae513
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+VPMASKMOVD_128_LoadForm(reg)
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+VPMASKMOVD_256_LoadForm(reg)
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+VPMASKMOVD_256_LoadForm(reg)
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+VPMASKMOVD_256_LoadForm(reg)
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+VPMASKMOVQ_128_LoadForm(reg)
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+ e4075aaaebedb98b.0d1e6f3298ab3b12.18300f655dc88b53.e7dfd9f1aee4e425
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 228a1c4d6ce2a34c.a09943ed3423c98d.6b4f46a25b3a89de.5c24fb31cd1fd6ad
+ 0000000000000000
+VPGATHERQQ_256_1(mem)
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+ b4560aba39b835dc.1f79d0b96bec7b2c.884a58d393e9c278.074c6a4bc113cf09
+ ac64394bc99331c7.baa42cd4b0a8f0e3.758c739eb3469645.a0e93ff30798d2be
+ ff906d17de8b549f
+ after
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+ 6fd118fe57ba4ee6.8539f7ac505e0f13.483364307cec4bd2.29fbc1c2c0ffdfe5
+ b4560aba39b835dc.1f79d0b96bec7b2c.884a58d393e9c278.074c6a4bc113cf09
+ ac64394bc99331c7.baa42cd4b0a8f0e3.758c739eb3469645.a0e93ff30798d2be
+ ff906d17de8b549f
+
+VPGATHERQQ_256_1(reg)
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+ 40e783436fa78557.e70f015b22d516ee.20a91ca3eb9fa59d.8784d018391109c6
+ 3a0fc203c1ca0c65.4122f2928433d662.03fc081079d1bdd8.c4b16a7f387680b1
+ 2b310bafd349c210.7fb0d00ec3605b3b.172927fa61228e21.dffadc7e6f2c0534
+ 639bd1efa9ae846b
+ after
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+ 30fb201392e6c149.e439528cd3c92ec4.617537586c90dad5.0000000000000016
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 2b310bafd349c210.7fb0d00ec3605b3b.172927fa61228e21.d7e2ce16c8bb36a6
+ 0000000000000000
+VPGATHERQQ_256_1(mem)
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+ d7d4f79b5a072062.1f4d653b6b506cac.d52804460b14608e.0004abb973120c4f
+ dfe47f8d68d6155b.3ac1cfd388cf38d4.048bb3baab93b840.ec2a6a4634a9916c
+ 803c3b63aa61b578.7c1df2c7969be209.475700e25ad085c7.391a0bc0804f7e07
+ f391ba85a30141bd
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+ d7d4f79b5a072062.1f4d653b6b506cac.d52804460b14608e.0004abb973120c4f
+ dfe47f8d68d6155b.3ac1cfd388cf38d4.048bb3baab93b840.ec2a6a4634a9916c
+ 803c3b63aa61b578.7c1df2c7969be209.475700e25ad085c7.391a0bc0804f7e07
+ f391ba85a30141bd
+
+VPGATHERQQ_256_1(reg)
+ before
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+ db03f55b9d75f6e8.bfb2fd26fa9ba28b.a37f1133b40b8508.381d21c111762bc6
+ 2276d8260c30c095.74495bcc9f43c7ba.a0fe65635da7550b.fd8e4e31b1d6dc76
+ 04607aaa83e70fcc.f3189dc6a897477c.f355225f2680b489.055ac9c58fe4b16b
+ ddbb3d5a761c96c1
+ after
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+ 254ba4efe9b94529.4717d6f7ec24ead4.0000000000000026.0000000000000000
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 04607aaa83e70fcc.f3189dc6a897477c.235f93d9362529a6.1fd58558d5bc54ba
+ 0000000000000000
+VPGATHERQQ_256_1(mem)
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+ b9b82cb7619bdf25.cf3e8f2b06c553c9.9f2a713b14741b50.6ac685b23f536408
+ 46c83fe868543c1a.9b5be32f9040ee43.bb2ff918a4513b78.8fd89c7683f93791
+ 466ff8d165c9b5a2
+ after
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+ 2b2ec3f793fc4103.cf88a950b335ec4b.7c4c7c211733052b.cc7d862a4bdacf6c
+ b9b82cb7619bdf25.cf3e8f2b06c553c9.9f2a713b14741b50.6ac685b23f536408
+ 46c83fe868543c1a.9b5be32f9040ee43.bb2ff918a4513b78.8fd89c7683f93791
+ 466ff8d165c9b5a2
+
+VPGATHERQQ_128_2(reg)
+ before
+ 9b46c5212fbd4bd8.5f99a76675a446fc.409bd2b99ca22b53.5c98c194954651bf
+ 9b1a2ec12ed364ce.8f69110d5406e8e7.c9b9872577e87495.0fa1758bb1cf4942
+ 51a7600cae066c20.627228b9d0f60ef8.42722fcf6d0d37a6.5f86c0d9c5680f1d
+ c9a98660fb52ce6b.64f09946b7f0a44a.b881f613ca0ddf21.d8824f5a9e8e906b
+ 07d2cdea05bcb649
+ after
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+ 0000000000000000.0000000000000000.026f4ae67288ad4c.72630652551946fc
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 0000000000000000.0000000000000000.b881f613ca0ddf21.d8824f5a9e8e906b
+ 0000000000000000
+VPGATHERQQ_128_2(mem)
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+ b55e49a6b520a622.31fa618f2b26565b.283f3873f1f3d023.c8958fd9e98f8ec7
+ 4b119e8b944e4656.38c16d22a7a65237.0087becbddf43ee2.7b11b91342086d2a
+ c80893ef34753d89.32ee1e2d1f2f597c.38344e7463efcc52.5ad3b257324de167
+ 7199a5010659561a
+ after
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+ b55e49a6b520a622.31fa618f2b26565b.283f3873f1f3d023.c8958fd9e98f8ec7
+ 4b119e8b944e4656.38c16d22a7a65237.0087becbddf43ee2.7b11b91342086d2a
+ c80893ef34753d89.32ee1e2d1f2f597c.38344e7463efcc52.5ad3b257324de167
+ 7199a5010659561a
+
+VPGATHERQQ_128_2(reg)
+ before
+ cd1cbf6d082939e1.b57fd3ae5f1076d8.2a3b9f0de0bdd7c5.5b8493494f60678f
+ 791b2cf684b7f455.a0b10ba3e29bdd5e.2c651d1c364c39af.f6b139286dc4f9b6
+ 815118fac801f514.14dbe7ac89925f38.4527c3b76dd9e9d6.94f7eeec889570e3
+ f279add41f02a7ba.9e3912a41f72e681.803fbe3bd05f55d4.c1945c706d51b731
+ 0ac22f92e874babc
+ after
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+ 0000000000000000.0000000000000000.a8ee7c3782f75f14.000000000000003c
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 0000000000000000.0000000000000000.803fbe3bd05f55d4.b47a6129a748634f
+ 0000000000000000
+VPGATHERQQ_128_2(mem)
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+ 000fc33dd51763e8.2ef927fd8b281a29.32e129bd7a5ad812.77d963cc00a032fb
+ 2edce56a9fab8e81.b8441fc725dec880.89654a08c9b2b031.b39b69870fe3c274
+ 4e5e9ff7c70b29d1
+ after
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+ 1ec3b71cd0dba4fc.3c918979341acd28.218007d04cdab7d2.8d5b62694e460dcb
+ 000fc33dd51763e8.2ef927fd8b281a29.32e129bd7a5ad812.77d963cc00a032fb
+ 2edce56a9fab8e81.b8441fc725dec880.89654a08c9b2b031.b39b69870fe3c274
+ 4e5e9ff7c70b29d1
+
+VPGATHERQQ_128_2(reg)
+ before
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+ cd031d14dcbaa15b.f5a584d89a41d076.61cedf5f7cc351a5.a62264bc6aa5b4e3
+ 5920cdeb2f4f9d62.c8d1b4d27405e4dd.c4fcfad919eebb6e.8a8d3c1c2f369c98
+ 70497026110cd6b9
+ after
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+ 0000000000000000.0000000000000000.9cba78c938dd0f28.0000000000000030
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 0000000000000000.0000000000000000.c4fcfad919eebb6e.23e37875c43e845a
+ 0000000000000000
+VPGATHERQQ_128_2(mem)
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+ 6f9e9aac5774f0ac.4c1e807590e8d9dd.116e15ab394f0f74.14bfff5edcf974c4
+ a1b1e8df53fea9b7.cb76dae035e5f28a.9e579e44bcceffdc.19ce42219ad19989
+ 0403422d9cbc639d.09aec5dee4a642fb.d7a29dc96683bbd1.159e3f0bfb318084
+ 17ee22764a149451
+ after
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+ 6f9e9aac5774f0ac.4c1e807590e8d9dd.116e15ab394f0f74.14bfff5edcf974c4
+ a1b1e8df53fea9b7.cb76dae035e5f28a.9e579e44bcceffdc.19ce42219ad19989
+ 0403422d9cbc639d.09aec5dee4a642fb.d7a29dc96683bbd1.159e3f0bfb318084
+ 17ee22764a149451
+
+VPGATHERQQ_256_2(reg)
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+ 56f94d43e653f3d4.8e56c88b41c68e6c.efb2fc088c69379a.7b4daa0a5a7f47d3
+ ac2ced5ccaa816c1.cdd04d523509d78d.aff5a1eb1d63b400.fe25127f3cbfef19
+ 37cf2367cd6f17f0.6d798da4a570d2f9.5e0886d2e711189b.5c4f9f507524145c
+ 2106fd5acf2ca0b8
+ after
+ 287819bfd576418e.24d15372fd2b0c7b.11846ccde72935cc.478bbd1701ea2f6f
+ 0000000000000038.00000000000000ec.0000000000000030.00000000000000bc
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ a748634f0e5b0240.ef43fa17f6482302.23e37875c43e845a.7cf328173188c7ff
+ 0000000000000000
+VPGATHERQQ_256_2(mem)
+ before
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+ 56d6ba66a2e9ee7e.89a604cd86527e26.0eea6b74d457271b.797f71369235e7be
+ 311d17ec7c525359.5d5b4d38fdbf2b77.acaa528a2c2823cd.592d11c437902042
+ 6458cd23918d5c07
+ after
+ da87d9791852814a.029c1bc03aa660fe.fb8e355d5d786bcd.08a8d8183571cf06
+ 120edf891a13a12e.195003c45f495e87.024af059299b8e24.b791c21b557e46de
+ 56d6ba66a2e9ee7e.89a604cd86527e26.0eea6b74d457271b.797f71369235e7be
+ 311d17ec7c525359.5d5b4d38fdbf2b77.acaa528a2c2823cd.592d11c437902042
+ 6458cd23918d5c07
+
+VPGATHERQQ_256_2(reg)
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+ 28154bc0945a8cc3.dd12066355ca151a.62d261a406b1dba1.cb7912170ef5efd3
+ fa1e65b6d52259f1.c63af00cecd24a38.aa0b855d3030b7b2.6500434631e99960
+ 26944cedfa7cd9d0.76cf0bcd055b4751.8893a0e8da01d0e5.c09790e030e25518
+ 6979a5c0d65c0e17
+ after
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+ 00000000000000a4.0000000000000060.000000000000005c.9f1941dfee21b158
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ d8c3c2182bb724bf.3de12b6f02af9633.02af9633119a4f34.c09790e030e25518
+ 0000000000000000
+VPGATHERQQ_256_2(mem)
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+ aa3f48a5b1a168da.40da83a8c0c8c4a8.ab793e4154de278a.125c700dc841c265
+ 00a9333aeff3520f.4d5b5476713e4961.f11dd8ff6d487da0.b9771d776537073a
+ 308d9d80fd6da63e
+ after
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+ d212d5c74bbf2c5c.bdb62f8a24d3a310.5d32860cede54add.2f806ae4da8e6a23
+ aa3f48a5b1a168da.40da83a8c0c8c4a8.ab793e4154de278a.125c700dc841c265
+ 00a9333aeff3520f.4d5b5476713e4961.f11dd8ff6d487da0.b9771d776537073a
+ 308d9d80fd6da63e
+
+VPGATHERQQ_256_2(reg)
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+ bf98c4dc4d869e40.541f20f823d8e110.37631c93419f2ba4.926e6085e3644079
+ ef06c4e79d61d077.69a37ad9b0635d14.2b626a99f9816066.0693a606d90d8673
+ 1f5f46ff196b0b4d.2d53fbe2464e373f.daade6bff5d4a9b9.a1067e7fb118f447
+ ef0394ce37027611
+ after
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+ 0000000000000030.7e29098744c75860.c7d3394608ca7358.e96ffc840e84d8f0
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 23e37875c43e845a.2d53fbe2464e373f.daade6bff5d4a9b9.a1067e7fb118f447
+ 0000000000000000
+VPGATHERQQ_256_2(mem)
+ before
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+ 868bff4fd4ccac46.2a419435837e2a9c.fec3247e2d2833c6.bcb51b8a7f4e2e2b
+ 1a06c38a0907b7fd.d49cd81ea21dc103.ef7afcbada6cbea7.cd8b01c8863efcd8
+ d35beff24f8bf821
+ after
+ 7dc593cd3746f8eb.5c5e76820ba1bb5d.296b50eeaf155cae.4f02ba6282957138
+ d689285a7c6066f4.b1c082cbbffe4c43.eb2724d8b834b77c.971b12dcecbf247f
+ 868bff4fd4ccac46.2a419435837e2a9c.fec3247e2d2833c6.bcb51b8a7f4e2e2b
+ 1a06c38a0907b7fd.d49cd81ea21dc103.ef7afcbada6cbea7.cd8b01c8863efcd8
+ d35beff24f8bf821
+
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/avx2-1.vgtest valgrind-3.8.0.new/none/tests/amd64/avx2-1.vgtest
--- valgrind-3.8.0.orig/none/tests/amd64/avx2-1.vgtest 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/none/tests/amd64/avx2-1.vgtest 2012-09-13 11:19:25.189050665 +0200
@@ -0,0 +1,3 @@
+prog: avx2-1
+prereq: ../../../tests/x86_amd64_features amd64-avx
+vgopts: -q
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/bmi.c valgrind-3.8.0.new/none/tests/amd64/bmi.c
--- valgrind-3.8.0.orig/none/tests/amd64/bmi.c 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/none/tests/amd64/bmi.c 2012-09-12 19:54:35.476028784 +0200
@@ -0,0 +1,1143 @@
+
+#include <stdio.h>
+
+typedef unsigned long long int ULong;
+typedef unsigned int UInt;
+
+__attribute__((noinline))
+void do_andn64 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg1, ULong arg2 )
+{
+ ULong tem, flag;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "andn %2, %3, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=r" (flag) : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ *flags = flag & 0x8d5;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "andn %2, %3, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=r" (flag) : "m" (arg1), "r" (arg2) : "cc"
+ );
+ if (*res != tem || *flags != (flag & 0x8d5))
+ printf ("Difference between r and m variants\n");
+}
+
+__attribute__((noinline))
+void do_andn32 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, UInt arg1, UInt arg2 )
+{
+ ULong tem, flag;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "andn %2, %3, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=r" (flag) : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ *flags = flag & 0x8d5;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "andn %2, %3, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=r" (flag) : "m" (arg1), "r" (arg2) : "cc"
+ );
+ if (*res != tem || *flags != (flag & 0x8d5))
+ printf ("Difference between r and m variants\n");
+}
+
+
+__attribute__((noinline))
+void do_mulx64 ( /*OUT*/ULong* res1, /*OUT*/ULong* res2,
+ ULong arg1, ULong arg2 )
+{
+ ULong tem1, tem2, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "movabsq $0x5555555555555555, %1" "\n\t"
+ "movq %4, %%rdx" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "popfq" "\n\t"
+ "mulx %5, %1, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %3" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem1), "=&r" (tem2), "=&r" (flag1), "=r" (flag2)
+ : "g" (arg1), "r" (arg2) : "cc", "rdx"
+ );
+ *res1 = tem1;
+ *res2 = tem2;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "movabsq $0x5555555555555555, %1" "\n\t"
+ "movq %4, %%rdx" "\n\t"
+ "pushfq" "\n\t"
+ "popq %2" "\n\t"
+ "mulx %5, %1, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %3" "\n"
+ : "=&r" (tem1), "=&r" (tem2), "=&r" (flag3), "=r" (flag4)
+ : "g" (arg1), "m" (arg2) : "cc", "rdx"
+ );
+ if (*res1 != tem1 || *res2 != tem2)
+ printf ("Difference between r and m variants\n");
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+__attribute__((noinline))
+void do_mulx32 ( /*OUT*/ULong* res1, /*OUT*/ULong* res2,
+ UInt arg1, UInt arg2 )
+{
+ ULong tem1, tem2, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "movabsq $0x5555555555555555, %1" "\n\t"
+ "movl %4, %%edx" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "popfq" "\n\t"
+ "mulx %5, %k1, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %3" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem1), "=&r" (tem2), "=&r" (flag1), "=r" (flag2)
+ : "g" (arg1), "r" (arg2) : "cc", "rdx"
+ );
+ *res1 = tem1;
+ *res2 = tem2;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "movabsq $0x5555555555555555, %1" "\n\t"
+ "movl %4, %%edx" "\n\t"
+ "pushfq" "\n\t"
+ "popq %2" "\n\t"
+ "mulx %5, %k1, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %3" "\n"
+ : "=&r" (tem1), "=&r" (tem2), "=&r" (flag3), "=r" (flag4)
+ : "g" (arg1), "m" (arg2) : "cc", "rdx"
+ );
+ if (*res1 != tem1 || *res2 != tem2)
+ printf ("Difference between r and m variants\n");
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+
+__attribute__((noinline))
+void do_sarx64 ( /*OUT*/ULong* res, ULong arg1, ULong arg2 )
+{
+ ULong tem, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "sarx %3, %4, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag1), "=r" (flag2)
+ : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "sarx %3, %4, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag3), "=r" (flag4)
+ : "r" (arg1), "m" (arg2) : "cc"
+ );
+ if (*res != tem)
+ printf ("Difference between r and m variants\n");
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+__attribute__((noinline))
+void do_sarx32 ( /*OUT*/ULong* res, UInt arg1, UInt arg2 )
+{
+ ULong tem, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "sarx %3, %4, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag1), "=r" (flag2)
+ : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "sarx %3, %4, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag3), "=r" (flag4)
+ : "r" (arg1), "m" (arg2) : "cc"
+ );
+ if (*res != tem)
+ printf ("Difference between r and m variants\n");
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+
+__attribute__((noinline))
+void do_shlx64 ( /*OUT*/ULong* res, ULong arg1, ULong arg2 )
+{
+ ULong tem, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "shlx %3, %4, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag1), "=r" (flag2)
+ : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "shlx %3, %4, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag3), "=r" (flag4)
+ : "r" (arg1), "m" (arg2) : "cc"
+ );
+ if (*res != tem)
+ printf ("Difference between r and m variants\n");
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+__attribute__((noinline))
+void do_shlx32 ( /*OUT*/ULong* res, UInt arg1, UInt arg2 )
+{
+ ULong tem, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "shlx %3, %4, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag1), "=r" (flag2)
+ : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "shlx %3, %4, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag3), "=r" (flag4)
+ : "r" (arg1), "m" (arg2) : "cc"
+ );
+ if (*res != tem)
+ printf ("Difference between r and m variants\n");
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+
+__attribute__((noinline))
+void do_shrx64 ( /*OUT*/ULong* res, ULong arg1, ULong arg2 )
+{
+ ULong tem, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "shrx %3, %4, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag1), "=r" (flag2)
+ : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "shrx %3, %4, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag3), "=r" (flag4)
+ : "r" (arg1), "m" (arg2) : "cc"
+ );
+ if (*res != tem)
+ printf ("Difference between r and m variants\n");
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+__attribute__((noinline))
+void do_shrx32 ( /*OUT*/ULong* res, UInt arg1, UInt arg2 )
+{
+ ULong tem, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "shrx %3, %4, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag1), "=r" (flag2)
+ : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "shrx %3, %4, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag3), "=r" (flag4)
+ : "r" (arg1), "m" (arg2) : "cc"
+ );
+ if (*res != tem)
+ printf ("Difference between r and m variants\n");
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+
+__attribute__((noinline))
+void do_rorx64 ( /*OUT*/ULong* res1, /*OUT*/ULong* res2, ULong arg )
+{
+ ULong tem, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "rorx $12, %3, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag1), "=r" (flag2) : "r" (arg) : "cc"
+ );
+ *res1 = tem;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "rorx $67, %3, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag3), "=r" (flag4) : "m" (arg) : "cc"
+ );
+ *res2 = tem;
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+__attribute__((noinline))
+void do_rorx32 ( /*OUT*/ULong* res1, /*OUT*/ULong* res2, UInt arg )
+{
+ ULong tem, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "rorx $12, %3, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag1), "=r" (flag2) : "r" (arg) : "cc"
+ );
+ *res1 = tem;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "rorx $67, %3, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag3), "=r" (flag4) : "m" (arg) : "cc"
+ );
+ *res2 = tem;
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+
+__attribute__((noinline))
+void do_blsi64 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg )
+{
+ ULong tem, flag;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "blsi %2, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg) : "cc"
+ );
+ *res = tem;
+ *flags = flag & 0x8d5;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "blsi %2, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "m" (arg) : "cc"
+ );
+ if (*res != tem || *flags != (flag & 0x8d5))
+ printf ("Difference between r and m variants\n");
+}
+
+__attribute__((noinline))
+void do_blsi32 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, UInt arg )
+{
+ ULong tem, flag;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "blsi %2, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg) : "cc"
+ );
+ *res = tem;
+ *flags = flag & 0x8d5;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "blsi %2, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "m" (arg) : "cc"
+ );
+ if (*res != tem || *flags != (flag & 0x8d5))
+ printf ("Difference between r and m variants\n");
+}
+
+
+__attribute__((noinline))
+void do_blsmsk64 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg )
+{
+ ULong tem, flag;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "blsmsk %2, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg) : "cc"
+ );
+ *res = tem;
+ *flags = flag & 0x8d5;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "blsmsk %2, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "m" (arg) : "cc"
+ );
+ if (*res != tem || *flags != (flag & 0x8d5))
+ printf ("Difference between r and m variants\n");
+}
+
+__attribute__((noinline))
+void do_blsmsk32 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, UInt arg )
+{
+ ULong tem, flag;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "blsmsk %2, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg) : "cc"
+ );
+ *res = tem;
+ *flags = flag & 0x8d5;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "blsmsk %2, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "m" (arg) : "cc"
+ );
+ if (*res != tem || *flags != (flag & 0x8d5))
+ printf ("Difference between r and m variants\n");
+}
+
+
+__attribute__((noinline))
+void do_blsr64 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg )
+{
+ ULong tem, flag;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "blsr %2, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg) : "cc"
+ );
+ *res = tem;
+ *flags = flag & 0x8d5;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "blsr %2, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "m" (arg) : "cc"
+ );
+ if (*res != tem || *flags != (flag & 0x8d5))
+ printf ("Difference between r and m variants\n");
+}
+
+__attribute__((noinline))
+void do_blsr32 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, UInt arg )
+{
+ ULong tem, flag;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "blsr %2, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg) : "cc"
+ );
+ *res = tem;
+ *flags = flag & 0x8d5;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "blsr %2, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "m" (arg) : "cc"
+ );
+ if (*res != tem || *flags != (flag & 0x8d5))
+ printf ("Difference between r and m variants\n");
+}
+
+
+__attribute__((noinline))
+void do_bextr64 ( /*OUT*/UInt* flags, /*OUT*/ULong* res,
+ ULong arg1, ULong arg2 )
+{
+ ULong tem, flag;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "bextr %2, %3, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ *flags = flag & 0x8d5;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "bextr %2, %3, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg1), "m" (arg2) : "cc"
+ );
+ if (*res != tem || *flags != (flag & 0x8d5))
+ printf ("Difference between r and m variants\n");
+}
+
+__attribute__((noinline))
+void do_bextr32 ( /*OUT*/UInt* flags, /*OUT*/ULong* res,
+ UInt arg1, UInt arg2 )
+{
+ ULong tem, flag;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "bextr %2, %3, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ *flags = flag & 0x8d5;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "bextr %2, %3, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg1), "m" (arg2) : "cc"
+ );
+ if (*res != tem || *flags != (flag & 0x8d5))
+ printf ("Difference between r and m variants\n");
+}
+
+
+__attribute__((noinline))
+void do_bzhi64 ( /*OUT*/UInt* flags, /*OUT*/ULong* res,
+ ULong arg1, ULong arg2 )
+{
+ ULong tem, flag;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "bzhi %2, %3, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ *flags = flag & 0x8d5;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "bzhi %2, %3, %0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg1), "m" (arg2) : "cc"
+ );
+ if (*res != tem || *flags != (flag & 0x8d5))
+ printf ("Difference between r and m variants\n");
+}
+
+__attribute__((noinline))
+void do_bzhi32 ( /*OUT*/UInt* flags, /*OUT*/ULong* res,
+ UInt arg1, UInt arg2 )
+{
+ ULong tem, flag;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "bzhi %2, %3, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ *flags = flag & 0x8d5;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "bzhi %2, %3, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "popq %1" "\n"
+ : "=&r" (tem), "=&r" (flag) : "r" (arg1), "m" (arg2) : "cc"
+ );
+ if (*res != tem || *flags != (flag & 0x8d5))
+ printf ("Difference between r and m variants\n");
+}
+
+
+__attribute__((noinline))
+void do_pdep64 ( /*OUT*/ULong* res, ULong arg1, ULong arg2 )
+{
+ ULong tem, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "pdep %3, %4, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag1), "=r" (flag2)
+ : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "pdep %3, %4, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag3), "=r" (flag4)
+ : "m" (arg1), "r" (arg2) : "cc"
+ );
+ if (*res != tem)
+ printf ("Difference between r and m variants\n");
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+__attribute__((noinline))
+void do_pdep32 ( /*OUT*/ULong* res, UInt arg1, UInt arg2 )
+{
+ ULong tem, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "pdep %3, %4, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag1), "=r" (flag2)
+ : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "pdep %3, %4, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag3), "=r" (flag4)
+ : "m" (arg1), "r" (arg2) : "cc"
+ );
+ if (*res != tem)
+ printf ("Difference between r and m variants\n");
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+
+__attribute__((noinline))
+void do_pext64 ( /*OUT*/ULong* res, ULong arg1, ULong arg2 )
+{
+ ULong tem, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "pext %3, %4, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag1), "=r" (flag2)
+ : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "pext %3, %4, %0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag3), "=r" (flag4)
+ : "m" (arg1), "r" (arg2) : "cc"
+ );
+ if (*res != tem)
+ printf ("Difference between r and m variants\n");
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+__attribute__((noinline))
+void do_pext32 ( /*OUT*/ULong* res, UInt arg1, UInt arg2 )
+{
+ ULong tem, flag1, flag2, flag3, flag4;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "pext %3, %4, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag1), "=r" (flag2)
+ : "r" (arg1), "r" (arg2) : "cc"
+ );
+ *res = tem;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %0" "\n\t"
+ "pushfq" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "movq (%%rsp), %1" "\n\t"
+ "popfq" "\n\t"
+ "pext %3, %4, %k0" "\n\t"
+ "pushfq" "\n\t"
+ "movq (%%rsp), %2" "\n\t"
+ "xorq $0x8d5, (%%rsp)" "\n\t"
+ "popfq" "\n"
+ : "=&r" (tem), "=&r" (flag3), "=r" (flag4)
+ : "m" (arg1), "r" (arg2) : "cc"
+ );
+ if (*res != tem)
+ printf ("Difference between r and m variants\n");
+ if (((flag1 ^ flag2) | (flag3 ^ flag4)) & 0x8d5)
+ printf ("Flags changed\n");
+}
+
+
+int main ( void )
+{
+ ULong w1, w2;
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_andn64(&flags, &res, w1, w2);
+ printf("andn64 %016llx %016llx -> %016llx %04x\n", w1, w2, res, flags);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_andn32(&flags, &res, w1, w2);
+ printf("andn32 %016llx %016llx -> %016llx %04x\n", w1, w2, res, flags);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res1, res2;
+ do_mulx64(&res1, &res2, w1, w2);
+ printf("mulx64 %016llx %016llx -> %016llx %016llx\n", w1, w2, res1, res2);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res1, res2;
+ do_mulx32(&res1, &res2, w1, w2);
+ printf("mulx32 %016llx %016llx -> %016llx %016llx\n", w1, w2, res1, res2);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ do_sarx64(&res, w1, w2);
+ printf("sarx64 %016llx %016llx -> %016llx\n", w1, w2, res);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ do_sarx32(&res, w1, w2);
+ printf("sarx32 %016llx %016llx -> %016llx\n", w1, w2, res);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ do_shlx64(&res, w1, w2);
+ printf("shlx64 %016llx %016llx -> %016llx\n", w1, w2, res);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ do_shlx32(&res, w1, w2);
+ printf("shlx32 %016llx %016llx -> %016llx\n", w1, w2, res);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ do_shrx64(&res, w1, w2);
+ printf("shrx64 %016llx %016llx -> %016llx\n", w1, w2, res);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ do_shrx32(&res, w1, w2);
+ printf("shrx32 %016llx %016llx -> %016llx\n", w1, w2, res);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res1, res2;
+ do_rorx64(&res1, &res2, w1);
+ printf("rorx64 %016llx -> %016llx %016llx\n", w1, res1, res2);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res1, res2;
+ do_rorx32(&res1, &res2, w1);
+ printf("rorx32 %016llx -> %016llx %016llx\n", w1, res1, res2);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_blsi64(&flags, &res, w1);
+ printf("blsi64 %016llx -> %016llx %04x\n", w1, res, flags);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_blsi32(&flags, &res, w1);
+ printf("blsi32 %016llx -> %016llx %04x\n", w1, res, flags);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_blsmsk64(&flags, &res, w1);
+ printf("blsmsk64 %016llx -> %016llx %04x\n", w1, res, flags);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_blsmsk32(&flags, &res, w1);
+ printf("blsmsk32 %016llx -> %016llx %04x\n", w1, res, flags);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_blsr64(&flags, &res, w1);
+ printf("blsr64 %016llx -> %016llx %04x\n", w1, res, flags);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_blsr32(&flags, &res, w1);
+ printf("blsr32 %016llx -> %016llx %04x\n", w1, res, flags);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_bextr64(&flags, &res, w1, w2);
+ printf("bextr64 %016llx %016llx -> %016llx %04x\n", w1, w2, res, flags);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_bextr32(&flags, &res, w1, w2);
+ printf("bextr32 %016llx %016llx -> %016llx %04x\n", w1, w2, res, flags);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_bzhi64(&flags, &res, w1, w2);
+ printf("bzhi64 %016llx %016llx -> %016llx %04x\n", w1, w2, res, flags);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_bzhi32(&flags, &res, w1, w2);
+ printf("bzhi32 %016llx %016llx -> %016llx %04x\n", w1, w2, res, flags);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ do_pdep64(&res, w1, w2);
+ printf("pdep64 %016llx %016llx -> %016llx\n", w1, w2, res);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ do_pdep32(&res, w1, w2);
+ printf("pdep32 %016llx %016llx -> %016llx\n", w1, w2, res);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ do_pext64(&res, w1, w2);
+ printf("pext64 %016llx %016llx -> %016llx\n", w1, w2, res);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ w1 = 0xFEDC192837475675ULL;
+ w2 = 0x57657438291CDEF0ULL;
+ while (1) {
+ ULong res;
+ do_pext32(&res, w1, w2);
+ printf("pext32 %016llx %016llx -> %016llx\n", w1, w2, res);
+ if (w1 == 0) break;
+ w1 = ((w1 >> 2) | (w1 >> 1)) + (w1 / 17ULL);
+ w2 = ((w2 >> 2) | (w2 >> 1)) + (w2 / 17ULL);
+ }
+
+ return 0;
+}
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/bmi.stdout.exp valgrind-3.8.0.new/none/tests/amd64/bmi.stdout.exp
--- valgrind-3.8.0.orig/none/tests/amd64/bmi.stdout.exp 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/none/tests/amd64/bmi.stdout.exp 2012-09-13 11:19:25.189050665 +0200
@@ -0,0 +1,3250 @@
+andn64 fedc192837475675 57657438291cdef0 -> a898090016430005 0080
+andn64 8efcf23ad7e922f3 452015034e67c955 -> 8adce238918822a2 0080
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+pdep32 0000000000007026 00000000000037d9 -> 0000000000003002
+pdep32 00000000000042b3 0000000000002347 -> 0000000000004013
+pdep32 00000000000035e9 0000000000001c06 -> 0000000000000028
+pdep32 0000000000002329 00000000000010a9 -> 0000000000002101
+pdep32 0000000000001bef 0000000000000d78 -> 00000000000012e8
+pdep32 00000000000011a3 00000000000008c8 -> 0000000000000080
+pdep32 0000000000000e02 00000000000006fa -> 0000000000000a00
+pdep32 0000000000000853 0000000000000468 -> 0000000000000040
+pdep32 00000000000006ba 0000000000000380 -> 0000000000000000
+pdep32 0000000000000464 0000000000000214 -> 0000000000000040
+pdep32 000000000000037d 00000000000001ae -> 000000000000025c
+pdep32 0000000000000233 0000000000000118 -> 0000000000000220
+pdep32 00000000000001be 00000000000000de -> 000000000000013c
+pdep32 0000000000000119 000000000000008c -> 0000000000000110
+pdep32 00000000000000de 000000000000006f -> 000000000000009e
+pdep32 000000000000008c 0000000000000045 -> 0000000000000084
+pdep32 000000000000006f 0000000000000037 -> 0000000000000067
+pdep32 0000000000000045 0000000000000022 -> 0000000000000004
+pdep32 0000000000000037 000000000000001b -> 0000000000000033
+pdep32 0000000000000022 0000000000000010 -> 0000000000000000
+pdep32 000000000000001b 000000000000000c -> 0000000000000018
+pdep32 0000000000000010 0000000000000007 -> 0000000000000010
+pdep32 000000000000000c 0000000000000003 -> 000000000000000c
+pdep32 0000000000000007 0000000000000001 -> 0000000000000001
+pdep32 0000000000000003 0000000000000000 -> 0000000000000000
+pdep32 0000000000000001 0000000000000000 -> 0000000000000000
+pdep32 0000000000000000 0000000000000000 -> 0000000000000000
+pext64 fedc192837475675 57657438291cdef0 -> 00000002b4ce29fc
+pext64 8efcf23ad7e922f3 452015034e67c955 -> 00000008810acd15
+pext64 7068b90cdf850938 37e901ef56b302d6 -> 0000000007c3b6a2
+pext64 42db3e5ed85503a5 2348b20e142667cf -> 0000000054c9c8bb
+pext64 35eea72efbea67d7 1c09d34c26e1c212 -> 000001849b12e48a
+pext64 232c23d3b476ef47 10ad37922d51847f -> 000000007f65a44f
+pext64 1bf0c1bf27fbb3ab 0d7b015093984564 -> 0000002b92073028
+pext64 11a1311a29a562ea 08cac1103a60926a -> 000000000086642f
+pext64 0e02582b8350ffd0 06fc5681c8cd2b10 -> 0000000003619159
+pext64 0854b4408f5b9e17 04687224d51a87fa -> 0000000004655d3a
+pext64 06bcf33434328063 03809eacb986283a -> 000000000309ae26
+pext64 0464f596e5f3ab8a 02152e09a7eb825e -> 000000002505fb93
+pext64 037dac8063df281c 01af3c969c7725a6 -> 000000000aef06f1
+pext64 0234910d6d0cfe89 01193d5aad28c013 -> 000000000138fb01
+pext64 01c0a27d7eaa2575 00df6b2373776c4a -> 000000001b4795d0
+pext64 010adda943af43d8 008d24457d4341d1 -> 000000000821a1de
+pext64 00d7b2ae8c91c8ce 007028a17fc8b89e -> 000000000c261cb7
+pext64 008cae284a0c2065 0042b77370e42ef0 -> 000000000001ba3c
+pext64 006fc6190eb4fc04 0035ecaa6c888c28 -> 0000000002bcb446
+pext64 004686bd6e829ce5 00232b89c5c8c9b6 -> 0000000002659556
+pext64 00380a0b248034f1 001bf185a53e82dc -> 0000000000030e1a
+pext64 0021536a650d4fc6 0011a1af9c2edaa2 -> 0000000001172da9
+pext64 001af3d8d0c8c068 000e0282bc13b27b -> 0000000000614517
+pext64 001193de10460316 000854daa0b4cc02 -> 0000000000027a41
+pext64 000df6b241dd45c1 0006bcf63e2fbf3d -> 0000000002bbc1d9
+pext64 0008d24469947f91 000464f7852a566a -> 00000000002622b0
+pext64 0007028a17f7fc21 00037dac915ab5c5 -> 0000000001b4aab5
+pext64 00042b77370e9574 000234911b32831c -> 0000000002095993
+pext64 00035ecaa6c8cb9c 0001c0a2862c25c1 -> 000000000309b218
+pext64 000232b89c5ca207 00010addcd657882 -> 000000000006ee52
+pext64 0001bf185a53fb83 0000d7b2a9b6ab1d -> 0000000005789ab9
+pext64 00011a1af9c2f08e 00008cae2719cda3 -> 00000000002648c9
+pext64 0000e0282bc137ba 00006fc61694404d -> 0000000000185002
+pext64 0000854daa0b4caf 00004686be70612c -> 000000000022f11c
+pext64 00006bcf63e2fc01 0000380a0af0025a -> 0000000001851700
+pext64 0000464f7852a469 000021536a829879 -> 000000000004f4cf
+pext64 000037dac915aa8f 00001af3d8f8abea -> 00000000015de9fa
+pext64 0000234911b3280d 00001193de14a839 -> 000000000000989d
+pext64 00001c0a2862c244 00000df6b24569e5 -> 000000000000368b
+pext64 000010addcd6577a 000008d2446cc8f9 -> 000000000104aa1e
+pext64 00000d7b2a9b6ac9 000007028a18af7d -> 0000000000c26c77
+pext64 000008cae2719cd4 0000042b77359960 -> 00000000000377e4
+pext64 000006fc61694403 0000035ecaa6d9df -> 000000000002bc4b
+pext64 000004686be70610 00000232b89c662a -> 0000000000009926
+pext64 00000380a0af0023 000001bf185a50b0 -> 0000000000001854
+pext64 0000021536a82984 0000011a1af9c13b -> 00000000000045e4
+pext64 000001af3d8f8abd 000000e0282bc000 -> 0000000001851700
+pext64 000001193de14a82 000000854daa0a5a -> 0000000000004f4d
+pext64 000000df6b24569d 0000006bcf63e2b5 -> 00000000002bbd3b
+pext64 0000008d2446cc8e 000000464f7852a0 -> 0000000000004c48
+pext64 0000007028a18af6 00000037dac915a7 -> 000000000000da2b
+pext64 00000042b7735995 000000234911b322 -> 0000000000082550
+pext64 00000035ecaa6d9d 0000001c0a2862bc -> 0000000000309b1e
+pext64 000000232b89c661 00000010addcd664 -> 000000000000377e
+pext64 0000001bf185a509 0000000d7b2a9b66 -> 0000000000015e24
+pext64 00000011a1af9c11 00000008cae27197 -> 0000000000004c93
+pext64 0000000e0282bbfd 00000006fc616943 -> 0000000000030aa1
+pext64 0000000854daa1a4 00000004686be704 -> 00000000000022f9
+pext64 00000006bcf63eb9 0000000380a0aeff -> 000000000030a2ff
+pext64 0000000464f78590 000000021536a868 -> 00000000000013d0
+pext64 000000037dac916c 00000001af3d8fad -> 000000000002bbd7
+pext64 0000000234911b32 00000001193de163 -> 000000000000098d
+pext64 00000001c0a2862b 00000000df6b2459 -> 0000000000000da5
+pext64 000000010addcd65 000000008d2446ca -> 00000000000104a8
+pext64 00000000d7b2a9b5 000000007028a18a -> 00000000000309b0
+pext64 000000008cae2718 0000000042b77358 -> 00000000000006ef
+pext64 000000006fc61693 0000000035ecaa6c -> 000000000000af10
+pext64 000000004686be6e 00000000232b89c5 -> 0000000000004c92
+pext64 00000000380a0af2 000000001bf185a4 -> 0000000000000614
+pext64 0000000021536a83 0000000011a1af9b -> 00000000000008bf
+pext64 000000001af3d8f7 000000000e0282bb -> 000000000006145b
+pext64 000000001193de15 000000000854daa0 -> 00000000000009e8
+pext64 000000000df6b244 0000000006bcf63d -> 0000000000002bbd
+pext64 0000000008d2446b 000000000464f784 -> 0000000000000260
+pext64 0000000007028a18 00000000037dac90 -> 00000000000000da
+pext64 00000000042b7735 000000000234911a -> 0000000000002094
+pext64 00000000035ecaa5 0000000001c0a285 -> 000000000000309b
+pext64 000000000232b89b 00000000010addcc -> 0000000000000374
+pext64 0000000001bf185a 0000000000d7b2a8 -> 00000000000015e2
+pext64 00000000011a1af9 00000000008cae26 -> 00000000000004c8
+pext64 0000000000e0282a 00000000006fc615 -> 0000000000000060
+pext64 0000000000854da9 00000000004686bd -> 000000000000022f
+pext64 00000000006bcf62 0000000000380a0a -> 0000000000001851
+pext64 0000000000464f77 0000000000215369 -> 00000000000004f1
+pext64 000000000037dac9 00000000001af3d7 -> 00000000000015dd
+pext64 0000000000234910 00000000001193de -> 0000000000000013
+pext64 00000000001c0a27 00000000000df6b1 -> 00000000000000d9
+pext64 000000000010add9 000000000008d242 -> 0000000000000208
+pext64 00000000000d7b28 0000000000070287 -> 0000000000000308
+pext64 000000000008cae0 0000000000042b72 -> 000000000000001b
+pext64 000000000006fc5f 0000000000035ec7 -> 00000000000015e7
+pext64 0000000000046871 00000000000232b3 -> 0000000000000027
+pext64 000000000003809d 000000000001bf16 -> 000000000000006a
+pext64 000000000002152c 0000000000011a1b -> 0000000000000022
+pext64 000000000001af3b 000000000000e027 -> 0000000000000613
+pext64 000000000001193c 000000000000854a -> 0000000000000012
+pext64 000000000000df6a 0000000000006bce -> 00000000000002bb
+pext64 0000000000008d23 000000000000464e -> 0000000000000012
+pext64 0000000000007026 00000000000037d9 -> 0000000000000018
+pext64 00000000000042b3 0000000000002347 -> 0000000000000023
+pext64 00000000000035e9 0000000000001c06 -> 00000000000000c0
+pext64 0000000000002329 00000000000010a9 -> 0000000000000007
+pext64 0000000000001bef 0000000000000d78 -> 00000000000002b8
+pext64 00000000000011a3 00000000000008c8 -> 0000000000000008
+pext64 0000000000000e02 00000000000006fa -> 0000000000000007
+pext64 0000000000000853 0000000000000468 -> 0000000000000008
+pext64 00000000000006ba 0000000000000380 -> 0000000000000030
+pext64 0000000000000464 0000000000000214 -> 0000000000000001
+pext64 000000000000037d 00000000000001ae -> 0000000000000056
+pext64 0000000000000233 0000000000000118 -> 0000000000000004
+pext64 00000000000001be 00000000000000de -> 000000000000002f
+pext64 0000000000000119 000000000000008c -> 0000000000000002
+pext64 00000000000000de 000000000000006f -> 0000000000000017
+pext64 000000000000008c 0000000000000045 -> 0000000000000001
+pext64 000000000000006f 0000000000000037 -> 0000000000000017
+pext64 0000000000000045 0000000000000022 -> 0000000000000000
+pext64 0000000000000037 000000000000001b -> 000000000000000b
+pext64 0000000000000022 0000000000000010 -> 0000000000000000
+pext64 000000000000001b 000000000000000c -> 0000000000000004
+pext64 0000000000000010 0000000000000007 -> 0000000000000000
+pext64 000000000000000c 0000000000000003 -> 0000000000000000
+pext64 0000000000000007 0000000000000001 -> 0000000000000001
+pext64 0000000000000003 0000000000000000 -> 0000000000000000
+pext64 0000000000000001 0000000000000000 -> 0000000000000000
+pext64 0000000000000000 0000000000000000 -> 0000000000000000
+pext32 fedc192837475675 57657438291cdef0 -> 00000000000229fc
+pext32 8efcf23ad7e922f3 452015034e67c955 -> 000000000002cd15
+pext32 7068b90cdf850938 37e901ef56b302d6 -> 00000000000036a2
+pext32 42db3e5ed85503a5 2348b20e142667cf -> 00000000000008bb
+pext32 35eea72efbea67d7 1c09d34c26e1c212 -> 000000000012e48a
+pext32 232c23d3b476ef47 10ad37922d51847f -> 000000000005a44f
+pext32 1bf0c1bf27fbb3ab 0d7b015093984564 -> 0000000000073028
+pext32 11a1311a29a562ea 08cac1103a60926a -> 000000000000642f
+pext32 0e02582b8350ffd0 06fc5681c8cd2b10 -> 0000000000009159
+pext32 0854b4408f5b9e17 04687224d51a87fa -> 0000000000055d3a
+pext32 06bcf33434328063 03809eacb986283a -> 0000000000000626
+pext32 0464f596e5f3ab8a 02152e09a7eb825e -> 000000000005fb93
+pext32 037dac8063df281c 01af3c969c7725a6 -> 00000000000006f1
+pext32 0234910d6d0cfe89 01193d5aad28c013 -> 000000000000fb01
+pext32 01c0a27d7eaa2575 00df6b2373776c4a -> 00000000000395d0
+pext32 010adda943af43d8 008d24457d4341d1 -> 000000000000a1de
+pext32 00d7b2ae8c91c8ce 007028a17fc8b89e -> 0000000000001cb7
+pext32 008cae284a0c2065 0042b77370e42ef0 -> 000000000000023c
+pext32 006fc6190eb4fc04 0035ecaa6c888c28 -> 0000000000003446
+pext32 004686bd6e829ce5 00232b89c5c8c9b6 -> 0000000000009556
+pext32 00380a0b248034f1 001bf185a53e82dc -> 000000000000061a
+pext32 0021536a650d4fc6 0011a1af9c2edaa2 -> 0000000000002da9
+pext32 001af3d8d0c8c068 000e0282bc13b27b -> 0000000000000517
+pext32 001193de10460316 000854daa0b4cc02 -> 0000000000000041
+pext32 000df6b241dd45c1 0006bcf63e2fbf3d -> 00000000000001d9
+pext32 0008d24469947f91 000464f7852a566a -> 00000000000022b0
+pext32 0007028a17f7fc21 00037dac915ab5c5 -> 000000000004aab5
+pext32 00042b77370e9574 000234911b32831c -> 0000000000005993
+pext32 00035ecaa6c8cb9c 0001c0a2862c25c1 -> 000000000000b218
+pext32 000232b89c5ca207 00010addcd657882 -> 0000000000002e52
+pext32 0001bf185a53fb83 0000d7b2a9b6ab1d -> 0000000000009ab9
+pext32 00011a1af9c2f08e 00008cae2719cda3 -> 00000000000048c9
+pext32 0000e0282bc137ba 00006fc61694404d -> 0000000000005002
+pext32 0000854daa0b4caf 00004686be70612c -> 000000000000f11c
+pext32 00006bcf63e2fc01 0000380a0af0025a -> 0000000000001700
+pext32 0000464f7852a469 000021536a829879 -> 00000000000034cf
+pext32 000037dac915aa8f 00001af3d8f8abea -> 000000000000e9fa
+pext32 0000234911b3280d 00001193de14a839 -> 000000000000089d
+pext32 00001c0a2862c244 00000df6b24569e5 -> 000000000000028b
+pext32 000010addcd6577a 000008d2446cc8f9 -> 000000000004aa1e
+pext32 00000d7b2a9b6ac9 000007028a18af7d -> 0000000000006c77
+pext32 000008cae2719cd4 0000042b77359960 -> 00000000000077e4
+pext32 000006fc61694403 0000035ecaa6d9df -> 000000000000044b
+pext32 000004686be70610 00000232b89c662a -> 0000000000001926
+pext32 00000380a0af0023 000001bf185a50b0 -> 0000000000000054
+pext32 0000021536a82984 0000011a1af9c13b -> 00000000000005e4
+pext32 000001af3d8f8abd 000000e0282bc000 -> 0000000000051700
+pext32 000001193de14a82 000000854daa0a5a -> 0000000000000f4d
+pext32 000000df6b24569d 0000006bcf63e2b5 -> 000000000000bd3b
+pext32 0000008d2446cc8e 000000464f7852a0 -> 0000000000000c48
+pext32 0000007028a18af6 00000037dac915a7 -> 0000000000001a2b
+pext32 00000042b7735995 000000234911b322 -> 0000000000002550
+pext32 00000035ecaa6d9d 0000001c0a2862bc -> 0000000000009b1e
+pext32 000000232b89c661 00000010addcd664 -> 000000000000377e
+pext32 0000001bf185a509 0000000d7b2a9b66 -> 0000000000001e24
+pext32 00000011a1af9c11 00000008cae27197 -> 0000000000004c93
+pext32 0000000e0282bbfd 00000006fc616943 -> 0000000000000aa1
+pext32 0000000854daa1a4 00000004686be704 -> 00000000000022f9
+pext32 00000006bcf63eb9 0000000380a0aeff -> 000000000010a2ff
+pext32 0000000464f78590 000000021536a868 -> 00000000000013d0
+pext32 000000037dac916c 00000001af3d8fad -> 000000000000bbd7
+pext32 0000000234911b32 00000001193de163 -> 000000000000098d
+pext32 00000001c0a2862b 00000000df6b2459 -> 0000000000000da5
+pext32 000000010addcd65 000000008d2446ca -> 00000000000104a8
+pext32 00000000d7b2a9b5 000000007028a18a -> 00000000000309b0
+pext32 000000008cae2718 0000000042b77358 -> 00000000000006ef
+pext32 000000006fc61693 0000000035ecaa6c -> 000000000000af10
+pext32 000000004686be6e 00000000232b89c5 -> 0000000000004c92
+pext32 00000000380a0af2 000000001bf185a4 -> 0000000000000614
+pext32 0000000021536a83 0000000011a1af9b -> 00000000000008bf
+pext32 000000001af3d8f7 000000000e0282bb -> 000000000006145b
+pext32 000000001193de15 000000000854daa0 -> 00000000000009e8
+pext32 000000000df6b244 0000000006bcf63d -> 0000000000002bbd
+pext32 0000000008d2446b 000000000464f784 -> 0000000000000260
+pext32 0000000007028a18 00000000037dac90 -> 00000000000000da
+pext32 00000000042b7735 000000000234911a -> 0000000000002094
+pext32 00000000035ecaa5 0000000001c0a285 -> 000000000000309b
+pext32 000000000232b89b 00000000010addcc -> 0000000000000374
+pext32 0000000001bf185a 0000000000d7b2a8 -> 00000000000015e2
+pext32 00000000011a1af9 00000000008cae26 -> 00000000000004c8
+pext32 0000000000e0282a 00000000006fc615 -> 0000000000000060
+pext32 0000000000854da9 00000000004686bd -> 000000000000022f
+pext32 00000000006bcf62 0000000000380a0a -> 0000000000001851
+pext32 0000000000464f77 0000000000215369 -> 00000000000004f1
+pext32 000000000037dac9 00000000001af3d7 -> 00000000000015dd
+pext32 0000000000234910 00000000001193de -> 0000000000000013
+pext32 00000000001c0a27 00000000000df6b1 -> 00000000000000d9
+pext32 000000000010add9 000000000008d242 -> 0000000000000208
+pext32 00000000000d7b28 0000000000070287 -> 0000000000000308
+pext32 000000000008cae0 0000000000042b72 -> 000000000000001b
+pext32 000000000006fc5f 0000000000035ec7 -> 00000000000015e7
+pext32 0000000000046871 00000000000232b3 -> 0000000000000027
+pext32 000000000003809d 000000000001bf16 -> 000000000000006a
+pext32 000000000002152c 0000000000011a1b -> 0000000000000022
+pext32 000000000001af3b 000000000000e027 -> 0000000000000613
+pext32 000000000001193c 000000000000854a -> 0000000000000012
+pext32 000000000000df6a 0000000000006bce -> 00000000000002bb
+pext32 0000000000008d23 000000000000464e -> 0000000000000012
+pext32 0000000000007026 00000000000037d9 -> 0000000000000018
+pext32 00000000000042b3 0000000000002347 -> 0000000000000023
+pext32 00000000000035e9 0000000000001c06 -> 00000000000000c0
+pext32 0000000000002329 00000000000010a9 -> 0000000000000007
+pext32 0000000000001bef 0000000000000d78 -> 00000000000002b8
+pext32 00000000000011a3 00000000000008c8 -> 0000000000000008
+pext32 0000000000000e02 00000000000006fa -> 0000000000000007
+pext32 0000000000000853 0000000000000468 -> 0000000000000008
+pext32 00000000000006ba 0000000000000380 -> 0000000000000030
+pext32 0000000000000464 0000000000000214 -> 0000000000000001
+pext32 000000000000037d 00000000000001ae -> 0000000000000056
+pext32 0000000000000233 0000000000000118 -> 0000000000000004
+pext32 00000000000001be 00000000000000de -> 000000000000002f
+pext32 0000000000000119 000000000000008c -> 0000000000000002
+pext32 00000000000000de 000000000000006f -> 0000000000000017
+pext32 000000000000008c 0000000000000045 -> 0000000000000001
+pext32 000000000000006f 0000000000000037 -> 0000000000000017
+pext32 0000000000000045 0000000000000022 -> 0000000000000000
+pext32 0000000000000037 000000000000001b -> 000000000000000b
+pext32 0000000000000022 0000000000000010 -> 0000000000000000
+pext32 000000000000001b 000000000000000c -> 0000000000000004
+pext32 0000000000000010 0000000000000007 -> 0000000000000000
+pext32 000000000000000c 0000000000000003 -> 0000000000000000
+pext32 0000000000000007 0000000000000001 -> 0000000000000001
+pext32 0000000000000003 0000000000000000 -> 0000000000000000
+pext32 0000000000000001 0000000000000000 -> 0000000000000000
+pext32 0000000000000000 0000000000000000 -> 0000000000000000
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/bmi.vgtest valgrind-3.8.0.new/none/tests/amd64/bmi.vgtest
--- valgrind-3.8.0.orig/none/tests/amd64/bmi.vgtest 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/none/tests/amd64/bmi.vgtest 2012-09-13 11:19:25.189050665 +0200
@@ -0,0 +1,3 @@
+prog: bmi
+prereq: ../../../tests/x86_amd64_features amd64-avx
+vgopts: -q
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/fma.c valgrind-3.8.0.new/none/tests/amd64/fma.c
--- valgrind-3.8.0.orig/none/tests/amd64/fma.c 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/none/tests/amd64/fma.c 2012-09-12 19:54:55.783334625 +0200
@@ -0,0 +1,1431 @@
+#include <stdio.h>
+#include <string.h>
+
+#define N 64
+struct float_test {
+ float x[N], y[N], z[N], expected[N], res[N];
+} ft __attribute__((aligned (32)));
+
+struct double_test {
+ double x[N], y[N], z[N], expected[N], res[N];
+} dt __attribute__((aligned (32)));
+
+float plus_zero, plus_infty, minus_infty, nan_value;
+
+static int testf( float x, float y )
+{
+ unsigned int a, b;
+ memcpy( &a, &x, sizeof (a) );
+ memcpy( &b, &y, sizeof (b) );
+ if ((a & 0x7fc00000U) == 0x7fc00000U)
+ return (b & 0x7fc00000U) != 0x7fc00000U;
+ return memcmp( &a, &b, sizeof (a) ) != 0;
+}
+
+static int test_fmaf( void )
+{
+ int res = 0, i, j;
+ float w;
+ for (i = 0; i < N; i++) {
+ int thisres = 0;
+ __asm __volatile__ ("vfmadd132ss %2, %3, %0" : "=x" (w) : "0" (ft.x[i]), "x" (ft.y[i]), "x" (ft.z[i]));
+ thisres |= testf( w, ft.expected[i] );
+ __asm __volatile__ ("vfmadd132ss %2, %3, %0" : "=x" (w) : "0" (ft.x[i]), "m" (ft.y[i]), "x" (ft.z[i]));
+ thisres |= testf( w, ft.expected[i] );
+ __asm __volatile__ ("vfmadd213ss %3, %2, %0" : "=x" (w) : "0" (ft.x[i]), "x" (ft.y[i]), "x" (ft.z[i]));
+ thisres |= testf( w, ft.expected[i] );
+ __asm __volatile__ ("vfmadd213ss %3, %2, %0" : "=x" (w) : "0" (ft.x[i]), "x" (ft.y[i]), "m" (ft.z[i]));
+ thisres |= testf( w, ft.expected[i] );
+ __asm __volatile__ ("vfmadd231ss %2, %1, %0" : "=x" (w) : "x" (ft.x[i]), "x" (ft.y[i]), "0" (ft.z[i]));
+ thisres |= testf( w, ft.expected[i] );
+ __asm __volatile__ ("vfmadd231ss %2, %1, %0" : "=x" (w) : "x" (ft.x[i]), "m" (ft.y[i]), "0" (ft.z[i]));
+ thisres |= testf( w, ft.expected[i] );
+ if (thisres)
+ printf( "Failure 1 %d %a %a\n", i, w, ft.expected[i] );
+ res |= thisres;
+ thisres = 0;
+ __asm __volatile__ ("vfnmsub132ss %2, %3, %0" : "=x" (w) : "0" (ft.x[i]), "x" (ft.y[i]), "x" (ft.z[i]));
+ thisres |= testf( -w, ft.expected[i] );
+ __asm __volatile__ ("vfnmsub132ss %2, %3, %0" : "=x" (w) : "0" (ft.x[i]), "m" (ft.y[i]), "x" (ft.z[i]));
+ thisres |= testf( -w, ft.expected[i] );
+ __asm __volatile__ ("vfnmsub213ss %3, %2, %0" : "=x" (w) : "0" (ft.x[i]), "x" (ft.y[i]), "x" (ft.z[i]));
+ thisres |= testf( -w, ft.expected[i] );
+ __asm __volatile__ ("vfnmsub213ss %3, %2, %0" : "=x" (w) : "0" (ft.x[i]), "x" (ft.y[i]), "m" (ft.z[i]));
+ thisres |= testf( -w, ft.expected[i] );
+ __asm __volatile__ ("vfnmsub231ss %2, %1, %0" : "=x" (w) : "x" (ft.x[i]), "x" (ft.y[i]), "0" (ft.z[i]));
+ thisres |= testf( -w, ft.expected[i] );
+ __asm __volatile__ ("vfnmsub231ss %2, %1, %0" : "=x" (w) : "x" (ft.x[i]), "m" (ft.y[i]), "0" (ft.z[i]));
+ thisres |= testf( -w, ft.expected[i] );
+ if (thisres)
+ printf( "Failure 2 %d %a %a\n", i, w, ft.expected[i] );
+ res |= thisres;
+ }
+ for (i = 0; i < N; i++)
+ ft.z[i] = -ft.z[i];
+ for (i = 0; i < N; i++) {
+ int thisres = 0;
+ __asm __volatile__ ("vfmsub132ss %2, %3, %0" : "=x" (w) : "0" (ft.x[i]), "x" (ft.y[i]), "x" (ft.z[i]));
+ thisres |= testf( w, ft.expected[i] );
+ __asm __volatile__ ("vfmsub132ss %2, %3, %0" : "=x" (w) : "0" (ft.x[i]), "m" (ft.y[i]), "x" (ft.z[i]));
+ thisres |= testf( w, ft.expected[i] );
+ __asm __volatile__ ("vfmsub213ss %3, %2, %0" : "=x" (w) : "0" (ft.x[i]), "x" (ft.y[i]), "x" (ft.z[i]));
+ thisres |= testf( w, ft.expected[i] );
+ __asm __volatile__ ("vfmsub213ss %3, %2, %0" : "=x" (w) : "0" (ft.x[i]), "x" (ft.y[i]), "m" (ft.z[i]));
+ thisres |= testf( w, ft.expected[i] );
+ __asm __volatile__ ("vfmsub231ss %2, %1, %0" : "=x" (w) : "x" (ft.x[i]), "x" (ft.y[i]), "0" (ft.z[i]));
+ thisres |= testf( w, ft.expected[i] );
+ __asm __volatile__ ("vfmsub231ss %2, %1, %0" : "=x" (w) : "x" (ft.x[i]), "m" (ft.y[i]), "0" (ft.z[i]));
+ thisres |= testf( w, ft.expected[i] );
+ if (thisres)
+ printf( "Failure 3 %d %a %a\n", i, w, ft.expected[i] );
+ res |= thisres;
+ thisres = 0;
+ __asm __volatile__ ("vfnmadd132ss %2, %3, %0" : "=x" (w) : "0" (ft.x[i]), "x" (ft.y[i]), "x" (ft.z[i]));
+ thisres |= testf( -w, ft.expected[i] );
+ __asm __volatile__ ("vfnmadd132ss %2, %3, %0" : "=x" (w) : "0" (ft.x[i]), "m" (ft.y[i]), "x" (ft.z[i]));
+ thisres |= testf( -w, ft.expected[i] );
+ __asm __volatile__ ("vfnmadd213ss %3, %2, %0" : "=x" (w) : "0" (ft.x[i]), "x" (ft.y[i]), "x" (ft.z[i]));
+ thisres |= testf( -w, ft.expected[i] );
+ __asm __volatile__ ("vfnmadd213ss %3, %2, %0" : "=x" (w) : "0" (ft.x[i]), "x" (ft.y[i]), "m" (ft.z[i]));
+ thisres |= testf( -w, ft.expected[i] );
+ __asm __volatile__ ("vfnmadd231ss %2, %1, %0" : "=x" (w) : "x" (ft.x[i]), "x" (ft.y[i]), "0" (ft.z[i]));
+ thisres |= testf( -w, ft.expected[i] );
+ __asm __volatile__ ("vfnmadd231ss %2, %1, %0" : "=x" (w) : "x" (ft.x[i]), "m" (ft.y[i]), "0" (ft.z[i]));
+ thisres |= testf( -w, ft.expected[i] );
+ if (thisres)
+ printf( "Failure 4 %d %a %a\n", i, w, ft.expected[i] );
+ res |= thisres;
+ }
+ for (i = 0; i < N; i++)
+ ft.z[i] = -ft.z[i];
+ for (i = 0; i < N; i += 4) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%2), %%xmm7; vmovaps (%3), %%xmm8;"
+ "vfmadd132ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%3), %%xmm8;"
+ "vfmadd132ps (%2), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%3), %%xmm7; vmovaps (%2), %%xmm8;"
+ "vfmadd213ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%2), %%xmm8;"
+ "vfmadd213ps (%3), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%xmm9; vmovaps (%2), %%xmm7; vmovaps (%1), %%xmm8;"
+ "vfmadd231ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%xmm9; vmovaps (%1), %%xmm8;"
+ "vfmadd231ps (%2), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 5 %d", i );
+ for (j = 0; j < 4; j++)
+ printf( " %a %a", ft.res[i+j], ft.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ thisres = 0;
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%2), %%xmm7; vmovaps (%3), %%xmm8;"
+ "vfnmsub132ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%3), %%xmm8;"
+ "vfnmsub132ps (%2), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%3), %%xmm7; vmovaps (%2), %%xmm8;"
+ "vfnmsub213ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%2), %%xmm8;"
+ "vfnmsub213ps (%3), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%xmm9; vmovaps (%2), %%xmm7; vmovaps (%1), %%xmm8;"
+ "vfnmsub231ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%xmm9; vmovaps (%1), %%xmm8;"
+ "vfnmsub231ps (%2), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 6 %d", i );
+ for (j = 0; j < 4; j++)
+ printf( " %a %a", ft.res[i+j], ft.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 0; i < N; i++)
+ ft.z[i] = -ft.z[i];
+ for (i = 0; i < N; i += 4) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%2), %%xmm7; vmovaps (%3), %%xmm8;"
+ "vfmsub132ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%3), %%xmm8;"
+ "vfmsub132ps (%2), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%3), %%xmm7; vmovaps (%2), %%xmm8;"
+ "vfmsub213ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%2), %%xmm8;"
+ "vfmsub213ps (%3), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%xmm9; vmovaps (%2), %%xmm7; vmovaps (%1), %%xmm8;"
+ "vfmsub231ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%xmm9; vmovaps (%1), %%xmm8;"
+ "vfmsub231ps (%2), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 7 %d", i );
+ for (j = 0; j < 4; j++)
+ printf( " %a %a", ft.res[i+j], ft.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ thisres = 0;
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%2), %%xmm7; vmovaps (%3), %%xmm8;"
+ "vfnmadd132ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%3), %%xmm8;"
+ "vfnmadd132ps (%2), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%3), %%xmm7; vmovaps (%2), %%xmm8;"
+ "vfnmadd213ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%2), %%xmm8;"
+ "vfnmadd213ps (%3), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%xmm9; vmovaps (%2), %%xmm7; vmovaps (%1), %%xmm8;"
+ "vfnmadd231ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%xmm9; vmovaps (%1), %%xmm8;"
+ "vfnmadd231ps (%2), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 8 %d", i );
+ for (j = 0; j < 4; j++)
+ printf( " %a %a", ft.res[i+j], ft.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 1; i < N; i += 2)
+ ft.z[i] = -ft.z[i];
+ for (i = 0; i < N; i += 4) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%2), %%xmm7; vmovaps (%3), %%xmm8;"
+ "vfmaddsub132ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%3), %%xmm8;"
+ "vfmaddsub132ps (%2), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%3), %%xmm7; vmovaps (%2), %%xmm8;"
+ "vfmaddsub213ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%2), %%xmm8;"
+ "vfmaddsub213ps (%3), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%xmm9; vmovaps (%2), %%xmm7; vmovaps (%1), %%xmm8;"
+ "vfmaddsub231ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%xmm9; vmovaps (%1), %%xmm8;"
+ "vfmaddsub231ps (%2), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 9 %d", i );
+ for (j = 0; j < 4; j++)
+ printf( " %a %a", ft.res[i+j], ft.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 0; i < N; i++)
+ ft.z[i] = -ft.z[i];
+ for (i = 0; i < N; i += 4) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%2), %%xmm7; vmovaps (%3), %%xmm8;"
+ "vfmsubadd132ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%3), %%xmm8;"
+ "vfmsubadd132ps (%2), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%3), %%xmm7; vmovaps (%2), %%xmm8;"
+ "vfmsubadd213ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%xmm9; vmovaps (%2), %%xmm8;"
+ "vfmsubadd213ps (%3), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%xmm9; vmovaps (%2), %%xmm7; vmovaps (%1), %%xmm8;"
+ "vfmsubadd231ps %%xmm7, %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%xmm9; vmovaps (%1), %%xmm8;"
+ "vfmsubadd231ps (%2), %%xmm8, %%xmm9;"
+ "vmovaps %%xmm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 10 %d", i );
+ for (j = 0; j < 4; j++)
+ printf( " %a %a", ft.res[i+j], ft.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 1; i < N; i += 2)
+ ft.z[i] = -ft.z[i];
+ for (i = 0; i < N; i += 8) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%2), %%ymm7; vmovaps (%3), %%ymm8;"
+ "vfmadd132ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%3), %%ymm8;"
+ "vfmadd132ps (%2), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%3), %%ymm7; vmovaps (%2), %%ymm8;"
+ "vfmadd213ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%2), %%ymm8;"
+ "vfmadd213ps (%3), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%ymm9; vmovaps (%2), %%ymm7; vmovaps (%1), %%ymm8;"
+ "vfmadd231ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%ymm9; vmovaps (%1), %%ymm8;"
+ "vfmadd231ps (%2), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 11 %d", i );
+ for (j = 0; j < 8; j++)
+ printf( " %a %a", ft.res[i+j], ft.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ thisres = 0;
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%2), %%ymm7; vmovaps (%3), %%ymm8;"
+ "vfnmsub132ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%3), %%ymm8;"
+ "vfnmsub132ps (%2), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%3), %%ymm7; vmovaps (%2), %%ymm8;"
+ "vfnmsub213ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%2), %%ymm8;"
+ "vfnmsub213ps (%3), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%ymm9; vmovaps (%2), %%ymm7; vmovaps (%1), %%ymm8;"
+ "vfnmsub231ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%ymm9; vmovaps (%1), %%ymm8;"
+ "vfnmsub231ps (%2), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 12 %d", i );
+ for (j = 0; j < 8; j++)
+ printf( " %a %a", ft.res[i+j], ft.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 0; i < N; i++)
+ ft.z[i] = -ft.z[i];
+ for (i = 0; i < N; i += 8) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%2), %%ymm7; vmovaps (%3), %%ymm8;"
+ "vfmsub132ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%3), %%ymm8;"
+ "vfmsub132ps (%2), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%3), %%ymm7; vmovaps (%2), %%ymm8;"
+ "vfmsub213ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%2), %%ymm8;"
+ "vfmsub213ps (%3), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%ymm9; vmovaps (%2), %%ymm7; vmovaps (%1), %%ymm8;"
+ "vfmsub231ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%ymm9; vmovaps (%1), %%ymm8;"
+ "vfmsub231ps (%2), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 13 %d", i );
+ for (j = 0; j < 8; j++)
+ printf( " %a %a", ft.res[i+j], ft.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ thisres = 0;
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%2), %%ymm7; vmovaps (%3), %%ymm8;"
+ "vfnmadd132ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%3), %%ymm8;"
+ "vfnmadd132ps (%2), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%3), %%ymm7; vmovaps (%2), %%ymm8;"
+ "vfnmadd213ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%2), %%ymm8;"
+ "vfnmadd213ps (%3), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%ymm9; vmovaps (%2), %%ymm7; vmovaps (%1), %%ymm8;"
+ "vfnmadd231ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%ymm9; vmovaps (%1), %%ymm8;"
+ "vfnmadd231ps (%2), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( -ft.res[i+j], ft.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 14 %d", i );
+ for (j = 0; j < 8; j++)
+ printf( " %a %a", ft.res[i+j], ft.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 1; i < N; i += 2)
+ ft.z[i] = -ft.z[i];
+ for (i = 0; i < N; i += 8) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%2), %%ymm7; vmovaps (%3), %%ymm8;"
+ "vfmaddsub132ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%3), %%ymm8;"
+ "vfmaddsub132ps (%2), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%3), %%ymm7; vmovaps (%2), %%ymm8;"
+ "vfmaddsub213ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%2), %%ymm8;"
+ "vfmaddsub213ps (%3), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%ymm9; vmovaps (%2), %%ymm7; vmovaps (%1), %%ymm8;"
+ "vfmaddsub231ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%ymm9; vmovaps (%1), %%ymm8;"
+ "vfmaddsub231ps (%2), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 15 %d", i );
+ for (j = 0; j < 8; j++)
+ printf( " %a %a", ft.res[i+j], ft.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 0; i < N; i++)
+ ft.z[i] = -ft.z[i];
+ for (i = 0; i < N; i += 8) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%2), %%ymm7; vmovaps (%3), %%ymm8;"
+ "vfmsubadd132ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%3), %%ymm8;"
+ "vfmsubadd132ps (%2), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%3), %%ymm7; vmovaps (%2), %%ymm8;"
+ "vfmsubadd213ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%1), %%ymm9; vmovaps (%2), %%ymm8;"
+ "vfmsubadd213ps (%3), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%ymm9; vmovaps (%2), %%ymm7; vmovaps (%1), %%ymm8;"
+ "vfmsubadd231ps %%ymm7, %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ __asm __volatile__ ("vmovaps (%3), %%ymm9; vmovaps (%1), %%ymm8;"
+ "vfmsubadd231ps (%2), %%ymm8, %%ymm9;"
+ "vmovaps %%ymm9, (%0)" : : "r" (&ft.res[i]), "r" (&ft.x[i]),
+ "r" (&ft.y[i]), "r" (&ft.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 8; j++)
+ thisres |= testf( ft.res[i+j], ft.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 16 %d", i );
+ for (j = 0; j < 8; j++)
+ printf( " %a %a", ft.res[i+j], ft.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 1; i < N; i += 2)
+ ft.z[i] = -ft.z[i];
+ return res;
+}
+
+static int test( double x, double y )
+{
+ unsigned long long a, b;
+ memcpy( &a, &x, sizeof (a) );
+ memcpy( &b, &y, sizeof (b) );
+ if ((a & 0x7ff8000000000000ULL) == 0x7ff8000000000000ULL)
+ return (b & 0x7ff8000000000000ULL) != 0x7ff8000000000000ULL;
+ return memcmp( &a, &b, sizeof (a) ) != 0;
+}
+
+static int test_fma( void )
+{
+ int res = 0, i, j;
+ double w;
+ for (i = 0; i < N; i++) {
+ int thisres = 0;
+ __asm __volatile__ ("vfmadd132sd %2, %3, %0" : "=x" (w) : "0" (dt.x[i]), "x" (dt.y[i]), "x" (dt.z[i]));
+ thisres |= test( w, dt.expected[i] );
+ __asm __volatile__ ("vfmadd132sd %2, %3, %0" : "=x" (w) : "0" (dt.x[i]), "m" (dt.y[i]), "x" (dt.z[i]));
+ thisres |= test( w, dt.expected[i] );
+ __asm __volatile__ ("vfmadd213sd %3, %2, %0" : "=x" (w) : "0" (dt.x[i]), "x" (dt.y[i]), "x" (dt.z[i]));
+ thisres |= test( w, dt.expected[i] );
+ __asm __volatile__ ("vfmadd213sd %3, %2, %0" : "=x" (w) : "0" (dt.x[i]), "x" (dt.y[i]), "m" (dt.z[i]));
+ thisres |= test( w, dt.expected[i] );
+ __asm __volatile__ ("vfmadd231sd %2, %1, %0" : "=x" (w) : "x" (dt.x[i]), "x" (dt.y[i]), "0" (dt.z[i]));
+ thisres |= test( w, dt.expected[i] );
+ __asm __volatile__ ("vfmadd231sd %2, %1, %0" : "=x" (w) : "x" (dt.x[i]), "m" (dt.y[i]), "0" (dt.z[i]));
+ thisres |= test( w, dt.expected[i] );
+ if (thisres)
+ printf( "Failure 1 %d %a %a\n", i, w, dt.expected[i] );
+ res |= thisres;
+ thisres = 0;
+ __asm __volatile__ ("vfnmsub132sd %2, %3, %0" : "=x" (w) : "0" (dt.x[i]), "x" (dt.y[i]), "x" (dt.z[i]));
+ thisres |= test( -w, dt.expected[i] );
+ __asm __volatile__ ("vfnmsub132sd %2, %3, %0" : "=x" (w) : "0" (dt.x[i]), "m" (dt.y[i]), "x" (dt.z[i]));
+ thisres |= test( -w, dt.expected[i] );
+ __asm __volatile__ ("vfnmsub213sd %3, %2, %0" : "=x" (w) : "0" (dt.x[i]), "x" (dt.y[i]), "x" (dt.z[i]));
+ thisres |= test( -w, dt.expected[i] );
+ __asm __volatile__ ("vfnmsub213sd %3, %2, %0" : "=x" (w) : "0" (dt.x[i]), "x" (dt.y[i]), "m" (dt.z[i]));
+ thisres |= test( -w, dt.expected[i] );
+ __asm __volatile__ ("vfnmsub231sd %2, %1, %0" : "=x" (w) : "x" (dt.x[i]), "x" (dt.y[i]), "0" (dt.z[i]));
+ thisres |= test( -w, dt.expected[i] );
+ __asm __volatile__ ("vfnmsub231sd %2, %1, %0" : "=x" (w) : "x" (dt.x[i]), "m" (dt.y[i]), "0" (dt.z[i]));
+ thisres |= test( -w, dt.expected[i] );
+ if (thisres)
+ printf( "Failure 2 %d %a %a\n", i, w, dt.expected[i] );
+ res |= thisres;
+ }
+ for (i = 0; i < N; i++)
+ dt.z[i] = -dt.z[i];
+ for (i = 0; i < N; i++) {
+ int thisres = 0;
+ __asm __volatile__ ("vfmsub132sd %2, %3, %0" : "=x" (w) : "0" (dt.x[i]), "x" (dt.y[i]), "x" (dt.z[i]));
+ thisres |= test( w, dt.expected[i] );
+ __asm __volatile__ ("vfmsub132sd %2, %3, %0" : "=x" (w) : "0" (dt.x[i]), "m" (dt.y[i]), "x" (dt.z[i]));
+ thisres |= test( w, dt.expected[i] );
+ __asm __volatile__ ("vfmsub213sd %3, %2, %0" : "=x" (w) : "0" (dt.x[i]), "x" (dt.y[i]), "x" (dt.z[i]));
+ thisres |= test( w, dt.expected[i] );
+ __asm __volatile__ ("vfmsub213sd %3, %2, %0" : "=x" (w) : "0" (dt.x[i]), "x" (dt.y[i]), "m" (dt.z[i]));
+ thisres |= test( w, dt.expected[i] );
+ __asm __volatile__ ("vfmsub231sd %2, %1, %0" : "=x" (w) : "x" (dt.x[i]), "x" (dt.y[i]), "0" (dt.z[i]));
+ thisres |= test( w, dt.expected[i] );
+ __asm __volatile__ ("vfmsub231sd %2, %1, %0" : "=x" (w) : "x" (dt.x[i]), "m" (dt.y[i]), "0" (dt.z[i]));
+ thisres |= test( w, dt.expected[i] );
+ if (thisres)
+ printf( "Failure 3 %d %a %a\n", i, w, dt.expected[i] );
+ res |= thisres;
+ thisres = 0;
+ __asm __volatile__ ("vfnmadd132sd %2, %3, %0" : "=x" (w) : "0" (dt.x[i]), "x" (dt.y[i]), "x" (dt.z[i]));
+ thisres |= test( -w, dt.expected[i] );
+ __asm __volatile__ ("vfnmadd132sd %2, %3, %0" : "=x" (w) : "0" (dt.x[i]), "m" (dt.y[i]), "x" (dt.z[i]));
+ thisres |= test( -w, dt.expected[i] );
+ __asm __volatile__ ("vfnmadd213sd %3, %2, %0" : "=x" (w) : "0" (dt.x[i]), "x" (dt.y[i]), "x" (dt.z[i]));
+ thisres |= test( -w, dt.expected[i] );
+ __asm __volatile__ ("vfnmadd213sd %3, %2, %0" : "=x" (w) : "0" (dt.x[i]), "x" (dt.y[i]), "m" (dt.z[i]));
+ thisres |= test( -w, dt.expected[i] );
+ __asm __volatile__ ("vfnmadd231sd %2, %1, %0" : "=x" (w) : "x" (dt.x[i]), "x" (dt.y[i]), "0" (dt.z[i]));
+ thisres |= test( -w, dt.expected[i] );
+ __asm __volatile__ ("vfnmadd231sd %2, %1, %0" : "=x" (w) : "x" (dt.x[i]), "m" (dt.y[i]), "0" (dt.z[i]));
+ thisres |= test( -w, dt.expected[i] );
+ if (thisres)
+ printf( "Failure 4 %d %a %a\n", i, w, dt.expected[i] );
+ res |= thisres;
+ }
+ for (i = 0; i < N; i++)
+ dt.z[i] = -dt.z[i];
+ for (i = 0; i < N; i += 2) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%2), %%xmm7; vmovapd (%3), %%xmm8;"
+ "vfmadd132pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%3), %%xmm8;"
+ "vfmadd132pd (%2), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%3), %%xmm7; vmovapd (%2), %%xmm8;"
+ "vfmadd213pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%2), %%xmm8;"
+ "vfmadd213pd (%3), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%xmm9; vmovapd (%2), %%xmm7; vmovapd (%1), %%xmm8;"
+ "vfmadd231pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%xmm9; vmovapd (%1), %%xmm8;"
+ "vfmadd231pd (%2), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 5 %d", i );
+ for (j = 0; j < 2; j++)
+ printf( " %a %a", dt.res[i+j], dt.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ thisres = 0;
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%2), %%xmm7; vmovapd (%3), %%xmm8;"
+ "vfnmsub132pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%3), %%xmm8;"
+ "vfnmsub132pd (%2), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%3), %%xmm7; vmovapd (%2), %%xmm8;"
+ "vfnmsub213pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%2), %%xmm8;"
+ "vfnmsub213pd (%3), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%xmm9; vmovapd (%2), %%xmm7; vmovapd (%1), %%xmm8;"
+ "vfnmsub231pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%xmm9; vmovapd (%1), %%xmm8;"
+ "vfnmsub231pd (%2), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 6 %d", i );
+ for (j = 0; j < 2; j++)
+ printf( " %a %a", dt.res[i+j], dt.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 0; i < N; i++)
+ dt.z[i] = -dt.z[i];
+ for (i = 0; i < N; i += 2) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%2), %%xmm7; vmovapd (%3), %%xmm8;"
+ "vfmsub132pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%3), %%xmm8;"
+ "vfmsub132pd (%2), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%3), %%xmm7; vmovapd (%2), %%xmm8;"
+ "vfmsub213pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%2), %%xmm8;"
+ "vfmsub213pd (%3), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%xmm9; vmovapd (%2), %%xmm7; vmovapd (%1), %%xmm8;"
+ "vfmsub231pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%xmm9; vmovapd (%1), %%xmm8;"
+ "vfmsub231pd (%2), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 7 %d", i );
+ for (j = 0; j < 2; j++)
+ printf( " %a %a", dt.res[i+j], dt.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ thisres = 0;
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%2), %%xmm7; vmovapd (%3), %%xmm8;"
+ "vfnmadd132pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%3), %%xmm8;"
+ "vfnmadd132pd (%2), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%3), %%xmm7; vmovapd (%2), %%xmm8;"
+ "vfnmadd213pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%2), %%xmm8;"
+ "vfnmadd213pd (%3), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%xmm9; vmovapd (%2), %%xmm7; vmovapd (%1), %%xmm8;"
+ "vfnmadd231pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%xmm9; vmovapd (%1), %%xmm8;"
+ "vfnmadd231pd (%2), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 8 %d", i );
+ for (j = 0; j < 2; j++)
+ printf( " %a %a", dt.res[i+j], dt.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 1; i < N; i += 2)
+ dt.z[i] = -dt.z[i];
+ for (i = 0; i < N; i += 2) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%2), %%xmm7; vmovapd (%3), %%xmm8;"
+ "vfmaddsub132pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%3), %%xmm8;"
+ "vfmaddsub132pd (%2), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%3), %%xmm7; vmovapd (%2), %%xmm8;"
+ "vfmaddsub213pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%2), %%xmm8;"
+ "vfmaddsub213pd (%3), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%xmm9; vmovapd (%2), %%xmm7; vmovapd (%1), %%xmm8;"
+ "vfmaddsub231pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%xmm9; vmovapd (%1), %%xmm8;"
+ "vfmaddsub231pd (%2), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 9 %d", i );
+ for (j = 0; j < 2; j++)
+ printf( " %a %a", dt.res[i+j], dt.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 0; i < N; i++)
+ dt.z[i] = -dt.z[i];
+ for (i = 0; i < N; i += 2) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%2), %%xmm7; vmovapd (%3), %%xmm8;"
+ "vfmsubadd132pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%3), %%xmm8;"
+ "vfmsubadd132pd (%2), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%3), %%xmm7; vmovapd (%2), %%xmm8;"
+ "vfmsubadd213pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%xmm9; vmovapd (%2), %%xmm8;"
+ "vfmsubadd213pd (%3), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%xmm9; vmovapd (%2), %%xmm7; vmovapd (%1), %%xmm8;"
+ "vfmsubadd231pd %%xmm7, %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%xmm9; vmovapd (%1), %%xmm8;"
+ "vfmsubadd231pd (%2), %%xmm8, %%xmm9;"
+ "vmovapd %%xmm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 2; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 10 %d", i );
+ for (j = 0; j < 2; j++)
+ printf( " %a %a", dt.res[i+j], dt.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 1; i < N; i += 2)
+ dt.z[i] = -dt.z[i];
+ for (i = 0; i < N; i += 4) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%2), %%ymm7; vmovapd (%3), %%ymm8;"
+ "vfmadd132pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%3), %%ymm8;"
+ "vfmadd132pd (%2), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%3), %%ymm7; vmovapd (%2), %%ymm8;"
+ "vfmadd213pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%2), %%ymm8;"
+ "vfmadd213pd (%3), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%ymm9; vmovapd (%2), %%ymm7; vmovapd (%1), %%ymm8;"
+ "vfmadd231pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%ymm9; vmovapd (%1), %%ymm8;"
+ "vfmadd231pd (%2), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 11 %d", i );
+ for (j = 0; j < 4; j++)
+ printf( " %a %a", dt.res[i+j], dt.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ thisres = 0;
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%2), %%ymm7; vmovapd (%3), %%ymm8;"
+ "vfnmsub132pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%3), %%ymm8;"
+ "vfnmsub132pd (%2), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%3), %%ymm7; vmovapd (%2), %%ymm8;"
+ "vfnmsub213pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%2), %%ymm8;"
+ "vfnmsub213pd (%3), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%ymm9; vmovapd (%2), %%ymm7; vmovapd (%1), %%ymm8;"
+ "vfnmsub231pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%ymm9; vmovapd (%1), %%ymm8;"
+ "vfnmsub231pd (%2), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 12 %d", i );
+ for (j = 0; j < 4; j++)
+ printf( " %a %a", dt.res[i+j], dt.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 0; i < N; i++)
+ dt.z[i] = -dt.z[i];
+ for (i = 0; i < N; i += 4) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%2), %%ymm7; vmovapd (%3), %%ymm8;"
+ "vfmsub132pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%3), %%ymm8;"
+ "vfmsub132pd (%2), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%3), %%ymm7; vmovapd (%2), %%ymm8;"
+ "vfmsub213pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%2), %%ymm8;"
+ "vfmsub213pd (%3), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%ymm9; vmovapd (%2), %%ymm7; vmovapd (%1), %%ymm8;"
+ "vfmsub231pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%ymm9; vmovapd (%1), %%ymm8;"
+ "vfmsub231pd (%2), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 13 %d", i );
+ for (j = 0; j < 4; j++)
+ printf( " %a %a", dt.res[i+j], dt.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ thisres = 0;
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%2), %%ymm7; vmovapd (%3), %%ymm8;"
+ "vfnmadd132pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%3), %%ymm8;"
+ "vfnmadd132pd (%2), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%3), %%ymm7; vmovapd (%2), %%ymm8;"
+ "vfnmadd213pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%2), %%ymm8;"
+ "vfnmadd213pd (%3), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%ymm9; vmovapd (%2), %%ymm7; vmovapd (%1), %%ymm8;"
+ "vfnmadd231pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%ymm9; vmovapd (%1), %%ymm8;"
+ "vfnmadd231pd (%2), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( -dt.res[i+j], dt.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 14 %d", i );
+ for (j = 0; j < 4; j++)
+ printf( " %a %a", dt.res[i+j], dt.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 1; i < N; i += 2)
+ dt.z[i] = -dt.z[i];
+ for (i = 0; i < N; i += 4) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%2), %%ymm7; vmovapd (%3), %%ymm8;"
+ "vfmaddsub132pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%3), %%ymm8;"
+ "vfmaddsub132pd (%2), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%3), %%ymm7; vmovapd (%2), %%ymm8;"
+ "vfmaddsub213pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%2), %%ymm8;"
+ "vfmaddsub213pd (%3), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%ymm9; vmovapd (%2), %%ymm7; vmovapd (%1), %%ymm8;"
+ "vfmaddsub231pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%ymm9; vmovapd (%1), %%ymm8;"
+ "vfmaddsub231pd (%2), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 15 %d", i );
+ for (j = 0; j < 4; j++)
+ printf( " %a %a", dt.res[i+j], dt.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 0; i < N; i++)
+ dt.z[i] = -dt.z[i];
+ for (i = 0; i < N; i += 4) {
+ int thisres = 0;
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%2), %%ymm7; vmovapd (%3), %%ymm8;"
+ "vfmsubadd132pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%3), %%ymm8;"
+ "vfmsubadd132pd (%2), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%3), %%ymm7; vmovapd (%2), %%ymm8;"
+ "vfmsubadd213pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%1), %%ymm9; vmovapd (%2), %%ymm8;"
+ "vfmsubadd213pd (%3), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%ymm9; vmovapd (%2), %%ymm7; vmovapd (%1), %%ymm8;"
+ "vfmsubadd231pd %%ymm7, %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ __asm __volatile__ ("vmovapd (%3), %%ymm9; vmovapd (%1), %%ymm8;"
+ "vfmsubadd231pd (%2), %%ymm8, %%ymm9;"
+ "vmovapd %%ymm9, (%0)" : : "r" (&dt.res[i]), "r" (&dt.x[i]),
+ "r" (&dt.y[i]), "r" (&dt.z[i]) : "xmm7", "xmm8", "xmm9");
+ for (j = 0; j < 4; j++)
+ thisres |= test( dt.res[i+j], dt.expected[i+j] );
+ if (thisres) {
+ printf( "Failure 16 %d", i );
+ for (j = 0; j < 4; j++)
+ printf( " %a %a", dt.res[i+j], dt.expected[i+j] );
+ printf( "\n" );
+ }
+ res |= thisres;
+ }
+ for (i = 1; i < N; i += 2)
+ dt.z[i] = -dt.z[i];
+ return res;
+}
+
+int main( )
+{
+ int res = 0;
+ int i = 0;
+ plus_zero = 0.0;
+ __asm __volatile__ ("" : : "r" (&plus_zero) : "memory");
+ nan_value = plus_zero / plus_zero;
+ plus_infty = 3.40282346638528859812e+38F * 16.0F;
+ minus_infty = -plus_infty;
+#define TEST_F( a, b, c, d ) \
+ do { \
+ ft.x[i] = a; \
+ ft.y[i] = b; \
+ ft.z[i] = c; \
+ ft.expected[i] = d; \
+ i++; \
+ } while (0)
+ TEST_F( 1.0, 2.0, 3.0, 5.0 );
+ TEST_F( nan_value, 2.0, 3.0, nan_value );
+ TEST_F( 1.0, nan_value, 3.0, nan_value );
+ TEST_F( 1.0, 2.0, nan_value, nan_value );
+ TEST_F( plus_infty, 0.0, nan_value, nan_value );
+ TEST_F( minus_infty, 0.0, nan_value, nan_value );
+ TEST_F( 0.0, plus_infty, nan_value, nan_value );
+ TEST_F( 0.0, minus_infty, nan_value, nan_value );
+ TEST_F( plus_infty, 0.0, 1.0, nan_value );
+ TEST_F( minus_infty, 0.0, 1.0, nan_value );
+ TEST_F( 0.0, plus_infty, 1.0, nan_value );
+ TEST_F( 0.0, minus_infty, 1.0, nan_value );
+ TEST_F( plus_infty, plus_infty, minus_infty, nan_value );
+ TEST_F( minus_infty, plus_infty, plus_infty, nan_value );
+ TEST_F( plus_infty, minus_infty, plus_infty, nan_value );
+ TEST_F( minus_infty, minus_infty, minus_infty, nan_value );
+ TEST_F( plus_infty, 3.5L, minus_infty, nan_value );
+ TEST_F( minus_infty, -7.5L, minus_infty, nan_value );
+ TEST_F( -13.5L, plus_infty, plus_infty, nan_value );
+ TEST_F( minus_infty, 7.5L, plus_infty, nan_value );
+ TEST_F( 1.25L, 0.75L, 0.0625L, 1.0L );
+ TEST_F( -3.40282346638528859812e+38F, -3.40282346638528859812e+38F, minus_infty, minus_infty );
+ TEST_F( 3.40282346638528859812e+38F / 2, 3.40282346638528859812e+38F / 2, minus_infty, minus_infty );
+ TEST_F( -3.40282346638528859812e+38F, 3.40282346638528859812e+38F, plus_infty, plus_infty );
+ TEST_F( 3.40282346638528859812e+38F / 2, -3.40282346638528859812e+38F / 4, plus_infty, plus_infty );
+ TEST_F( plus_infty, 4, plus_infty, plus_infty );
+ TEST_F( 2, minus_infty, minus_infty, minus_infty );
+ TEST_F( minus_infty, minus_infty, plus_infty, plus_infty );
+ TEST_F( plus_infty, minus_infty, minus_infty, minus_infty );
+ TEST_F( 0x1.7ff8p+13, 0x1.000002p+0, 0x1.ffffp-24, 0x1.7ff802p+13 );
+ TEST_F( 0x1.fffp+0, 0x1.00001p+0, -0x1.fffp+0, 0x1.fffp-20 );
+ TEST_F( 0x1.9abcdep+127, 0x0.9abcdep-126, -0x1.f08948p+0, 0x1.bb421p-25 );
+ TEST_F( 0x1.9abcdep+100, 0x0.9abcdep-126, -0x1.f08948p-27, 0x1.bb421p-52 );
+ TEST_F( 0x1.fffffep+127, 0x1.001p+0, -0x1.fffffep+127, 0x1.fffffep+115 );
+ TEST_F( -0x1.fffffep+127, 0x1.fffffep+0, 0x1.fffffep+127, -0x1.fffffap+127 );
+ TEST_F( 0x1.fffffep+127, 2.0, -0x1.fffffep+127, 0x1.fffffep+127 );
+
+ res |= test_fmaf( );
+ i = 0;
+#define TEST( a, b, c, d ) \
+ do { \
+ dt.x[i] = a; \
+ dt.y[i] = b; \
+ dt.z[i] = c; \
+ dt.expected[i] = d; \
+ i++; \
+ } while (0)
+ TEST( 1.0, 2.0, 3.0, 5.0 );
+ TEST( nan_value, 2.0, 3.0, nan_value );
+ TEST( 1.0, nan_value, 3.0, nan_value );
+ TEST( 1.0, 2.0, nan_value, nan_value );
+ TEST( plus_infty, 0.0, nan_value, nan_value );
+ TEST( minus_infty, 0.0, nan_value, nan_value );
+ TEST( 0.0, plus_infty, nan_value, nan_value );
+ TEST( 0.0, minus_infty, nan_value, nan_value );
+ TEST( plus_infty, 0.0, 1.0, nan_value );
+ TEST( minus_infty, 0.0, 1.0, nan_value );
+ TEST( 0.0, plus_infty, 1.0, nan_value );
+ TEST( 0.0, minus_infty, 1.0, nan_value );
+ TEST( plus_infty, plus_infty, minus_infty, nan_value );
+ TEST( minus_infty, plus_infty, plus_infty, nan_value );
+ TEST( plus_infty, minus_infty, plus_infty, nan_value );
+ TEST( minus_infty, minus_infty, minus_infty, nan_value );
+ TEST( plus_infty, 3.5L, minus_infty, nan_value );
+ TEST( minus_infty, -7.5L, minus_infty, nan_value );
+ TEST( -13.5L, plus_infty, plus_infty, nan_value );
+ TEST( minus_infty, 7.5L, plus_infty, nan_value );
+ TEST( 1.25L, 0.75L, 0.0625L, 1.0L );
+ TEST( -1.79769313486231570815e+308L, -1.79769313486231570815e+308L, minus_infty, minus_infty );
+ TEST( 1.79769313486231570815e+308L / 2, 1.79769313486231570815e+308L / 2, minus_infty, minus_infty );
+ TEST( -1.79769313486231570815e+308L, 1.79769313486231570815e+308L, plus_infty, plus_infty );
+ TEST( 1.79769313486231570815e+308L / 2, -1.79769313486231570815e+308L / 4, plus_infty, plus_infty );
+ TEST( plus_infty, 4, plus_infty, plus_infty );
+ TEST( 2, minus_infty, minus_infty, minus_infty );
+ TEST( minus_infty, minus_infty, plus_infty, plus_infty );
+ TEST( plus_infty, minus_infty, minus_infty, minus_infty );
+ TEST( 0x1.7fp+13, 0x1.0000000000001p+0, 0x1.ffep-48, 0x1.7f00000000001p+13 );
+ TEST( 0x1.fffp+0, 0x1.0000000000001p+0, -0x1.fffp+0, 0x1.fffp-52 );
+ TEST( 0x1.0000002p+0, 0x1.ffffffcp-1, 0x1p-300, 1.0 );
+ TEST( 0x1.0000002p+0, 0x1.ffffffcp-1, -0x1p-300, 0x1.fffffffffffffp-1 );
+ TEST( 0x1.deadbeef2feedp+1023, 0x0.deadbeef2feedp-1022, -0x1.a05f8c01a4bfbp+1, 0x1.0989687bc9da4p-53 );
+ TEST( 0x1.deadbeef2feedp+900, 0x0.deadbeef2feedp-1022, -0x1.a05f8c01a4bfbp-122, 0x1.0989687bc9da4p-176 );
+ TEST( 0x1.fffffffffffffp+1023, 0x1.001p+0, -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1011 );
+ TEST( -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+0, 0x1.fffffffffffffp+1023, -0x1.ffffffffffffdp+1023 );
+ TEST( 0x1.fffffffffffffp+1023, 2.0, -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023 );
+ TEST( 0x1.6a09e667f3bccp-538, 0x1.6a09e667f3bccp-538, 0.0, 0.0 );
+ TEST( 0x1.deadbeef2feedp-495, 0x1.deadbeef2feedp-495, -0x1.bf86a5786a574p-989, 0x0.0000042625a1fp-1022 );
+ TEST( 0x1.deadbeef2feedp-503, 0x1.deadbeef2feedp-503, -0x1.bf86a5786a574p-1005, 0x0.0000000004262p-1022 );
+ TEST( 0x1p-537, 0x1p-538, 0x1p-1074, 0x0.0000000000002p-1022 );
+ TEST( 0x1.7fffff8p-968, 0x1p-106, 0x0.000001p-1022, 0x0.0000010000001p-1022 );
+ TEST( 0x1.4000004p-967, 0x1p-106, 0x0.000001p-1022, 0x0.0000010000003p-1022 );
+ TEST( 0x1.4p-967, -0x1p-106, -0x0.000001p-1022, -0x0.0000010000002p-1022 );
+ TEST( -0x1.19cab66d73e17p-959, 0x1.c7108a8c5ff51p-107, -0x0.80b0ad65d9b64p-1022, -0x0.80b0ad65d9d59p-1022 );
+ TEST( -0x1.d2eaed6e8e9d3p-979, -0x1.4e066c62ac9ddp-63, -0x0.9245e6b003454p-1022, -0x0.9245c09c5fb5dp-1022 );
+ TEST( 0x1.153d650bb9f06p-907, 0x1.2d01230d48407p-125, -0x0.b278d5acfc3cp-1022, -0x0.b22757123bbe9p-1022 );
+ TEST( -0x1.fffffffffffffp-711, 0x1.fffffffffffffp-275, 0x1.fffffe00007ffp-983, 0x1.7ffffe00007ffp-983 );
+
+ res |= test_fma( );
+ if (res == 0)
+ printf( "Testing successful\n");
+ return 0;
+}
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/fma.stdout.exp valgrind-3.8.0.new/none/tests/amd64/fma.stdout.exp
--- valgrind-3.8.0.orig/none/tests/amd64/fma.stdout.exp 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/none/tests/amd64/fma.stdout.exp 2012-09-13 11:19:25.188050651 +0200
@@ -0,0 +1 @@
+Testing successful
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/fma.vgtest valgrind-3.8.0.new/none/tests/amd64/fma.vgtest
--- valgrind-3.8.0.orig/none/tests/amd64/fma.vgtest 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/none/tests/amd64/fma.vgtest 2012-09-13 11:19:25.189050665 +0200
@@ -0,0 +1,3 @@
+prog: fma
+prereq: ../../../tests/x86_amd64_features amd64-avx
+vgopts: -q
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/Makefile.am valgrind-3.8.0.new/none/tests/amd64/Makefile.am
--- valgrind-3.8.0.orig/none/tests/amd64/Makefile.am 2012-09-12 17:37:34.545930341 +0200
+++ valgrind-3.8.0.new/none/tests/amd64/Makefile.am 2012-09-13 13:22:30.796798471 +0200
@@ -24,7 +24,10 @@
aes.vgtest aes.stdout.exp aes.stderr.exp \
amd64locked.vgtest amd64locked.stdout.exp amd64locked.stderr.exp \
avx-1.vgtest avx-1.stdout.exp avx-1.stderr.exp \
+ avx2-1.vgtest avx2-1.stdout.exp avx2-1.stderr.exp \
asorep.stderr.exp asorep.stdout.exp asorep.vgtest \
+ bmi.stderr.exp bmi.stdout.exp bmi.vgtest \
+ fma.stderr.exp fma.stdout.exp fma.vgtest \
bug127521-64.vgtest bug127521-64.stdout.exp bug127521-64.stderr.exp \
bug132813-amd64.vgtest bug132813-amd64.stdout.exp \
bug132813-amd64.stderr.exp \
@@ -109,6 +112,15 @@
check_PROGRAMS += avx-1
endif
endif
+if BUILD_AVX2_TESTS
+ check_PROGRAMS += avx2-1
+endif
+if BUILD_BMI_TESTS
+ check_PROGRAMS += bmi
+endif
+if BUILD_FMA_TESTS
+ check_PROGRAMS += fma
+endif
if BUILD_MOVBE_TESTS
check_PROGRAMS += movbe
endif
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/none/tests/amd64/Makefile.in valgrind-3.8.0.new/none/tests/amd64/Makefile.in
--- valgrind-3.8.0.orig/none/tests/amd64/Makefile.in 2012-09-12 17:37:34.543930313 +0200
+++ valgrind-3.8.0.new/none/tests/amd64/Makefile.in 2012-09-13 13:24:07.024230939 +0200
@@ -64,7 +64,8 @@
redundantRexW$(EXEEXT) smc1$(EXEEXT) sbbmisc$(EXEEXT) \
nibz_bennee_mmap$(EXEEXT) xadd$(EXEEXT) $(am__EXEEXT_5) \
$(am__EXEEXT_6) $(am__EXEEXT_7) $(am__EXEEXT_8) \
- $(am__EXEEXT_9) $(am__EXEEXT_10)
+ $(am__EXEEXT_9) $(am__EXEEXT_10) $(am__EXEEXT_11) \
+ $(am__EXEEXT_12) $(am__EXEEXT_13)
@BUILD_SSSE3_TESTS_TRUE@am__append_6 = ssse3_misaligned
@BUILD_LZCNT_TESTS_TRUE@am__append_7 = lzcnt64
@BUILD_SSE42_TESTS_TRUE@am__append_8 = \
@@ -72,10 +73,13 @@
@BUILD_SSE42_TESTS_TRUE@ pcmpstr64w pcmpxstrx64w
@BUILD_AVX_TESTS_TRUE@@BUILD_VPCLMULQDQ_TESTS_TRUE@am__append_9 = avx-1
-@BUILD_MOVBE_TESTS_TRUE@am__append_10 = movbe
+@BUILD_AVX2_TESTS_TRUE@am__append_10 = avx2-1
+@BUILD_BMI_TESTS_TRUE@am__append_11 = bmi
+@BUILD_FMA_TESTS_TRUE@am__append_12 = fma
+@BUILD_MOVBE_TESTS_TRUE@am__append_13 = movbe
# DDD: these need to be made to work on Darwin like the x86/ ones were.
-@VGCONF_OS_IS_DARWIN_FALSE@am__append_11 = \
+@VGCONF_OS_IS_DARWIN_FALSE@am__append_14 = \
@VGCONF_OS_IS_DARWIN_FALSE@ bug137714-amd64 \
@VGCONF_OS_IS_DARWIN_FALSE@ bug156404-amd64 \
@VGCONF_OS_IS_DARWIN_FALSE@ faultstatus \
@@ -110,8 +114,11 @@
@BUILD_SSE42_TESTS_TRUE@ pcmpstr64w$(EXEEXT) \
@BUILD_SSE42_TESTS_TRUE@ pcmpxstrx64w$(EXEEXT)
@BUILD_AVX_TESTS_TRUE@@BUILD_VPCLMULQDQ_TESTS_TRUE@am__EXEEXT_8 = avx-1$(EXEEXT)
-@BUILD_MOVBE_TESTS_TRUE@am__EXEEXT_9 = movbe$(EXEEXT)
-@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_10 = bug137714-amd64$(EXEEXT) \
+@BUILD_AVX2_TESTS_TRUE@am__EXEEXT_9 = avx2-1$(EXEEXT)
+@BUILD_BMI_TESTS_TRUE@am__EXEEXT_10 = bmi$(EXEEXT)
+@BUILD_FMA_TESTS_TRUE@am__EXEEXT_11 = fma$(EXEEXT)
+@BUILD_MOVBE_TESTS_TRUE@am__EXEEXT_12 = movbe$(EXEEXT)
+@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_13 = bug137714-amd64$(EXEEXT) \
@VGCONF_OS_IS_DARWIN_FALSE@ bug156404-amd64$(EXEEXT) \
@VGCONF_OS_IS_DARWIN_FALSE@ faultstatus$(EXEEXT) \
@VGCONF_OS_IS_DARWIN_FALSE@ fcmovnu$(EXEEXT) fxtract$(EXEEXT) \
@@ -137,6 +144,12 @@
avx_1_SOURCES = avx-1.c
avx_1_OBJECTS = avx-1.$(OBJEXT)
avx_1_LDADD = $(LDADD)
+avx2_1_SOURCES = avx2-1.c
+avx2_1_OBJECTS = avx2-1.$(OBJEXT)
+avx2_1_LDADD = $(LDADD)
+bmi_SOURCES = bmi.c
+bmi_OBJECTS = bmi.$(OBJEXT)
+bmi_LDADD = $(LDADD)
bug127521_64_SOURCES = bug127521-64.c
bug127521_64_OBJECTS = bug127521-64.$(OBJEXT)
bug127521_64_LDADD = $(LDADD)
@@ -167,6 +180,9 @@
fcmovnu_SOURCES = fcmovnu.c
fcmovnu_OBJECTS = fcmovnu.$(OBJEXT)
fcmovnu_LDADD = $(LDADD)
+fma_SOURCES = fma.c
+fma_OBJECTS = fma.$(OBJEXT)
+fma_LDADD = $(LDADD)
fxtract_SOURCES = fxtract.c
fxtract_OBJECTS = fxtract-fxtract.$(OBJEXT)
fxtract_DEPENDENCIES =
@@ -265,23 +281,25 @@
$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
CCLD = $(CC)
LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
-SOURCES = aes.c allexec.c amd64locked.c asorep.c avx-1.c \
- bug127521-64.c bug132813-amd64.c bug132918.c bug137714-amd64.c \
- bug156404-amd64.c clc.c cmpxchg.c crc32.c faultstatus.c \
- fcmovnu.c fxtract.c $(insn_basic_SOURCES) $(insn_fpu_SOURCES) \
- $(insn_mmx_SOURCES) $(insn_pclmulqdq_SOURCES) \
- $(insn_sse_SOURCES) $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
+SOURCES = aes.c allexec.c amd64locked.c asorep.c avx-1.c avx2-1.c \
+ bmi.c bug127521-64.c bug132813-amd64.c bug132918.c \
+ bug137714-amd64.c bug156404-amd64.c clc.c cmpxchg.c crc32.c \
+ faultstatus.c fcmovnu.c fma.c fxtract.c $(insn_basic_SOURCES) \
+ $(insn_fpu_SOURCES) $(insn_mmx_SOURCES) \
+ $(insn_pclmulqdq_SOURCES) $(insn_sse_SOURCES) \
+ $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
$(insn_ssse3_SOURCES) jrcxz.c looper.c loopnel.c lzcnt64.c \
movbe.c nan80and64.c nibz_bennee_mmap.c pcmpstr64.c \
pcmpstr64w.c pcmpxstrx64.c pcmpxstrx64w.c rcl-amd64.c \
redundantRexW.c sbbmisc.c shrld.c slahf-amd64.c smc1.c \
sse4-64.c ssse3_misaligned.c xadd.c
-DIST_SOURCES = aes.c allexec.c amd64locked.c asorep.c avx-1.c \
- bug127521-64.c bug132813-amd64.c bug132918.c bug137714-amd64.c \
- bug156404-amd64.c clc.c cmpxchg.c crc32.c faultstatus.c \
- fcmovnu.c fxtract.c $(insn_basic_SOURCES) $(insn_fpu_SOURCES) \
- $(insn_mmx_SOURCES) $(insn_pclmulqdq_SOURCES) \
- $(insn_sse_SOURCES) $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
+DIST_SOURCES = aes.c allexec.c amd64locked.c asorep.c avx-1.c avx2-1.c \
+ bmi.c bug127521-64.c bug132813-amd64.c bug132918.c \
+ bug137714-amd64.c bug156404-amd64.c clc.c cmpxchg.c crc32.c \
+ faultstatus.c fcmovnu.c fma.c fxtract.c $(insn_basic_SOURCES) \
+ $(insn_fpu_SOURCES) $(insn_mmx_SOURCES) \
+ $(insn_pclmulqdq_SOURCES) $(insn_sse_SOURCES) \
+ $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
$(insn_ssse3_SOURCES) jrcxz.c looper.c loopnel.c lzcnt64.c \
movbe.c nan80and64.c nibz_bennee_mmap.c pcmpstr64.c \
pcmpstr64w.c pcmpxstrx64.c pcmpxstrx64w.c rcl-amd64.c \
@@ -578,7 +596,10 @@
aes.vgtest aes.stdout.exp aes.stderr.exp \
amd64locked.vgtest amd64locked.stdout.exp amd64locked.stderr.exp \
avx-1.vgtest avx-1.stdout.exp avx-1.stderr.exp \
+ avx2-1.vgtest avx2-1.stdout.exp avx2-1.stderr.exp \
asorep.stderr.exp asorep.stdout.exp asorep.vgtest \
+ bmi.stderr.exp bmi.stdout.exp bmi.vgtest \
+ fma.stderr.exp fma.stdout.exp fma.vgtest \
bug127521-64.vgtest bug127521-64.stdout.exp bug127521-64.stderr.exp \
bug132813-amd64.vgtest bug132813-amd64.stdout.exp \
bug132813-amd64.stderr.exp \
@@ -706,6 +727,12 @@
avx-1$(EXEEXT): $(avx_1_OBJECTS) $(avx_1_DEPENDENCIES)
@rm -f avx-1$(EXEEXT)
$(LINK) $(avx_1_OBJECTS) $(avx_1_LDADD) $(LIBS)
+avx2-1$(EXEEXT): $(avx2_1_OBJECTS) $(avx2_1_DEPENDENCIES)
+ @rm -f avx2-1$(EXEEXT)
+ $(LINK) $(avx2_1_OBJECTS) $(avx2_1_LDADD) $(LIBS)
+bmi$(EXEEXT): $(bmi_OBJECTS) $(bmi_DEPENDENCIES)
+ @rm -f bmi$(EXEEXT)
+ $(LINK) $(bmi_OBJECTS) $(bmi_LDADD) $(LIBS)
bug127521-64$(EXEEXT): $(bug127521_64_OBJECTS) $(bug127521_64_DEPENDENCIES)
@rm -f bug127521-64$(EXEEXT)
$(LINK) $(bug127521_64_OBJECTS) $(bug127521_64_LDADD) $(LIBS)
@@ -736,6 +763,9 @@
fcmovnu$(EXEEXT): $(fcmovnu_OBJECTS) $(fcmovnu_DEPENDENCIES)
@rm -f fcmovnu$(EXEEXT)
$(LINK) $(fcmovnu_OBJECTS) $(fcmovnu_LDADD) $(LIBS)
+fma$(EXEEXT): $(fma_OBJECTS) $(fma_DEPENDENCIES)
+ @rm -f fma$(EXEEXT)
+ $(LINK) $(fma_OBJECTS) $(fma_LDADD) $(LIBS)
fxtract$(EXEEXT): $(fxtract_OBJECTS) $(fxtract_DEPENDENCIES)
@rm -f fxtract$(EXEEXT)
$(fxtract_LINK) $(fxtract_OBJECTS) $(fxtract_LDADD) $(LIBS)
@@ -835,6 +865,8 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/amd64locked-amd64locked.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/asorep.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avx-1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avx2-1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bmi.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug127521-64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug132813-amd64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug132918.Po@am__quote@
@@ -845,6 +877,7 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/crc32.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/faultstatus.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fcmovnu.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fma.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fxtract-fxtract.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_basic.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_fpu.Po@am__quote@
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/priv/guest_amd64_defs.h valgrind-3.8.0.new/VEX/priv/guest_amd64_defs.h
--- valgrind-3.8.0.orig/VEX/priv/guest_amd64_defs.h 2012-09-12 17:37:34.509929812 +0200
+++ valgrind-3.8.0.new/VEX/priv/guest_amd64_defs.h 2012-09-12 19:54:35.382027367 +0200
@@ -151,6 +151,9 @@
ULong dHi, ULong dLo,
ULong imm_and_return_control_bit );
+extern ULong amd64g_calculate_pext ( ULong, ULong );
+extern ULong amd64g_calculate_pdep ( ULong, ULong );
+
/* --- DIRTY HELPERS --- */
extern ULong amd64g_dirtyhelper_loadF80le ( ULong/*addr*/ );
@@ -504,6 +507,18 @@
AMD64G_CC_OP_SMULL, /* 51 */
AMD64G_CC_OP_SMULQ, /* 52 */
+ AMD64G_CC_OP_ANDN32, /* 53 */
+ AMD64G_CC_OP_ANDN64, /* 54 DEP1 = res, DEP2 = 0, NDEP = unused */
+
+ AMD64G_CC_OP_BLSI32, /* 55 */
+ AMD64G_CC_OP_BLSI64, /* 56 DEP1 = res, DEP2 = arg, NDEP = unused */
+
+ AMD64G_CC_OP_BLSMSK32,/* 57 */
+ AMD64G_CC_OP_BLSMSK64,/* 58 DEP1 = res, DEP2 = arg, NDEP = unused */
+
+ AMD64G_CC_OP_BLSR32, /* 59 */
+ AMD64G_CC_OP_BLSR64, /* 60 DEP1 = res, DEP2 = arg, NDEP = unused */
+
AMD64G_CC_OP_NUMBER
};
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/priv/guest_amd64_helpers.c valgrind-3.8.0.new/VEX/priv/guest_amd64_helpers.c
--- valgrind-3.8.0.orig/VEX/priv/guest_amd64_helpers.c 2012-09-12 17:37:34.513929872 +0200
+++ valgrind-3.8.0.new/VEX/priv/guest_amd64_helpers.c 2012-09-12 19:54:35.389027473 +0200
@@ -491,6 +491,72 @@
} \
}
+/*-------------------------------------------------------------*/
+
+#define ACTIONS_ANDN(DATA_BITS,DATA_UTYPE) \
+{ \
+ PREAMBLE(DATA_BITS); \
+ { Long cf, pf, af, zf, sf, of; \
+ cf = 0; \
+ pf = 0; \
+ af = 0; \
+ zf = ((DATA_UTYPE)CC_DEP1 == 0) << 6; \
+ sf = lshift(CC_DEP1, 8 - DATA_BITS) & 0x80; \
+ of = 0; \
+ return cf | pf | af | zf | sf | of; \
+ } \
+}
+
+/*-------------------------------------------------------------*/
+
+#define ACTIONS_BLSI(DATA_BITS,DATA_UTYPE) \
+{ \
+ PREAMBLE(DATA_BITS); \
+ { Long cf, pf, af, zf, sf, of; \
+ cf = ((DATA_UTYPE)CC_DEP2 != 0); \
+ pf = 0; \
+ af = 0; \
+ zf = ((DATA_UTYPE)CC_DEP1 == 0) << 6; \
+ sf = lshift(CC_DEP1, 8 - DATA_BITS) & 0x80; \
+ of = 0; \
+ return cf | pf | af | zf | sf | of; \
+ } \
+}
+
+/*-------------------------------------------------------------*/
+
+#define ACTIONS_BLSMSK(DATA_BITS,DATA_UTYPE) \
+{ \
+ PREAMBLE(DATA_BITS); \
+ { Long cf, pf, af, zf, sf, of; \
+ cf = ((DATA_UTYPE)CC_DEP2 == 0); \
+ pf = 0; \
+ af = 0; \
+ zf = 0; \
+ sf = lshift(CC_DEP1, 8 - DATA_BITS) & 0x80; \
+ of = 0; \
+ return cf | pf | af | zf | sf | of; \
+ } \
+}
+
+/*-------------------------------------------------------------*/
+
+#define ACTIONS_BLSR(DATA_BITS,DATA_UTYPE) \
+{ \
+ PREAMBLE(DATA_BITS); \
+ { Long cf, pf, af, zf, sf, of; \
+ cf = ((DATA_UTYPE)CC_DEP2 == 0); \
+ pf = 0; \
+ af = 0; \
+ zf = ((DATA_UTYPE)CC_DEP1 == 0) << 6; \
+ sf = lshift(CC_DEP1, 8 - DATA_BITS) & 0x80; \
+ of = 0; \
+ return cf | pf | af | zf | sf | of; \
+ } \
+}
+
+/*-------------------------------------------------------------*/
+
#if PROFILE_RFLAGS
@@ -654,6 +720,18 @@
case AMD64G_CC_OP_SMULQ: ACTIONS_SMULQ;
+ case AMD64G_CC_OP_ANDN32: ACTIONS_ANDN( 32, UInt );
+ case AMD64G_CC_OP_ANDN64: ACTIONS_ANDN( 64, ULong );
+
+ case AMD64G_CC_OP_BLSI32: ACTIONS_BLSI( 32, UInt );
+ case AMD64G_CC_OP_BLSI64: ACTIONS_BLSI( 64, ULong );
+
+ case AMD64G_CC_OP_BLSMSK32: ACTIONS_BLSMSK( 32, UInt );
+ case AMD64G_CC_OP_BLSMSK64: ACTIONS_BLSMSK( 64, ULong );
+
+ case AMD64G_CC_OP_BLSR32: ACTIONS_BLSR( 32, UInt );
+ case AMD64G_CC_OP_BLSR64: ACTIONS_BLSR( 64, ULong );
+
default:
/* shouldn't really make these calls from generated code */
vex_printf("amd64g_calculate_rflags_all_WRK(AMD64)"
@@ -3142,6 +3220,36 @@
return res;
}
+/* CALLED FROM GENERATED CODE: CLEAN HELPER */
+ULong amd64g_calculate_pext ( ULong src_masked, ULong mask )
+{
+ ULong dst = 0;
+ ULong src_bit;
+ ULong dst_bit = 1;
+ for (src_bit = 1; src_bit; src_bit <<= 1) {
+ if (mask & src_bit) {
+ if (src_masked & src_bit) dst |= dst_bit;
+ dst_bit <<= 1;
+ }
+ }
+ return dst;
+}
+
+/* CALLED FROM GENERATED CODE: CLEAN HELPER */
+ULong amd64g_calculate_pdep ( ULong src, ULong mask )
+{
+ ULong dst = 0;
+ ULong dst_bit;
+ ULong src_bit = 1;
+ for (dst_bit = 1; dst_bit; dst_bit <<= 1) {
+ if (mask & dst_bit) {
+ if (src & src_bit) dst |= dst_bit;
+ src_bit <<= 1;
+ }
+ }
+ return dst;
+}
+
/*---------------------------------------------------------------*/
/*--- Helpers for SSE4.2 PCMP{E,I}STR{I,M} ---*/
/*---------------------------------------------------------------*/
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/priv/guest_amd64_toIR.c valgrind-3.8.0.new/VEX/priv/guest_amd64_toIR.c
--- valgrind-3.8.0.orig/VEX/priv/guest_amd64_toIR.c 2012-09-12 17:37:34.509929813 +0200
+++ valgrind-3.8.0.new/VEX/priv/guest_amd64_toIR.c 2012-09-13 10:32:46.687584061 +0200
@@ -1291,6 +1291,38 @@
}
+static
+IRExpr* getIRegV ( Int sz, Prefix pfx )
+{
+ if (sz == 4) {
+ sz = 8;
+ return unop(Iop_64to32,
+ IRExpr_Get( offsetIReg( sz, getVexNvvvv(pfx), False ),
+ szToITy(sz) ));
+ } else {
+ return IRExpr_Get( offsetIReg( sz, getVexNvvvv(pfx), False ),
+ szToITy(sz) );
+ }
+}
+
+static
+void putIRegV ( Int sz, Prefix pfx, IRExpr* e )
+{
+ vassert(typeOfIRExpr(irsb->tyenv,e) == szToITy(sz));
+ if (sz == 4) {
+ e = unop(Iop_32Uto64,e);
+ }
+ stmt( IRStmt_Put( offsetIReg( sz, getVexNvvvv(pfx), False ), e ) );
+}
+
+static
+HChar* nameIRegV ( Int sz, Prefix pfx )
+{
+ return nameIReg( sz, getVexNvvvv(pfx), False );
+}
+
+
+
/* Produce the guest state offset for a reference to the 'e' register
field in a modrm byte, taking into account REX (or its absence),
and the size of the access. eregOfRexRM will assert if mod_reg_rm
@@ -2674,6 +2706,88 @@
}
+/* Similarly for VSIB addressing. This returns just the addend,
+ and fills in *rI and *vscale with the register number of the vector
+ index and its multiplicand. */
+static
+IRTemp disAVSIBMode ( /*OUT*/Int* len,
+ VexAbiInfo* vbi, Prefix pfx, Long delta,
+ /*OUT*/HChar* buf, /*OUT*/UInt* rI,
+ IRType ty, /*OUT*/Int* vscale )
+{
+ UChar mod_reg_rm = getUChar(delta);
+ HChar *vindex;
+
+ *len = 0;
+ *rI = 0;
+ *vscale = 0;
+ buf[0] = (UChar)0;
+ if ((mod_reg_rm & 7) != 4 || epartIsReg(mod_reg_rm))
+ return IRTemp_INVALID;
+
+ UChar sib = getUChar(delta+1);
+ UChar scale = toUChar((sib >> 6) & 3);
+ UChar index_r = toUChar((sib >> 3) & 7);
+ UChar base_r = toUChar(sib & 7);
+ Long d = 0;
+ /* correct since #(R13) == 8 + #(RBP) */
+ Bool base_is_BPor13 = toBool(base_r == R_RBP);
+ delta += 2;
+ *len = 2;
+
+ *rI = index_r | (getRexX(pfx) << 3);
+ if (ty == Ity_V128)
+ vindex = nameXMMReg(*rI);
+ else
+ vindex = nameYMMReg(*rI);
+ *vscale = 1<<scale;
+
+ switch (mod_reg_rm >> 6) {
+ case 0:
+ if (base_is_BPor13) {
+ d = getSDisp32(delta);
+ *len += 4;
+ if (scale == 0) {
+ DIS(buf, "%s%lld(,%s)", segRegTxt(pfx), d, vindex);
+ } else {
+ DIS(buf, "%s%lld(,%s,%d)", segRegTxt(pfx), d, vindex, 1<<scale);
+ }
+ return disAMode_copy2tmp( mkU64(d) );
+ } else {
+ if (scale == 0) {
+ DIS(buf, "%s(%s,%s)", segRegTxt(pfx),
+ nameIRegRexB(8,pfx,base_r), vindex);
+ } else {
+ DIS(buf, "%s(%s,%s,%d)", segRegTxt(pfx),
+ nameIRegRexB(8,pfx,base_r), vindex, 1<<scale);
+ }
+ }
+ break;
+ case 1:
+ d = getSDisp8(delta);
+ *len += 1;
+ goto have_disp;
+ case 2:
+ d = getSDisp32(delta);
+ *len += 4;
+ have_disp:
+ if (scale == 0) {
+ DIS(buf, "%s%lld(%s,%s)", segRegTxt(pfx), d,
+ nameIRegRexB(8,pfx,base_r), vindex);
+ } else {
+ DIS(buf, "%s%lld(%s,%s,%d)", segRegTxt(pfx), d,
+ nameIRegRexB(8,pfx,base_r), vindex, 1<<scale);
+ }
+ break;
+ }
+
+ if (!d)
+ return disAMode_copy2tmp( getIRegRexB(8,pfx,base_r) );
+ return disAMode_copy2tmp( binop(Iop_Add64, getIRegRexB(8,pfx,base_r),
+ mkU64(d)) );
+}
+
+
/* Figure out the number of (insn-stream) bytes constituting the amode
beginning at delta. Is useful for getting hold of literals beyond
the end of the amode before it has been disassembled. */
@@ -4667,6 +4781,35 @@
}
+/* Generate an IR sequence to do a count-trailing-zeroes operation on
+ the supplied IRTemp, and return a new IRTemp holding the result.
+ 'ty' may be Ity_I16, Ity_I32 or Ity_I64 only. In the case where
+ the argument is zero, return the number of bits in the word (the
+ natural semantics). */
+static IRTemp gen_TZCNT ( IRType ty, IRTemp src )
+{
+ vassert(ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16);
+
+ IRTemp src64 = newTemp(Ity_I64);
+ assign(src64, widenUto64( mkexpr(src) ));
+
+ // Ctz64 has undefined semantics when its input is zero, so
+ // special-case around that.
+ IRTemp res64 = newTemp(Ity_I64);
+ assign(res64,
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(Iop_CmpEQ64, mkexpr(src64), mkU64(0))),
+ unop(Iop_Ctz64, mkexpr(src64)),
+ mkU64(8 * sizeofIRType(ty))
+ ));
+
+ IRTemp res = newTemp(ty);
+ assign(res, narrowTo(ty, mkexpr(res64)));
+ return res;
+}
+
+
/*------------------------------------------------------------*/
/*--- ---*/
/*--- x87 FLOATING POINT INSTRUCTIONS ---*/
@@ -9270,6 +9413,31 @@
return math_PABS_XMM(aa, 1);
}
+/* YMM version of math_PABS_XMM. */
+static IRTemp math_PABS_YMM ( IRTemp aa, Int laneszB )
+{
+ IRTemp res = newTemp(Ity_V256);
+ IRTemp aaHi = IRTemp_INVALID;
+ IRTemp aaLo = IRTemp_INVALID;
+ breakupV256toV128s(aa, &aaHi, &aaLo);
+ assign(res, binop(Iop_V128HLtoV256,
+ mkexpr(math_PABS_XMM(aaHi, laneszB)),
+ mkexpr(math_PABS_XMM(aaLo, laneszB))));
+ return res;
+}
+
+static IRTemp math_PABS_YMM_pap4 ( IRTemp aa ) {
+ return math_PABS_YMM(aa, 4);
+}
+
+static IRTemp math_PABS_YMM_pap2 ( IRTemp aa ) {
+ return math_PABS_YMM(aa, 2);
+}
+
+static IRTemp math_PABS_YMM_pap1 ( IRTemp aa ) {
+ return math_PABS_YMM(aa, 1);
+}
+
static IRExpr* dis_PALIGNR_XMM_helper ( IRTemp hi64,
IRTemp lo64, Long byteShift )
{
@@ -9637,6 +9805,47 @@
}
+static Long dis_PSHUFD_32x8 ( VexAbiInfo* vbi, Prefix pfx, Long delta )
+{
+ Int order;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp sV = newTemp(Ity_V256);
+ UChar modrm = getUChar(delta);
+ IRTemp addr = IRTemp_INVALID;
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getYMMReg(rE) );
+ order = (Int)getUChar(delta+1);
+ delta += 1+1;
+ DIP("vpshufd $%d,%s,%s\n", order, nameYMMReg(rE), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf,
+ 1/*byte after the amode*/ );
+ assign( sV, loadLE(Ity_V256, mkexpr(addr)) );
+ order = (Int)getUChar(delta+alen);
+ delta += alen+1;
+ DIP("vpshufd $%d,%s,%s\n", order, dis_buf, nameYMMReg(rG));
+ }
+
+ IRTemp s[8];
+ s[7] = s[6] = s[5] = s[4] = s[3] = s[2] = s[1] = s[0] = IRTemp_INVALID;
+ breakupV256to32s( sV, &s[7], &s[6], &s[5], &s[4],
+ &s[3], &s[2], &s[1], &s[0] );
+
+ putYMMReg( rG, mkV256from32s( s[4 + ((order>>6)&3)],
+ s[4 + ((order>>4)&3)],
+ s[4 + ((order>>2)&3)],
+ s[4 + ((order>>0)&3)],
+ s[0 + ((order>>6)&3)],
+ s[0 + ((order>>4)&3)],
+ s[0 + ((order>>2)&3)],
+ s[0 + ((order>>0)&3)] ) );
+ return delta;
+}
+
+
static IRTemp math_PSRLDQ ( IRTemp sV, Int imm )
{
IRTemp dV = newTemp(Ity_V128);
@@ -10289,6 +10498,41 @@
}
+static Long dis_PMOVMSKB_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta )
+{
+ /* UInt x86g_calculate_sse_pmovmskb ( ULong w64hi, ULong w64lo ); */
+ UChar modrm = getUChar(delta);
+ vassert(epartIsReg(modrm)); /* ensured by caller */
+ UInt rE = eregOfRexRM(pfx,modrm);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp t0 = newTemp(Ity_I64);
+ IRTemp t1 = newTemp(Ity_I64);
+ IRTemp t2 = newTemp(Ity_I64);
+ IRTemp t3 = newTemp(Ity_I64);
+ IRTemp t5 = newTemp(Ity_I64);
+ IRTemp t6 = newTemp(Ity_I64);
+ assign(t0, getYMMRegLane64(rE, 0));
+ assign(t1, getYMMRegLane64(rE, 1));
+ assign(t2, getYMMRegLane64(rE, 2));
+ assign(t3, getYMMRegLane64(rE, 3));
+ assign(t5, mkIRExprCCall( Ity_I64, 0/*regparms*/,
+ "amd64g_calculate_sse_pmovmskb",
+ &amd64g_calculate_sse_pmovmskb,
+ mkIRExprVec_2( mkexpr(t1), mkexpr(t0) )));
+ assign(t6, mkIRExprCCall( Ity_I64, 0/*regparms*/,
+ "amd64g_calculate_sse_pmovmskb",
+ &amd64g_calculate_sse_pmovmskb,
+ mkIRExprVec_2( mkexpr(t3), mkexpr(t2) )));
+ putIReg32(rG, binop(Iop_Or32, unop(Iop_64to32,mkexpr(t5)),
+ binop(Iop_Shl32,
+ unop(Iop_64to32,mkexpr(t6)), mkU8(16))));
+ DIP("vpmovmskb %s,%s\n", nameYMMReg(rE), nameIReg32(rG));
+ delta += 1;
+ return delta;
+}
+
+
/* FIXME: why not just use InterleaveLO / InterleaveHI? I think the
relevant ops are "xIsH ? InterleaveHI32x4 : InterleaveLO32x4". */
/* Does the maths for 128 bit versions of UNPCKLPS and UNPCKHPS */
@@ -10551,6 +10795,22 @@
}
+static IRTemp math_PMULUDQ_256 ( IRTemp sV, IRTemp dV )
+{
+ /* This is a really poor translation -- could be improved if
+ performance critical */
+ IRTemp sHi, sLo, dHi, dLo;
+ sHi = sLo = dHi = dLo = IRTemp_INVALID;
+ breakupV256toV128s( dV, &dHi, &dLo);
+ breakupV256toV128s( sV, &sHi, &sLo);
+ IRTemp res = newTemp(Ity_V256);
+ assign(res, binop(Iop_V128HLtoV256,
+ mkexpr(math_PMULUDQ_128(sHi, dHi)),
+ mkexpr(math_PMULUDQ_128(sLo, dLo))));
+ return res;
+}
+
+
static IRTemp math_PMULDQ_128 ( IRTemp dV, IRTemp sV )
{
/* This is a really poor translation -- could be improved if
@@ -10567,6 +10827,22 @@
}
+static IRTemp math_PMULDQ_256 ( IRTemp sV, IRTemp dV )
+{
+ /* This is a really poor translation -- could be improved if
+ performance critical */
+ IRTemp sHi, sLo, dHi, dLo;
+ sHi = sLo = dHi = dLo = IRTemp_INVALID;
+ breakupV256toV128s( dV, &dHi, &dLo);
+ breakupV256toV128s( sV, &sHi, &sLo);
+ IRTemp res = newTemp(Ity_V256);
+ assign(res, binop(Iop_V128HLtoV256,
+ mkexpr(math_PMULDQ_128(sHi, dHi)),
+ mkexpr(math_PMULDQ_128(sLo, dLo))));
+ return res;
+}
+
+
static IRTemp math_PMADDWD_128 ( IRTemp dV, IRTemp sV )
{
IRTemp sVhi, sVlo, dVhi, dVlo;
@@ -10589,6 +10865,20 @@
}
+static IRTemp math_PMADDWD_256 ( IRTemp dV, IRTemp sV )
+{
+ IRTemp sHi, sLo, dHi, dLo;
+ sHi = sLo = dHi = dLo = IRTemp_INVALID;
+ breakupV256toV128s( dV, &dHi, &dLo);
+ breakupV256toV128s( sV, &sHi, &sLo);
+ IRTemp res = newTemp(Ity_V256);
+ assign(res, binop(Iop_V128HLtoV256,
+ mkexpr(math_PMADDWD_128(dHi, sHi)),
+ mkexpr(math_PMADDWD_128(dLo, sLo))));
+ return res;
+}
+
+
static IRTemp math_ADDSUBPD_128 ( IRTemp dV, IRTemp sV )
{
IRTemp addV = newTemp(Ity_V128);
@@ -10722,6 +11012,54 @@
}
+/* Handle 256 bit PSHUFLW and PSHUFHW. */
+static Long dis_PSHUFxW_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool xIsH )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt imm8;
+ IRTemp sV, s[8], sV64[4], dVhi, dVlo;
+ sV64[3] = sV64[2] = sV64[1] = sV64[0] = IRTemp_INVALID;
+ s[7] = s[6] = s[5] = s[4] = s[3] = s[2] = s[1] = s[0] = IRTemp_INVALID;
+ sV = newTemp(Ity_V256);
+ dVhi = newTemp(Ity_I64);
+ dVlo = newTemp(Ity_I64);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getYMMReg(rE) );
+ imm8 = (UInt)getUChar(delta+1);
+ delta += 1+1;
+ DIP("vpshuf%cw $%u,%s,%s\n", xIsH ? 'h' : 'l',
+ imm8, nameYMMReg(rE), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( sV, loadLE(Ity_V256, mkexpr(addr)) );
+ imm8 = (UInt)getUChar(delta+alen);
+ delta += alen+1;
+ DIP("vpshuf%cw $%u,%s,%s\n", xIsH ? 'h' : 'l',
+ imm8, dis_buf, nameYMMReg(rG));
+ }
+
+ breakupV256to64s( sV, &sV64[3], &sV64[2], &sV64[1], &sV64[0] );
+ breakup64to16s( sV64[xIsH ? 3 : 2], &s[7], &s[6], &s[5], &s[4] );
+ breakup64to16s( sV64[xIsH ? 1 : 0], &s[3], &s[2], &s[1], &s[0] );
+
+ assign( dVhi, mk64from16s( s[4 + ((imm8>>6)&3)], s[4 + ((imm8>>4)&3)],
+ s[4 + ((imm8>>2)&3)], s[4 + ((imm8>>0)&3)] ) );
+ assign( dVlo, mk64from16s( s[0 + ((imm8>>6)&3)], s[0 + ((imm8>>4)&3)],
+ s[0 + ((imm8>>2)&3)], s[0 + ((imm8>>0)&3)] ) );
+ putYMMReg( rG, mkV256from64s( xIsH ? dVhi : sV64[3],
+ xIsH ? sV64[2] : dVhi,
+ xIsH ? dVlo : sV64[1],
+ xIsH ? sV64[0] : dVlo ) );
+ return delta;
+}
+
+
static Long dis_PEXTRW_128_EregOnly_toG ( VexAbiInfo* vbi, Prefix pfx,
Long delta, Bool isAvx )
{
@@ -10932,6 +11270,20 @@
}
+static IRTemp math_PSADBW_256 ( IRTemp dV, IRTemp sV )
+{
+ IRTemp sHi, sLo, dHi, dLo;
+ sHi = sLo = dHi = dLo = IRTemp_INVALID;
+ breakupV256toV128s( dV, &dHi, &dLo);
+ breakupV256toV128s( sV, &sHi, &sLo);
+ IRTemp res = newTemp(Ity_V256);
+ assign(res, binop(Iop_V128HLtoV256,
+ mkexpr(math_PSADBW_128(dHi, sHi)),
+ mkexpr(math_PSADBW_128(dLo, sLo))));
+ return res;
+}
+
+
static Long dis_MASKMOVDQU ( VexAbiInfo* vbi, Prefix pfx,
Long delta, Bool isAvx )
{
@@ -14460,6 +14812,21 @@
}
+static
+IRTemp math_PSHUFB_YMM ( IRTemp dV/*data to perm*/, IRTemp sV/*perm*/ )
+{
+ IRTemp sHi, sLo, dHi, dLo;
+ sHi = sLo = dHi = dLo = IRTemp_INVALID;
+ breakupV256toV128s( dV, &dHi, &dLo);
+ breakupV256toV128s( sV, &sHi, &sLo);
+ IRTemp res = newTemp(Ity_V256);
+ assign(res, binop(Iop_V128HLtoV256,
+ mkexpr(math_PSHUFB_XMM(dHi, sHi)),
+ mkexpr(math_PSHUFB_XMM(dLo, sLo))));
+ return res;
+}
+
+
static Long dis_PHADD_128 ( VexAbiInfo* vbi, Prefix pfx, Long delta,
Bool isAvx, UChar opc )
{
@@ -14499,14 +14866,16 @@
if (epartIsReg(modrm)) {
UInt rE = eregOfRexRM(pfx,modrm);
assign( sV, getXMMReg(rE) );
- DIP("ph%s %s,%s\n", str, nameXMMReg(rE), nameXMMReg(rG));
+ DIP("%sph%s %s,%s\n", isAvx ? "v" : "", str,
+ nameXMMReg(rE), nameXMMReg(rG));
delta += 1;
} else {
addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
if (!isAvx)
gen_SEGV_if_not_16_aligned( addr );
assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- DIP("ph%s %s,%s\n", str, dis_buf, nameXMMReg(rG));
+ DIP("%sph%s %s,%s\n", isAvx ? "v" : "", str,
+ dis_buf, nameXMMReg(rG));
delta += alen;
}
@@ -14532,6 +14901,78 @@
}
+static Long dis_PHADD_256 ( VexAbiInfo* vbi, Prefix pfx, Long delta, UChar opc )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ HChar* str = "???";
+ IROp opV64 = Iop_INVALID;
+ IROp opCatO = Iop_CatOddLanes16x4;
+ IROp opCatE = Iop_CatEvenLanes16x4;
+ IRTemp sV = newTemp(Ity_V256);
+ IRTemp dV = newTemp(Ity_V256);
+ IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
+ s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+
+ switch (opc) {
+ case 0x01: opV64 = Iop_Add16x4; str = "addw"; break;
+ case 0x02: opV64 = Iop_Add32x2; str = "addd"; break;
+ case 0x03: opV64 = Iop_QAdd16Sx4; str = "addsw"; break;
+ case 0x05: opV64 = Iop_Sub16x4; str = "subw"; break;
+ case 0x06: opV64 = Iop_Sub32x2; str = "subd"; break;
+ case 0x07: opV64 = Iop_QSub16Sx4; str = "subsw"; break;
+ default: vassert(0);
+ }
+ if (opc == 0x02 || opc == 0x06) {
+ opCatO = Iop_InterleaveHI32x2;
+ opCatE = Iop_InterleaveLO32x2;
+ }
+
+ assign( dV, getYMMReg(rV) );
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getYMMReg(rE) );
+ DIP("vph%s %s,%s\n", str, nameYMMReg(rE), nameYMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V256, mkexpr(addr)) );
+ DIP("vph%s %s,%s\n", str, dis_buf, nameYMMReg(rG));
+ delta += alen;
+ }
+
+ breakupV256to64s( dV, &d3, &d2, &d1, &d0 );
+ breakupV256to64s( sV, &s3, &s2, &s1, &s0 );
+
+ /* This isn't a particularly efficient way to compute the
+ result, but at least it avoids a proliferation of IROps,
+ hence avoids complication all the backends. */
+
+ putYMMReg( rG,
+ binop(Iop_V128HLtoV256,
+ binop(Iop_64HLtoV128,
+ binop(opV64,
+ binop(opCatE,mkexpr(s3),mkexpr(s2)),
+ binop(opCatO,mkexpr(s3),mkexpr(s2)) ),
+ binop(opV64,
+ binop(opCatE,mkexpr(d3),mkexpr(d2)),
+ binop(opCatO,mkexpr(d3),mkexpr(d2)) ) ),
+ binop(Iop_64HLtoV128,
+ binop(opV64,
+ binop(opCatE,mkexpr(s1),mkexpr(s0)),
+ binop(opCatO,mkexpr(s1),mkexpr(s0)) ),
+ binop(opV64,
+ binop(opCatE,mkexpr(d1),mkexpr(d0)),
+ binop(opCatO,mkexpr(d1),mkexpr(d0)) ) ) ) );
+ return delta;
+}
+
+
static IRTemp math_PMADDUBSW_128 ( IRTemp dV, IRTemp sV )
{
IRTemp sVoddsSX = newTemp(Ity_V128);
@@ -14558,6 +14999,21 @@
}
+static
+IRTemp math_PMADDUBSW_256 ( IRTemp dV, IRTemp sV )
+{
+ IRTemp sHi, sLo, dHi, dLo;
+ sHi = sLo = dHi = dLo = IRTemp_INVALID;
+ breakupV256toV128s( dV, &dHi, &dLo);
+ breakupV256toV128s( sV, &sHi, &sLo);
+ IRTemp res = newTemp(Ity_V256);
+ assign(res, binop(Iop_V128HLtoV256,
+ mkexpr(math_PMADDUBSW_128(dHi, sHi)),
+ mkexpr(math_PMADDUBSW_128(dLo, sLo))));
+ return res;
+}
+
+
__attribute__((noinline))
static
Long dis_ESC_0F38__SupSSE3 ( Bool* decode_OK,
@@ -15266,32 +15722,31 @@
}
break;
- case 0xBD:
- /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension,
- which we can only decode if we're sure this is an AMD cpu
- that supports LZCNT, since otherwise it's BSR, which behaves
- differently. Bizarrely, my Sandy Bridge also accepts these
- instructions but produces different results. */
+ case 0xBC:
+ /* F3 0F BC -- TZCNT (count trailing zeroes. A BMI extension,
+ which we can only decode if we're sure this is a BMI1 capable cpu
+ that supports TZCNT, since otherwise it's BSF, which behaves
+ differently on zero source. */
if (haveF3noF2(pfx) /* so both 66 and 48 are possibilities */
- && (sz == 2 || sz == 4 || sz == 8)
- && 0 != (archinfo->hwcaps & VEX_HWCAPS_AMD64_LZCNT)) {
+ && (sz == 2 || sz == 4 || sz == 8)
+ && 0 != (archinfo->hwcaps & VEX_HWCAPS_AMD64_BMI)) {
/*IRType*/ ty = szToITy(sz);
IRTemp src = newTemp(ty);
modrm = getUChar(delta);
if (epartIsReg(modrm)) {
assign(src, getIRegE(sz, pfx, modrm));
delta += 1;
- DIP("lzcnt%c %s, %s\n", nameISize(sz), nameIRegE(sz, pfx, modrm),
+ DIP("tzcnt%c %s, %s\n", nameISize(sz), nameIRegE(sz, pfx, modrm),
nameIRegG(sz, pfx, modrm));
} else {
addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0);
assign(src, loadLE(ty, mkexpr(addr)));
delta += alen;
- DIP("lzcnt%c %s, %s\n", nameISize(sz), dis_buf,
+ DIP("tzcnt%c %s, %s\n", nameISize(sz), dis_buf,
nameIRegG(sz, pfx, modrm));
}
- IRTemp res = gen_LZCNT(ty, src);
+ IRTemp res = gen_TZCNT(ty, src);
putIRegG(sz, pfx, modrm, mkexpr(res));
// Update flags. This is pretty lame .. perhaps can do better
@@ -15327,7 +15782,68 @@
}
break;
- default:
+ case 0xBD:
+ /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension,
+ which we can only decode if we're sure this is an AMD cpu
+ that supports LZCNT, since otherwise it's BSR, which behaves
+ differently. Bizarrely, my Sandy Bridge also accepts these
+ instructions but produces different results. */
+ if (haveF3noF2(pfx) /* so both 66 and 48 are possibilities */
+ && (sz == 2 || sz == 4 || sz == 8)
+ && 0 != (archinfo->hwcaps & VEX_HWCAPS_AMD64_LZCNT)) {
+ /*IRType*/ ty = szToITy(sz);
+ IRTemp src = newTemp(ty);
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ assign(src, getIRegE(sz, pfx, modrm));
+ delta += 1;
+ DIP("lzcnt%c %s, %s\n", nameISize(sz), nameIRegE(sz, pfx, modrm),
+ nameIRegG(sz, pfx, modrm));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0);
+ assign(src, loadLE(ty, mkexpr(addr)));
+ delta += alen;
+ DIP("lzcnt%c %s, %s\n", nameISize(sz), dis_buf,
+ nameIRegG(sz, pfx, modrm));
+ }
+
+ IRTemp res = gen_LZCNT(ty, src);
+ putIRegG(sz, pfx, modrm, mkexpr(res));
+
+ // Update flags. This is pretty lame .. perhaps can do better
+ // if this turns out to be performance critical.
+ // O S A P are cleared. Z is set if RESULT == 0.
+ // C is set if SRC is zero.
+ IRTemp src64 = newTemp(Ity_I64);
+ IRTemp res64 = newTemp(Ity_I64);
+ assign(src64, widenUto64(mkexpr(src)));
+ assign(res64, widenUto64(mkexpr(res)));
+
+ IRTemp oszacp = newTemp(Ity_I64);
+ assign(
+ oszacp,
+ binop(Iop_Or64,
+ binop(Iop_Shl64,
+ unop(Iop_1Uto64,
+ binop(Iop_CmpEQ64, mkexpr(res64), mkU64(0))),
+ mkU8(AMD64G_CC_SHIFT_Z)),
+ binop(Iop_Shl64,
+ unop(Iop_1Uto64,
+ binop(Iop_CmpEQ64, mkexpr(src64), mkU64(0))),
+ mkU8(AMD64G_CC_SHIFT_C))
+ )
+ );
+
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(oszacp) ));
+
+ goto decode_success;
+ }
+ break;
+
+ default:
break;
}
@@ -15731,6 +16247,47 @@
}
+/* Handles 256 bit versions of PMOVZXBW and PMOVSXBW. */
+static Long dis_PMOVxXBW_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool xIsZ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcVec = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UChar how = xIsZ ? 'z' : 's';
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcVec, getXMMReg(rE) );
+ delta += 1;
+ DIP( "vpmov%cxbw %s,%s\n", how, nameXMMReg(rE), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcVec, loadLE( Ity_V128, mkexpr(addr) ) );
+ delta += alen;
+ DIP( "vpmov%cxbw %s,%s\n", how, dis_buf, nameYMMReg(rG) );
+ }
+
+ /* First do zero extend. */
+ IRExpr* res
+ = binop( Iop_V128HLtoV256,
+ binop( Iop_InterleaveHI8x16,
+ IRExpr_Const( IRConst_V128(0) ), mkexpr(srcVec) ),
+ binop( Iop_InterleaveLO8x16,
+ IRExpr_Const( IRConst_V128(0) ), mkexpr(srcVec) ) );
+ /* And if needed sign extension as well. */
+ if (!xIsZ)
+ res = binop( Iop_SarN16x16,
+ binop( Iop_ShlN16x16, res, mkU8(8) ), mkU8(8) );
+
+ putYMMReg ( rG, res );
+
+ return delta;
+}
+
+
static Long dis_PMOVxXWD_128 ( VexAbiInfo* vbi, Prefix pfx,
Long delta, Bool isAvx, Bool xIsZ )
{
@@ -15770,6 +16327,45 @@
}
+static Long dis_PMOVxXWD_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool xIsZ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcVec = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UChar how = xIsZ ? 'z' : 's';
+ UInt rG = gregOfRexRM(pfx, modrm);
+
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcVec, getXMMReg(rE) );
+ delta += 1;
+ DIP( "vpmov%cxwd %s,%s\n", how, nameXMMReg(rE), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcVec, loadLE( Ity_V128, mkexpr(addr) ) );
+ delta += alen;
+ DIP( "vpmov%cxwd %s,%s\n", how, dis_buf, nameYMMReg(rG) );
+ }
+
+ IRExpr* res
+ = binop( Iop_V128HLtoV256,
+ binop( Iop_InterleaveHI16x8,
+ IRExpr_Const( IRConst_V128(0) ), mkexpr(srcVec) ),
+ binop( Iop_InterleaveLO16x8,
+ IRExpr_Const( IRConst_V128(0) ), mkexpr(srcVec) ) );
+ if (!xIsZ)
+ res = binop(Iop_SarN32x8,
+ binop(Iop_ShlN32x8, res, mkU8(16)), mkU8(16));
+
+ putYMMReg ( rG, res );
+
+ return delta;
+}
+
+
static Long dis_PMOVSXWQ_128 ( VexAbiInfo* vbi, Prefix pfx,
Long delta, Bool isAvx )
{
@@ -15803,6 +16399,41 @@
}
+static Long dis_PMOVSXWQ_256 ( VexAbiInfo* vbi, Prefix pfx, Long delta )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcBytes = newTemp(Ity_I64);
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp s3, s2, s1, s0;
+ s3 = s2 = s1 = s0 = IRTemp_INVALID;
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcBytes, getXMMRegLane64( rE, 0 ) );
+ delta += 1;
+ DIP( "vpmovsxwq %s,%s\n", nameXMMReg(rE), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcBytes, loadLE( Ity_I64, mkexpr(addr) ) );
+ delta += alen;
+ DIP( "vpmovsxwq %s,%s\n", dis_buf, nameYMMReg(rG) );
+ }
+
+ breakup64to16s( srcBytes, &s3, &s2, &s1, &s0 );
+ putYMMReg( rG, binop( Iop_V128HLtoV256,
+ binop( Iop_64HLtoV128,
+ unop( Iop_16Sto64, mkexpr(s3) ),
+ unop( Iop_16Sto64, mkexpr(s2) ) ),
+ binop( Iop_64HLtoV128,
+ unop( Iop_16Sto64, mkexpr(s1) ),
+ unop( Iop_16Sto64, mkexpr(s0) ) ) ) );
+ return delta;
+}
+
+
static Long dis_PMOVZXWQ_128 ( VexAbiInfo* vbi, Prefix pfx,
Long delta, Bool isAvx )
{
@@ -15839,6 +16470,45 @@
}
+static Long dis_PMOVZXWQ_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcVec = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcVec, getXMMReg(rE) );
+ delta += 1;
+ DIP( "vpmovzxwq %s,%s\n", nameXMMReg(rE), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcVec,
+ unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) );
+ delta += alen;
+ DIP( "vpmovzxwq %s,%s\n", dis_buf, nameYMMReg(rG) );
+ }
+
+ IRTemp zeroVec = newTemp( Ity_V128 );
+ assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) );
+
+ putYMMReg( rG, binop( Iop_V128HLtoV256,
+ binop( Iop_InterleaveHI16x8,
+ mkexpr(zeroVec),
+ binop( Iop_InterleaveLO16x8,
+ mkexpr(zeroVec), mkexpr(srcVec) ) ),
+ binop( Iop_InterleaveLO16x8,
+ mkexpr(zeroVec),
+ binop( Iop_InterleaveLO16x8,
+ mkexpr(zeroVec), mkexpr(srcVec) ) ) ) );
+ return delta;
+}
+
+
/* Handles 128 bit versions of PMOVZXDQ and PMOVSXDQ. */
static Long dis_PMOVxXDQ_128 ( VexAbiInfo* vbi, Prefix pfx,
Long delta, Bool isAvx, Bool xIsZ )
@@ -15886,6 +16556,59 @@
}
+/* Handles 256 bit versions of PMOVZXDQ and PMOVSXDQ. */
+static Long dis_PMOVxXDQ_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool xIsZ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcVec = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UChar how = xIsZ ? 'z' : 's';
+ UInt rG = gregOfRexRM(pfx, modrm);
+ /* Compute both srcI64 -- the value to expand -- and srcVec -- same
+ thing in a V128, with arbitrary junk in the top 64 bits. Use
+ one or both of them and let iropt clean up afterwards (as
+ usual). */
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcVec, getXMMReg(rE) );
+ delta += 1;
+ DIP( "vpmov%cxdq %s,%s\n", how, nameXMMReg(rE), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcVec, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP( "vpmov%cxdq %s,%s\n", how, dis_buf, nameYMMReg(rG) );
+ }
+
+ IRExpr* res;
+ if (xIsZ)
+ res = binop( Iop_V128HLtoV256,
+ binop( Iop_InterleaveHI32x4,
+ IRExpr_Const( IRConst_V128(0) ), mkexpr(srcVec) ),
+ binop( Iop_InterleaveLO32x4,
+ IRExpr_Const( IRConst_V128(0) ), mkexpr(srcVec) ) );
+ else {
+ IRTemp s3, s2, s1, s0;
+ s3 = s2 = s1 = s0 = IRTemp_INVALID;
+ breakupV128to32s( srcVec, &s3, &s2, &s1, &s0 );
+ res = binop( Iop_V128HLtoV256,
+ binop( Iop_64HLtoV128,
+ unop( Iop_32Sto64, mkexpr(s3) ),
+ unop( Iop_32Sto64, mkexpr(s2) ) ),
+ binop( Iop_64HLtoV128,
+ unop( Iop_32Sto64, mkexpr(s1) ),
+ unop( Iop_32Sto64, mkexpr(s0) ) ) );
+ }
+
+ putYMMReg ( rG, res );
+
+ return delta;
+}
+
+
/* Handles 128 bit versions of PMOVZXBD and PMOVSXBD. */
static Long dis_PMOVxXBD_128 ( VexAbiInfo* vbi, Prefix pfx,
Long delta, Bool isAvx, Bool xIsZ )
@@ -15929,6 +16652,53 @@
}
+/* Handles 256 bit versions of PMOVZXBD and PMOVSXBD. */
+static Long dis_PMOVxXBD_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool xIsZ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcVec = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UChar how = xIsZ ? 'z' : 's';
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcVec, getXMMReg(rE) );
+ delta += 1;
+ DIP( "vpmov%cxbd %s,%s\n", how, nameXMMReg(rE), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcVec,
+ unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) );
+ delta += alen;
+ DIP( "vpmov%cxbd %s,%s\n", how, dis_buf, nameYMMReg(rG) );
+ }
+
+ IRTemp zeroVec = newTemp(Ity_V128);
+ assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) );
+
+ IRExpr* res
+ = binop( Iop_V128HLtoV256,
+ binop(Iop_InterleaveHI8x16,
+ mkexpr(zeroVec),
+ binop(Iop_InterleaveLO8x16,
+ mkexpr(zeroVec), mkexpr(srcVec)) ),
+ binop(Iop_InterleaveLO8x16,
+ mkexpr(zeroVec),
+ binop(Iop_InterleaveLO8x16,
+ mkexpr(zeroVec), mkexpr(srcVec)) ) );
+ if (!xIsZ)
+ res = binop(Iop_SarN32x8,
+ binop(Iop_ShlN32x8, res, mkU8(24)), mkU8(24));
+
+ putYMMReg ( rG, res );
+
+ return delta;
+}
+
+
/* Handles 128 bit versions of PMOVSXBQ. */
static Long dis_PMOVSXBQ_128 ( VexAbiInfo* vbi, Prefix pfx,
Long delta, Bool isAvx )
@@ -15962,6 +16732,52 @@
}
+/* Handles 256 bit versions of PMOVSXBQ. */
+static Long dis_PMOVSXBQ_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcBytes = newTemp(Ity_I32);
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcBytes, getXMMRegLane32( rE, 0 ) );
+ delta += 1;
+ DIP( "vpmovsxbq %s,%s\n", nameXMMReg(rE), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcBytes, loadLE( Ity_I32, mkexpr(addr) ) );
+ delta += alen;
+ DIP( "vpmovsxbq %s,%s\n", dis_buf, nameYMMReg(rG) );
+ }
+
+ putYMMReg
+ ( rG, binop( Iop_V128HLtoV256,
+ binop( Iop_64HLtoV128,
+ unop( Iop_8Sto64,
+ unop( Iop_16HIto8,
+ unop( Iop_32HIto16,
+ mkexpr(srcBytes) ) ) ),
+ unop( Iop_8Sto64,
+ unop( Iop_16to8,
+ unop( Iop_32HIto16,
+ mkexpr(srcBytes) ) ) ) ),
+ binop( Iop_64HLtoV128,
+ unop( Iop_8Sto64,
+ unop( Iop_16HIto8,
+ unop( Iop_32to16,
+ mkexpr(srcBytes) ) ) ),
+ unop( Iop_8Sto64,
+ unop( Iop_16to8,
+ unop( Iop_32to16,
+ mkexpr(srcBytes) ) ) ) ) ) );
+ return delta;
+}
+
+
/* Handles 128 bit versions of PMOVZXBQ. */
static Long dis_PMOVZXBQ_128 ( VexAbiInfo* vbi, Prefix pfx,
Long delta, Bool isAvx )
@@ -16001,21 +16817,66 @@
}
-static Long dis_PHMINPOSUW_128 ( VexAbiInfo* vbi, Prefix pfx,
- Long delta, Bool isAvx )
+/* Handles 256 bit versions of PMOVZXBQ. */
+static Long dis_PMOVZXBQ_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta )
{
- IRTemp addr = IRTemp_INVALID;
- Int alen = 0;
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
HChar dis_buf[50];
- UChar modrm = getUChar(delta);
- UChar* mbV = isAvx ? "v" : "";
- IRTemp sV = newTemp(Ity_V128);
- IRTemp sHi = newTemp(Ity_I64);
- IRTemp sLo = newTemp(Ity_I64);
- IRTemp dLo = newTemp(Ity_I64);
- UInt rG = gregOfRexRM(pfx,modrm);
- if (epartIsReg(modrm)) {
- UInt rE = eregOfRexRM(pfx,modrm);
+ IRTemp srcVec = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcVec, getXMMReg(rE) );
+ delta += 1;
+ DIP( "vpmovzxbq %s,%s\n", nameXMMReg(rE), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcVec,
+ unop( Iop_32UtoV128, loadLE( Ity_I32, mkexpr(addr) )));
+ delta += alen;
+ DIP( "vpmovzxbq %s,%s\n", dis_buf, nameYMMReg(rG) );
+ }
+
+ IRTemp zeroVec = newTemp(Ity_V128);
+ assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) );
+
+ putYMMReg
+ ( rG, binop( Iop_V128HLtoV256,
+ binop( Iop_InterleaveHI8x16,
+ mkexpr(zeroVec),
+ binop( Iop_InterleaveLO8x16,
+ mkexpr(zeroVec),
+ binop( Iop_InterleaveLO8x16,
+ mkexpr(zeroVec), mkexpr(srcVec) ) ) ),
+ binop( Iop_InterleaveLO8x16,
+ mkexpr(zeroVec),
+ binop( Iop_InterleaveLO8x16,
+ mkexpr(zeroVec),
+ binop( Iop_InterleaveLO8x16,
+ mkexpr(zeroVec), mkexpr(srcVec) ) ) )
+ ) );
+ return delta;
+}
+
+
+static Long dis_PHMINPOSUW_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ UChar* mbV = isAvx ? "v" : "";
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
assign( sV, getXMMReg(rE) );
delta += 1;
DIP("%sphminposuw %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG));
@@ -20062,9 +20923,17 @@
return delta;
case 0xBC: /* BSF Gv,Ev */
- if (haveF2(pfx)) goto decode_failure;
- delta = dis_bs_E_G ( vbi, pfx, sz, delta, True );
- return delta;
+ if (!haveF2orF3(pfx)
+ || (haveF3noF2(pfx)
+ && 0 == (archinfo->hwcaps & VEX_HWCAPS_AMD64_BMI))) {
+ /* no-F2 no-F3 0F BC = BSF
+ or F3 0F BC = REP; BSF on older CPUs. */
+ delta = dis_bs_E_G ( vbi, pfx, sz, delta, True );
+ return delta;
+ }
+ /* Fall through, since F3 0F BC is TZCNT, and needs to
+ be handled by dis_ESC_0F__SSE4. */
+ break;
case 0xBD: /* BSR Gv,Ev */
if (!haveF2orF3(pfx)
@@ -20711,6 +21580,194 @@
}
+/* Vector by scalar shift of V by the amount specified at the bottom
+ of E. */
+static ULong dis_AVX256_shiftV_byE ( VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, IROp op )
+{
+ HChar dis_buf[50];
+ Int alen, size;
+ IRTemp addr;
+ Bool shl, shr, sar;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);;
+ IRTemp g0 = newTemp(Ity_V256);
+ IRTemp g1 = newTemp(Ity_V256);
+ IRTemp amt = newTemp(Ity_I64);
+ IRTemp amt8 = newTemp(Ity_I8);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( amt, getXMMRegLane64(rE, 0) );
+ DIP("%s %s,%s,%s\n", opname, nameXMMReg(rE),
+ nameYMMReg(rV), nameYMMReg(rG) );
+ delta++;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( amt, loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("%s %s,%s,%s\n", opname, dis_buf, nameYMMReg(rV), nameYMMReg(rG) );
+ delta += alen;
+ }
+ assign( g0, getYMMReg(rV) );
+ assign( amt8, unop(Iop_64to8, mkexpr(amt)) );
+
+ shl = shr = sar = False;
+ size = 0;
+ switch (op) {
+ case Iop_ShlN16x16: shl = True; size = 32; break;
+ case Iop_ShlN32x8: shl = True; size = 32; break;
+ case Iop_ShlN64x4: shl = True; size = 64; break;
+ case Iop_SarN16x16: sar = True; size = 16; break;
+ case Iop_SarN32x8: sar = True; size = 32; break;
+ case Iop_ShrN16x16: shr = True; size = 16; break;
+ case Iop_ShrN32x8: shr = True; size = 32; break;
+ case Iop_ShrN64x4: shr = True; size = 64; break;
+ default: vassert(0);
+ }
+
+ if (shl || shr) {
+ assign(
+ g1,
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(Iop_CmpLT64U, mkexpr(amt), mkU64(size))),
+ binop(Iop_V128HLtoV256, mkV128(0), mkV128(0)),
+ binop(op, mkexpr(g0), mkexpr(amt8))
+ )
+ );
+ } else
+ if (sar) {
+ assign(
+ g1,
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(Iop_CmpLT64U, mkexpr(amt), mkU64(size))),
+ binop(op, mkexpr(g0), mkU8(size-1)),
+ binop(op, mkexpr(g0), mkexpr(amt8))
+ )
+ );
+ } else {
+ vassert(0);
+ }
+
+ putYMMReg( rG, mkexpr(g1) );
+ return delta;
+}
+
+
+/* Vector by vector shift of V by the amount specified at the bottom
+ of E. Vector by vector shifts are defined for all shift amounts,
+ so not using Iop_S*x* here (and SSE2 doesn't support variable shifts
+ anyway). */
+static ULong dis_AVX_var_shiftV_byE ( VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, IROp op, Bool isYMM )
+{
+ HChar dis_buf[50];
+ Int alen, size, i;
+ IRTemp addr;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);;
+ IRTemp sV = isYMM ? newTemp(Ity_V256) : newTemp(Ity_V128);
+ IRTemp amt = isYMM ? newTemp(Ity_V256) : newTemp(Ity_V128);
+ IRTemp amts[8], sVs[8], res[8];
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( amt, isYMM ? getYMMReg(rE) : getXMMReg(rE) );
+ if (isYMM) {
+ DIP("%s %s,%s,%s\n", opname, nameYMMReg(rE),
+ nameYMMReg(rV), nameYMMReg(rG) );
+ } else {
+ DIP("%s %s,%s,%s\n", opname, nameXMMReg(rE),
+ nameXMMReg(rV), nameXMMReg(rG) );
+ }
+ delta++;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( amt, loadLE(isYMM ? Ity_V256 : Ity_V128, mkexpr(addr)) );
+ if (isYMM) {
+ DIP("%s %s,%s,%s\n", opname, dis_buf, nameYMMReg(rV),
+ nameYMMReg(rG) );
+ } else {
+ DIP("%s %s,%s,%s\n", opname, dis_buf, nameXMMReg(rV),
+ nameXMMReg(rG) );
+ }
+ delta += alen;
+ }
+ assign( sV, isYMM ? getYMMReg(rV) : getXMMReg(rV) );
+
+ size = 0;
+ switch (op) {
+ case Iop_Shl32: size = 32; break;
+ case Iop_Shl64: size = 64; break;
+ case Iop_Sar32: size = 32; break;
+ case Iop_Shr32: size = 32; break;
+ case Iop_Shr64: size = 64; break;
+ default: vassert(0);
+ }
+
+ for (i = 0; i < 8; i++) {
+ sVs[i] = IRTemp_INVALID;
+ amts[i] = IRTemp_INVALID;
+ }
+ switch (size) {
+ case 32:
+ if (isYMM) {
+ breakupV256to32s( sV, &sVs[7], &sVs[6], &sVs[5], &sVs[4],
+ &sVs[3], &sVs[2], &sVs[1], &sVs[0] );
+ breakupV256to32s( amt, &amts[7], &amts[6], &amts[5], &amts[4],
+ &amts[3], &amts[2], &amts[1], &amts[0] );
+ } else {
+ breakupV128to32s( sV, &sVs[3], &sVs[2], &sVs[1], &sVs[0] );
+ breakupV128to32s( amt, &amts[3], &amts[2], &amts[1], &amts[0] );
+ }
+ break;
+ case 64:
+ if (isYMM) {
+ breakupV256to64s( sV, &sVs[3], &sVs[2], &sVs[1], &sVs[0] );
+ breakupV256to64s( amt, &amts[3], &amts[2], &amts[1], &amts[0] );
+ } else {
+ breakupV128to64s( sV, &sVs[1], &sVs[0] );
+ breakupV128to64s( amt, &amts[1], &amts[0] );
+ }
+ break;
+ default: vassert(0);
+ }
+ for (i = 0; i < 8; i++)
+ if (sVs[i] != IRTemp_INVALID) {
+ res[i] = size == 32 ? newTemp(Ity_I32) : newTemp(Ity_I64);
+ assign( res[i],
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(size == 32 ? Iop_CmpLT32U : Iop_CmpLT64U,
+ mkexpr(amts[i]),
+ size == 32 ? mkU32(size) : mkU64(size))),
+ op == Iop_Sar32 ? binop(op, mkexpr(sVs[i]), mkU8(size-1))
+ : size == 32 ? mkU32(0) : mkU64(0),
+ binop(op, mkexpr(sVs[i]),
+ unop(size == 32 ? Iop_32to8 : Iop_64to8,
+ mkexpr(amts[i]))) ) );
+ }
+ switch (size) {
+ case 32:
+ for (i = 0; i < 8; i++)
+ putYMMRegLane32( rG, i, (i < 4 || isYMM)
+ ? mkexpr(res[i]) : mkU32(0) );
+ break;
+ case 64:
+ for (i = 0; i < 4; i++)
+ putYMMRegLane64( rG, i, (i < 2 || isYMM)
+ ? mkexpr(res[i]) : mkU64(0) );
+ break;
+ default: vassert(0);
+ }
+
+ return delta;
+}
+
+
/* Vector by scalar shift of E into V, by an immediate byte. Modified
version of dis_SSE_shiftE_imm. */
static
@@ -20768,6 +21825,64 @@
}
+/* Vector by scalar shift of E into V, by an immediate byte. Modified
+ version of dis_AVX128_shiftE_to_V_imm. */
+static
+Long dis_AVX256_shiftE_to_V_imm( Prefix pfx,
+ Long delta, HChar* opname, IROp op )
+{
+ Bool shl, shr, sar;
+ UChar rm = getUChar(delta);
+ IRTemp e0 = newTemp(Ity_V256);
+ IRTemp e1 = newTemp(Ity_V256);
+ UInt rD = getVexNvvvv(pfx);
+ UChar amt, size;
+ vassert(epartIsReg(rm));
+ vassert(gregLO3ofRM(rm) == 2
+ || gregLO3ofRM(rm) == 4 || gregLO3ofRM(rm) == 6);
+ amt = getUChar(delta+1);
+ delta += 2;
+ DIP("%s $%d,%s,%s\n", opname,
+ (Int)amt,
+ nameYMMReg(eregOfRexRM(pfx,rm)),
+ nameYMMReg(rD));
+ assign( e0, getYMMReg(eregOfRexRM(pfx,rm)) );
+
+ shl = shr = sar = False;
+ size = 0;
+ switch (op) {
+ case Iop_ShlN16x16: shl = True; size = 16; break;
+ case Iop_ShlN32x8: shl = True; size = 32; break;
+ case Iop_ShlN64x4: shl = True; size = 64; break;
+ case Iop_SarN16x16: sar = True; size = 16; break;
+ case Iop_SarN32x8: sar = True; size = 32; break;
+ case Iop_ShrN16x16: shr = True; size = 16; break;
+ case Iop_ShrN32x8: shr = True; size = 32; break;
+ case Iop_ShrN64x4: shr = True; size = 64; break;
+ default: vassert(0);
+ }
+
+
+ if (shl || shr) {
+ assign( e1, amt >= size
+ ? binop(Iop_V128HLtoV256, mkV128(0), mkV128(0))
+ : binop(op, mkexpr(e0), mkU8(amt))
+ );
+ } else
+ if (sar) {
+ assign( e1, amt >= size
+ ? binop(op, mkexpr(e0), mkU8(size-1))
+ : binop(op, mkexpr(e0), mkU8(amt))
+ );
+ } else {
+ vassert(0);
+ }
+
+ putYMMReg( rD, mkexpr(e1) );
+ return delta;
+}
+
+
/* Lower 64-bit lane only AVX128 binary operation:
G[63:0] = V[63:0] `op` E[63:0]
G[127:64] = V[127:64]
@@ -21281,6 +22396,21 @@
}
+/* Handle a VEX_NDS_256_66_0F_WIG (3-addr) insn, with a simple IROp
+ for the operation, no inversion of the left arg, and no swapping of
+ args. */
+static
+Long dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple (
+ /*OUT*/Bool* uses_vvvv, VexAbiInfo* vbi,
+ Prefix pfx, Long delta, HChar* name,
+ IROp op
+ )
+{
+ return dis_VEX_NDS_256_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, name, op, NULL, False, False);
+}
+
+
/* Handle a VEX_NDS_256_66_0F_WIG (3-addr) insn, using the given IR
generator to compute the result, no inversion of the left
arg, and no swapping of args. */
@@ -21299,6 +22429,39 @@
/* Handles AVX256 unary E-to-G all-lanes operations. */
static
+Long dis_AVX256_E_to_G_unary ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname,
+ IRTemp (*opFn)(IRTemp) )
+{
+ HChar dis_buf[50];
+ Int alen;
+ IRTemp addr;
+ IRTemp res = newTemp(Ity_V256);
+ IRTemp arg = newTemp(Ity_V256);
+ UChar rm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, rm);
+ if (epartIsReg(rm)) {
+ UInt rE = eregOfRexRM(pfx,rm);
+ assign(arg, getYMMReg(rE));
+ delta += 1;
+ DIP("%s %s,%s\n", opname, nameYMMReg(rE), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(arg, loadLE(Ity_V256, mkexpr(addr)));
+ delta += alen;
+ DIP("%s %s,%s\n", opname, dis_buf, nameYMMReg(rG));
+ }
+ res = opFn(arg);
+ putYMMReg( rG, mkexpr(res) );
+ *uses_vvvv = False;
+ return delta;
+}
+
+
+/* Handles AVX256 unary E-to-G all-lanes operations. */
+static
Long dis_AVX256_E_to_G_unary_all ( /*OUT*/Bool* uses_vvvv,
VexAbiInfo* vbi,
Prefix pfx, Long delta,
@@ -21403,33 +22566,119 @@
}
-__attribute__((noinline))
-static
-Long dis_ESC_0F__VEX (
- /*MB_OUT*/DisResult* dres,
- /*OUT*/ Bool* uses_vvvv,
- Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
- Bool resteerCisOk,
- void* callback_opaque,
- VexArchInfo* archinfo,
- VexAbiInfo* vbi,
- Prefix pfx, Int sz, Long deltaIN
- )
+static IRTemp math_VPUNPCK_YMM ( IRTemp tL, IRType tR, IROp op )
{
- IRTemp addr = IRTemp_INVALID;
- Int alen = 0;
- HChar dis_buf[50];
- Long delta = deltaIN;
- UChar opc = getUChar(delta);
- delta++;
- *uses_vvvv = False;
+ IRTemp tLhi, tLlo, tRhi, tRlo;
+ tLhi = tLlo = tRhi = tRlo = IRTemp_INVALID;
+ IRTemp res = newTemp(Ity_V256);
+ breakupV256toV128s( tL, &tLhi, &tLlo );
+ breakupV256toV128s( tR, &tRhi, &tRlo );
+ assign( res, binop( Iop_V128HLtoV256,
+ binop( op, mkexpr(tRhi), mkexpr(tLhi) ),
+ binop( op, mkexpr(tRlo), mkexpr(tLlo) ) ) );
+ return res;
+}
- switch (opc) {
- case 0x10:
- /* VMOVSD m64, xmm1 = VEX.LIG.F2.0F.WIG 10 /r */
- /* Move 64 bits from E (mem only) to G (lo half xmm).
- Bits 255-64 of the dest are zeroed out. */
+static IRTemp math_VPUNPCKLBW_YMM ( IRTemp tL, IRTemp tR )
+{
+ return math_VPUNPCK_YMM( tL, tR, Iop_InterleaveLO8x16 );
+}
+
+
+static IRTemp math_VPUNPCKLWD_YMM ( IRTemp tL, IRTemp tR )
+{
+ return math_VPUNPCK_YMM( tL, tR, Iop_InterleaveLO16x8 );
+}
+
+
+static IRTemp math_VPUNPCKLDQ_YMM ( IRTemp tL, IRTemp tR )
+{
+ return math_VPUNPCK_YMM( tL, tR, Iop_InterleaveLO32x4 );
+}
+
+
+static IRTemp math_VPUNPCKLQDQ_YMM ( IRTemp tL, IRTemp tR )
+{
+ return math_VPUNPCK_YMM( tL, tR, Iop_InterleaveLO64x2 );
+}
+
+
+static IRTemp math_VPUNPCKHBW_YMM ( IRTemp tL, IRTemp tR )
+{
+ return math_VPUNPCK_YMM( tL, tR, Iop_InterleaveHI8x16 );
+}
+
+
+static IRTemp math_VPUNPCKHWD_YMM ( IRTemp tL, IRTemp tR )
+{
+ return math_VPUNPCK_YMM( tL, tR, Iop_InterleaveHI16x8 );
+}
+
+
+static IRTemp math_VPUNPCKHDQ_YMM ( IRTemp tL, IRTemp tR )
+{
+ return math_VPUNPCK_YMM( tL, tR, Iop_InterleaveHI32x4 );
+}
+
+
+static IRTemp math_VPUNPCKHQDQ_YMM ( IRTemp tL, IRTemp tR )
+{
+ return math_VPUNPCK_YMM( tL, tR, Iop_InterleaveHI64x2 );
+}
+
+
+static IRTemp math_VPACKSSWB_YMM ( IRTemp tL, IRTemp tR )
+{
+ return math_VPUNPCK_YMM( tL, tR, Iop_QNarrowBin16Sto8Sx16 );
+}
+
+
+static IRTemp math_VPACKUSWB_YMM ( IRTemp tL, IRTemp tR )
+{
+ return math_VPUNPCK_YMM( tL, tR, Iop_QNarrowBin16Sto8Ux16 );
+}
+
+
+static IRTemp math_VPACKSSDW_YMM ( IRTemp tL, IRTemp tR )
+{
+ return math_VPUNPCK_YMM( tL, tR, Iop_QNarrowBin32Sto16Sx8 );
+}
+
+
+static IRTemp math_VPACKUSDW_YMM ( IRTemp tL, IRTemp tR )
+{
+ return math_VPUNPCK_YMM( tL, tR, Iop_QNarrowBin32Sto16Ux8 );
+}
+
+
+__attribute__((noinline))
+static
+Long dis_ESC_0F__VEX (
+ /*MB_OUT*/DisResult* dres,
+ /*OUT*/ Bool* uses_vvvv,
+ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ VexArchInfo* archinfo,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN
+ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ *uses_vvvv = False;
+
+ switch (opc) {
+
+ case 0x10:
+ /* VMOVSD m64, xmm1 = VEX.LIG.F2.0F.WIG 10 /r */
+ /* Move 64 bits from E (mem only) to G (lo half xmm).
+ Bits 255-64 of the dest are zeroed out. */
if (haveF2no66noF3(pfx) && !epartIsReg(getUChar(delta))) {
UChar modrm = getUChar(delta);
addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
@@ -22926,6 +24175,14 @@
False/*!invertLeftArg*/, True/*swapArgs*/ );
goto decode_success;
}
+ /* VPUNPCKLBW r/m, rV, r ::: r = interleave-lo-bytes(rV, r/m) */
+ /* VPUNPCKLBW = VEX.NDS.256.66.0F.WIG 60 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpunpcklbw",
+ math_VPUNPCKLBW_YMM );
+ goto decode_success;
+ }
break;
case 0x61:
@@ -22938,6 +24195,14 @@
False/*!invertLeftArg*/, True/*swapArgs*/ );
goto decode_success;
}
+ /* VPUNPCKLWD r/m, rV, r ::: r = interleave-lo-words(rV, r/m) */
+ /* VPUNPCKLWD = VEX.NDS.256.66.0F.WIG 61 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpunpcklwd",
+ math_VPUNPCKLWD_YMM );
+ goto decode_success;
+ }
break;
case 0x62:
@@ -22950,6 +24215,14 @@
False/*!invertLeftArg*/, True/*swapArgs*/ );
goto decode_success;
}
+ /* VPUNPCKLDQ r/m, rV, r ::: r = interleave-lo-dwords(rV, r/m) */
+ /* VPUNPCKLDQ = VEX.NDS.256.66.0F.WIG 62 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpunpckldq",
+ math_VPUNPCKLDQ_YMM );
+ goto decode_success;
+ }
break;
case 0x63:
@@ -22962,6 +24235,14 @@
False/*!invertLeftArg*/, True/*swapArgs*/ );
goto decode_success;
}
+ /* VPACKSSWB r/m, rV, r ::: r = QNarrowBin16Sto8Sx16(rV, r/m) */
+ /* VPACKSSWB = VEX.NDS.256.66.0F.WIG 63 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpacksswb",
+ math_VPACKSSWB_YMM );
+ goto decode_success;
+ }
break;
case 0x64:
@@ -22972,6 +24253,13 @@
uses_vvvv, vbi, pfx, delta, "vpcmpgtb", Iop_CmpGT8Sx16 );
goto decode_success;
}
+ /* VPCMPGTB r/m, rV, r ::: r = rV `>s-by-8s` r/m */
+ /* VPCMPGTB = VEX.NDS.256.66.0F.WIG 64 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpgtb", Iop_CmpGT8Sx32 );
+ goto decode_success;
+ }
break;
case 0x65:
@@ -22982,6 +24270,13 @@
uses_vvvv, vbi, pfx, delta, "vpcmpgtw", Iop_CmpGT16Sx8 );
goto decode_success;
}
+ /* VPCMPGTW r/m, rV, r ::: r = rV `>s-by-16s` r/m */
+ /* VPCMPGTW = VEX.NDS.256.66.0F.WIG 65 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpgtw", Iop_CmpGT16Sx16 );
+ goto decode_success;
+ }
break;
case 0x66:
@@ -22992,6 +24287,13 @@
uses_vvvv, vbi, pfx, delta, "vpcmpgtd", Iop_CmpGT32Sx4 );
goto decode_success;
}
+ /* VPCMPGTD r/m, rV, r ::: r = rV `>s-by-32s` r/m */
+ /* VPCMPGTD = VEX.NDS.256.66.0F.WIG 66 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpgtd", Iop_CmpGT32Sx8 );
+ goto decode_success;
+ }
break;
case 0x67:
@@ -23004,6 +24306,14 @@
False/*!invertLeftArg*/, True/*swapArgs*/ );
goto decode_success;
}
+ /* VPACKUSWB r/m, rV, r ::: r = QNarrowBin16Sto8Ux16(rV, r/m) */
+ /* VPACKUSWB = VEX.NDS.256.66.0F.WIG 67 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpackuswb",
+ math_VPACKUSWB_YMM );
+ goto decode_success;
+ }
break;
case 0x68:
@@ -23016,6 +24326,14 @@
False/*!invertLeftArg*/, True/*swapArgs*/ );
goto decode_success;
}
+ /* VPUNPCKHBW r/m, rV, r ::: r = interleave-hi-bytes(rV, r/m) */
+ /* VPUNPCKHBW = VEX.NDS.256.0F.WIG 68 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpunpckhbw",
+ math_VPUNPCKHBW_YMM );
+ goto decode_success;
+ }
break;
case 0x69:
@@ -23028,6 +24346,14 @@
False/*!invertLeftArg*/, True/*swapArgs*/ );
goto decode_success;
}
+ /* VPUNPCKHWD r/m, rV, r ::: r = interleave-hi-words(rV, r/m) */
+ /* VPUNPCKHWD = VEX.NDS.256.0F.WIG 69 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpunpckhwd",
+ math_VPUNPCKHWD_YMM );
+ goto decode_success;
+ }
break;
case 0x6A:
@@ -23040,6 +24366,14 @@
False/*!invertLeftArg*/, True/*swapArgs*/ );
goto decode_success;
}
+ /* VPUNPCKHDQ r/m, rV, r ::: r = interleave-hi-dwords(rV, r/m) */
+ /* VPUNPCKHDQ = VEX.NDS.256.66.0F.WIG 6A /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpunpckhdq",
+ math_VPUNPCKHDQ_YMM );
+ goto decode_success;
+ }
break;
case 0x6B:
@@ -23052,6 +24386,14 @@
False/*!invertLeftArg*/, True/*swapArgs*/ );
goto decode_success;
}
+ /* VPACKSSDW r/m, rV, r ::: r = QNarrowBin32Sto16Sx8(rV, r/m) */
+ /* VPACKSSDW = VEX.NDS.256.66.0F.WIG 6B /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpackssdw",
+ math_VPACKSSDW_YMM );
+ goto decode_success;
+ }
break;
case 0x6C:
@@ -23064,6 +24406,14 @@
False/*!invertLeftArg*/, True/*swapArgs*/ );
goto decode_success;
}
+ /* VPUNPCKLQDQ r/m, rV, r ::: r = interleave-lo-64bitses(rV, r/m) */
+ /* VPUNPCKLQDQ = VEX.NDS.256.0F.WIG 6C /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpunpcklqdq",
+ math_VPUNPCKLQDQ_YMM );
+ goto decode_success;
+ }
break;
case 0x6D:
@@ -23076,6 +24426,14 @@
False/*!invertLeftArg*/, True/*swapArgs*/ );
goto decode_success;
}
+ /* VPUNPCKHQDQ r/m, rV, r ::: r = interleave-hi-64bitses(rV, r/m) */
+ /* VPUNPCKHQDQ = VEX.NDS.256.0F.WIG 6D /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpunpckhqdq",
+ math_VPUNPCKHQDQ_YMM );
+ goto decode_success;
+ }
break;
case 0x6E:
@@ -23190,18 +24548,33 @@
delta = dis_PSHUFD_32x4( vbi, pfx, delta, True/*writesYmm*/);
goto decode_success;
}
+ /* VPSHUFD imm8, ymm2/m256, ymm1 = VEX.256.66.0F.WIG 70 /r ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PSHUFD_32x8( vbi, pfx, delta);
+ goto decode_success;
+ }
/* VPSHUFLW imm8, xmm2/m128, xmm1 = VEX.128.F2.0F.WIG 70 /r ib */
if (haveF2no66noF3(pfx) && 0==getVexL(pfx)/*128*/) {
delta = dis_PSHUFxW_128( vbi, pfx, delta,
True/*isAvx*/, False/*!xIsH*/ );
goto decode_success;
}
+ /* VPSHUFLW imm8, ymm2/m256, ymm1 = VEX.256.F2.0F.WIG 70 /r ib */
+ if (haveF2no66noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PSHUFxW_256( vbi, pfx, delta, False/*!xIsH*/ );
+ goto decode_success;
+ }
/* VPSHUFHW imm8, xmm2/m128, xmm1 = VEX.128.F3.0F.WIG 70 /r ib */
if (haveF3no66noF2(pfx) && 0==getVexL(pfx)/*128*/) {
delta = dis_PSHUFxW_128( vbi, pfx, delta,
True/*isAvx*/, True/*xIsH*/ );
goto decode_success;
}
+ /* VPSHUFHW imm8, ymm2/m256, ymm1 = VEX.256.F3.0F.WIG 70 /r ib */
+ if (haveF3no66noF2(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PSHUFxW_256( vbi, pfx, delta, True/*xIsH*/ );
+ goto decode_success;
+ }
break;
case 0x71:
@@ -23231,6 +24604,32 @@
}
/* else fall through */
}
+ /* VPSRLW imm8, ymm2, ymm1 = VEX.NDD.256.66.0F.WIG 71 /2 ib */
+ /* VPSRAW imm8, ymm2, ymm1 = VEX.NDD.256.66.0F.WIG 71 /4 ib */
+ /* VPSLLW imm8, ymm2, ymm1 = VEX.NDD.256.66.0F.WIG 71 /6 ib */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/
+ && epartIsReg(getUChar(delta))) {
+ if (gregLO3ofRM(getUChar(delta)) == 2/*SRL*/) {
+ delta = dis_AVX256_shiftE_to_V_imm( pfx, delta,
+ "vpsrlw", Iop_ShrN16x16 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 4/*SRA*/) {
+ delta = dis_AVX256_shiftE_to_V_imm( pfx, delta,
+ "vpsraw", Iop_SarN16x16 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 6/*SLL*/) {
+ delta = dis_AVX256_shiftE_to_V_imm( pfx, delta,
+ "vpsllw", Iop_ShlN16x16 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* else fall through */
+ }
break;
case 0x72:
@@ -23260,6 +24659,32 @@
}
/* else fall through */
}
+ /* VPSRLD imm8, ymm2, ymm1 = VEX.NDD.256.66.0F.WIG 72 /2 ib */
+ /* VPSRAD imm8, ymm2, ymm1 = VEX.NDD.256.66.0F.WIG 72 /4 ib */
+ /* VPSLLD imm8, ymm2, ymm1 = VEX.NDD.256.66.0F.WIG 72 /6 ib */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/
+ && epartIsReg(getUChar(delta))) {
+ if (gregLO3ofRM(getUChar(delta)) == 2/*SRL*/) {
+ delta = dis_AVX256_shiftE_to_V_imm( pfx, delta,
+ "vpsrld", Iop_ShrN32x8 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 4/*SRA*/) {
+ delta = dis_AVX256_shiftE_to_V_imm( pfx, delta,
+ "vpsrad", Iop_SarN32x8 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 6/*SLL*/) {
+ delta = dis_AVX256_shiftE_to_V_imm( pfx, delta,
+ "vpslld", Iop_ShlN32x8 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* else fall through */
+ }
break;
case 0x73:
@@ -23304,6 +24729,54 @@
}
/* else fall through */
}
+ /* VPSRLDQ imm8, ymm2, ymm1 = VEX.NDD.256.66.0F.WIG 73 /3 ib */
+ /* VPSLLDQ imm8, ymm2, ymm1 = VEX.NDD.256.66.0F.WIG 73 /7 ib */
+ /* VPSRLQ imm8, ymm2, ymm1 = VEX.NDD.256.66.0F.WIG 73 /2 ib */
+ /* VPSLLQ imm8, ymm2, ymm1 = VEX.NDD.256.66.0F.WIG 73 /6 ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && epartIsReg(getUChar(delta))) {
+ Int rS = eregOfRexRM(pfx,getUChar(delta));
+ Int rD = getVexNvvvv(pfx);
+ if (gregLO3ofRM(getUChar(delta)) == 3) {
+ IRTemp vecS0 = newTemp(Ity_V128);
+ IRTemp vecS1 = newTemp(Ity_V128);
+ Int imm = (Int)getUChar(delta+1);
+ DIP("vpsrldq $%d,%s,%s\n", imm, nameYMMReg(rS), nameYMMReg(rD));
+ delta += 2;
+ assign( vecS0, getYMMRegLane128(rS, 0));
+ assign( vecS1, getYMMRegLane128(rS, 1));
+ putYMMRegLane128(rD, 0, mkexpr(math_PSRLDQ( vecS0, imm )));
+ putYMMRegLane128(rD, 1, mkexpr(math_PSRLDQ( vecS1, imm )));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 7) {
+ IRTemp vecS0 = newTemp(Ity_V128);
+ IRTemp vecS1 = newTemp(Ity_V128);
+ Int imm = (Int)getUChar(delta+1);
+ DIP("vpslldq $%d,%s,%s\n", imm, nameYMMReg(rS), nameYMMReg(rD));
+ delta += 2;
+ assign( vecS0, getYMMRegLane128(rS, 0));
+ assign( vecS1, getYMMRegLane128(rS, 1));
+ putYMMRegLane128(rD, 0, mkexpr(math_PSLLDQ( vecS0, imm )));
+ putYMMRegLane128(rD, 1, mkexpr(math_PSLLDQ( vecS1, imm )));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 2) {
+ delta = dis_AVX256_shiftE_to_V_imm( pfx, delta,
+ "vpsrlq", Iop_ShrN64x4 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 6) {
+ delta = dis_AVX256_shiftE_to_V_imm( pfx, delta,
+ "vpsllq", Iop_ShlN64x4 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* else fall through */
+ }
break;
case 0x74:
@@ -23314,6 +24787,13 @@
uses_vvvv, vbi, pfx, delta, "vpcmpeqb", Iop_CmpEQ8x16 );
goto decode_success;
}
+ /* VPCMPEQB r/m, rV, r ::: r = rV `eq-by-8s` r/m */
+ /* VPCMPEQB = VEX.NDS.256.66.0F.WIG 74 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpeqb", Iop_CmpEQ8x32 );
+ goto decode_success;
+ }
break;
case 0x75:
@@ -23324,6 +24804,13 @@
uses_vvvv, vbi, pfx, delta, "vpcmpeqw", Iop_CmpEQ16x8 );
goto decode_success;
}
+ /* VPCMPEQW r/m, rV, r ::: r = rV `eq-by-16s` r/m */
+ /* VPCMPEQW = VEX.NDS.256.66.0F.WIG 75 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpeqw", Iop_CmpEQ16x16 );
+ goto decode_success;
+ }
break;
case 0x76:
@@ -23334,6 +24821,13 @@
uses_vvvv, vbi, pfx, delta, "vpcmpeqd", Iop_CmpEQ32x4 );
goto decode_success;
}
+ /* VPCMPEQD r/m, rV, r ::: r = rV `eq-by-32s` r/m */
+ /* VPCMPEQD = VEX.NDS.256.66.0F.WIG 76 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpeqd", Iop_CmpEQ32x8 );
+ goto decode_success;
+ }
break;
case 0x77:
@@ -23901,6 +25395,14 @@
goto decode_success;
}
+ /* VPSRLW xmm3/m128, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG D1 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_shiftV_byE( vbi, pfx, delta,
+ "vpsrlw", Iop_ShrN16x16 );
+ *uses_vvvv = True;
+ goto decode_success;
+
+ }
break;
case 0xD2:
@@ -23911,6 +25413,13 @@
*uses_vvvv = True;
goto decode_success;
}
+ /* VPSRLD xmm3/m128, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG D2 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_shiftV_byE( vbi, pfx, delta,
+ "vpsrld", Iop_ShrN32x8 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
case 0xD3:
@@ -23921,6 +25430,13 @@
*uses_vvvv = True;
goto decode_success;
}
+ /* VPSRLQ xmm3/m128, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG D3 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_shiftV_byE( vbi, pfx, delta,
+ "vpsrlq", Iop_ShrN64x4 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
case 0xD4:
@@ -23931,6 +25447,13 @@
uses_vvvv, vbi, pfx, delta, "vpaddq", Iop_Add64x2 );
goto decode_success;
}
+ /* VPADDQ r/m, rV, r ::: r = rV + r/m */
+ /* VPADDQ = VEX.NDS.256.66.0F.WIG D4 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpaddq", Iop_Add64x4 );
+ goto decode_success;
+ }
break;
case 0xD5:
@@ -23940,6 +25463,12 @@
uses_vvvv, vbi, pfx, delta, "vpmullw", Iop_Mul16x8 );
goto decode_success;
}
+ /* VPMULLW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG D5 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpmullw", Iop_Mul16x16 );
+ goto decode_success;
+ }
break;
case 0xD6:
@@ -23970,8 +25499,13 @@
delta = dis_PMOVMSKB_128( vbi, pfx, delta, True/*isAvx*/ );
goto decode_success;
}
- break;
-
+ /* VEX.128.66.0F.WIG D7 /r = VPMOVMSKB ymm1, r32 */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVMSKB_256( vbi, pfx, delta );
+ goto decode_success;
+ }
+ break;
+
case 0xD8:
/* VPSUBUSB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D8 /r */
if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
@@ -23979,7 +25513,13 @@
uses_vvvv, vbi, pfx, delta, "vpsubusb", Iop_QSub8Ux16 );
goto decode_success;
}
- break;
+ /* VPSUBUSB ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG D8 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpsubusb", Iop_QSub8Ux32 );
+ goto decode_success;
+ }
+ break;
case 0xD9:
/* VPSUBUSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D9 /r */
@@ -23988,6 +25528,12 @@
uses_vvvv, vbi, pfx, delta, "vpsubusw", Iop_QSub16Ux8 );
goto decode_success;
}
+ /* VPSUBUSW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG D9 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpsubusw", Iop_QSub16Ux16 );
+ goto decode_success;
+ }
break;
case 0xDA:
@@ -23997,6 +25543,12 @@
uses_vvvv, vbi, pfx, delta, "vpminub", Iop_Min8Ux16 );
goto decode_success;
}
+ /* VPMINUB ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG DA /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpminub", Iop_Min8Ux32 );
+ goto decode_success;
+ }
break;
case 0xDB:
@@ -24007,6 +25559,13 @@
uses_vvvv, vbi, pfx, delta, "vpand", Iop_AndV128 );
goto decode_success;
}
+ /* VPAND r/m, rV, r ::: r = rV & r/m */
+ /* VEX.NDS.256.66.0F.WIG DB /r = VPAND ymm3/m256, ymm2, ymm1 */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpand", Iop_AndV256 );
+ goto decode_success;
+ }
break;
case 0xDC:
@@ -24016,6 +25575,12 @@
uses_vvvv, vbi, pfx, delta, "vpaddusb", Iop_QAdd8Ux16 );
goto decode_success;
}
+ /* VPADDUSB ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG DC /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpaddusb", Iop_QAdd8Ux32 );
+ goto decode_success;
+ }
break;
case 0xDD:
@@ -24025,6 +25590,12 @@
uses_vvvv, vbi, pfx, delta, "vpaddusw", Iop_QAdd16Ux8 );
goto decode_success;
}
+ /* VPADDUSW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG DD /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpaddusw", Iop_QAdd16Ux16 );
+ goto decode_success;
+ }
break;
case 0xDE:
@@ -24034,6 +25605,12 @@
uses_vvvv, vbi, pfx, delta, "vpmaxub", Iop_Max8Ux16 );
goto decode_success;
}
+ /* VPMAXUB ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG DE /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpmaxub", Iop_Max8Ux32 );
+ goto decode_success;
+ }
break;
case 0xDF:
@@ -24045,6 +25622,14 @@
NULL, True/*invertLeftArg*/, False/*swapArgs*/ );
goto decode_success;
}
+ /* VPANDN r/m, rV, r ::: r = rV & ~r/m (is that correct, re the ~ ?) */
+ /* VEX.NDS.256.66.0F.WIG DF /r = VPANDN ymm3/m256, ymm2, ymm1 */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpandn", Iop_AndV256,
+ NULL, True/*invertLeftArg*/, False/*swapArgs*/ );
+ goto decode_success;
+ }
break;
case 0xE0:
@@ -24054,6 +25639,12 @@
uses_vvvv, vbi, pfx, delta, "vpavgb", Iop_Avg8Ux16 );
goto decode_success;
}
+ /* VPAVGB ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG E0 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpavgb", Iop_Avg8Ux32 );
+ goto decode_success;
+ }
break;
case 0xE1:
@@ -24064,6 +25655,13 @@
*uses_vvvv = True;
goto decode_success;
}
+ /* VPSRAW xmm3/m128, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG E1 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_shiftV_byE( vbi, pfx, delta,
+ "vpsraw", Iop_SarN16x16 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
case 0xE2:
@@ -24074,6 +25672,13 @@
*uses_vvvv = True;
goto decode_success;
}
+ /* VPSRAD xmm3/m128, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG E2 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_shiftV_byE( vbi, pfx, delta,
+ "vpsrad", Iop_SarN32x8 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
case 0xE3:
@@ -24083,6 +25688,12 @@
uses_vvvv, vbi, pfx, delta, "vpavgw", Iop_Avg16Ux8 );
goto decode_success;
}
+ /* VPAVGW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG E3 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpavgw", Iop_Avg16Ux16 );
+ goto decode_success;
+ }
break;
case 0xE4:
@@ -24092,6 +25703,12 @@
uses_vvvv, vbi, pfx, delta, "vpmulhuw", Iop_MulHi16Ux8 );
goto decode_success;
}
+ /* VPMULHUW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG E4 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpmulhuw", Iop_MulHi16Ux16 );
+ goto decode_success;
+ }
break;
case 0xE5:
@@ -24101,6 +25718,12 @@
uses_vvvv, vbi, pfx, delta, "vpmulhw", Iop_MulHi16Sx8 );
goto decode_success;
}
+ /* VPMULHW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG E5 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpmulhw", Iop_MulHi16Sx16 );
+ goto decode_success;
+ }
break;
case 0xE6:
@@ -24176,6 +25799,12 @@
uses_vvvv, vbi, pfx, delta, "vpsubsb", Iop_QSub8Sx16 );
goto decode_success;
}
+ /* VPSUBSB ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG E8 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpsubsb", Iop_QSub8Sx32 );
+ goto decode_success;
+ }
break;
case 0xE9:
@@ -24185,6 +25814,12 @@
uses_vvvv, vbi, pfx, delta, "vpsubsw", Iop_QSub16Sx8 );
goto decode_success;
}
+ /* VPSUBSW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG E9 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpsubsw", Iop_QSub16Sx16 );
+ goto decode_success;
+ }
break;
case 0xEA:
@@ -24195,6 +25830,13 @@
uses_vvvv, vbi, pfx, delta, "vpminsw", Iop_Min16Sx8 );
goto decode_success;
}
+ /* VPMINSW r/m, rV, r ::: r = min-signed16s(rV, r/m) */
+ /* VPMINSW = VEX.NDS.256.66.0F.WIG EA /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpminsw", Iop_Min16Sx16 );
+ goto decode_success;
+ }
break;
case 0xEB:
@@ -24205,6 +25847,13 @@
uses_vvvv, vbi, pfx, delta, "vpor", Iop_OrV128 );
goto decode_success;
}
+ /* VPOR r/m, rV, r ::: r = rV | r/m */
+ /* VPOR = VEX.NDS.256.66.0F.WIG EB /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpor", Iop_OrV256 );
+ goto decode_success;
+ }
break;
case 0xEC:
@@ -24214,6 +25863,12 @@
uses_vvvv, vbi, pfx, delta, "vpaddsb", Iop_QAdd8Sx16 );
goto decode_success;
}
+ /* VPADDSB ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG EC /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpaddsb", Iop_QAdd8Sx32 );
+ goto decode_success;
+ }
break;
case 0xED:
@@ -24223,6 +25878,12 @@
uses_vvvv, vbi, pfx, delta, "vpaddsw", Iop_QAdd16Sx8 );
goto decode_success;
}
+ /* VPADDSW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG ED /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpaddsw", Iop_QAdd16Sx16 );
+ goto decode_success;
+ }
break;
case 0xEE:
@@ -24233,6 +25894,13 @@
uses_vvvv, vbi, pfx, delta, "vpmaxsw", Iop_Max16Sx8 );
goto decode_success;
}
+ /* VPMAXSW r/m, rV, r ::: r = max-signed16s(rV, r/m) */
+ /* VPMAXSW = VEX.NDS.256.66.0F.WIG EE /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpmaxsw", Iop_Max16Sx16 );
+ goto decode_success;
+ }
break;
case 0xEF:
@@ -24243,6 +25911,13 @@
uses_vvvv, vbi, pfx, delta, "vpxor", Iop_XorV128 );
goto decode_success;
}
+ /* VPXOR r/m, rV, r ::: r = rV ^ r/m */
+ /* VPXOR = VEX.NDS.256.66.0F.WIG EF /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpxor", Iop_XorV256 );
+ goto decode_success;
+ }
break;
case 0xF0:
@@ -24283,6 +25958,14 @@
goto decode_success;
}
+ /* VPSLLW xmm3/m128, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG F1 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_shiftV_byE( vbi, pfx, delta,
+ "vpsllw", Iop_ShlN16x16 );
+ *uses_vvvv = True;
+ goto decode_success;
+
+ }
break;
case 0xF2:
@@ -24293,6 +25976,13 @@
*uses_vvvv = True;
goto decode_success;
}
+ /* VPSLLD xmm3/m128, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG F2 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_shiftV_byE( vbi, pfx, delta,
+ "vpslld", Iop_ShlN32x8 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
case 0xF3:
@@ -24303,6 +25993,13 @@
*uses_vvvv = True;
goto decode_success;
}
+ /* VPSLLQ xmm3/m128, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG F3 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_shiftV_byE( vbi, pfx, delta,
+ "vpsllq", Iop_ShlN64x4 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
case 0xF4:
@@ -24313,6 +26010,13 @@
"vpmuludq", math_PMULUDQ_128 );
goto decode_success;
}
+ /* VPMULUDQ ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG F4 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta,
+ "vpmuludq", math_PMULUDQ_256 );
+ goto decode_success;
+ }
break;
case 0xF5:
@@ -24323,6 +26027,13 @@
"vpmaddwd", math_PMADDWD_128 );
goto decode_success;
}
+ /* VPMADDWD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG F5 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta,
+ "vpmaddwd", math_PMADDWD_256 );
+ goto decode_success;
+ }
break;
case 0xF6:
@@ -24333,6 +26044,13 @@
"vpsadbw", math_PSADBW_128 );
goto decode_success;
}
+ /* VPSADBW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG F6 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta,
+ "vpsadbw", math_PSADBW_256 );
+ goto decode_success;
+ }
break;
case 0xF7:
@@ -24352,6 +26070,13 @@
uses_vvvv, vbi, pfx, delta, "vpsubb", Iop_Sub8x16 );
goto decode_success;
}
+ /* VPSUBB r/m, rV, r ::: r = rV - r/m */
+ /* VPSUBB = VEX.NDS.256.66.0F.WIG F8 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpsubb", Iop_Sub8x32 );
+ goto decode_success;
+ }
break;
case 0xF9:
@@ -24362,6 +26087,13 @@
uses_vvvv, vbi, pfx, delta, "vpsubw", Iop_Sub16x8 );
goto decode_success;
}
+ /* VPSUBW r/m, rV, r ::: r = rV - r/m */
+ /* VPSUBW = VEX.NDS.256.66.0F.WIG F9 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpsubw", Iop_Sub16x16 );
+ goto decode_success;
+ }
break;
case 0xFA:
@@ -24372,6 +26104,13 @@
uses_vvvv, vbi, pfx, delta, "vpsubd", Iop_Sub32x4 );
goto decode_success;
}
+ /* VPSUBD r/m, rV, r ::: r = rV - r/m */
+ /* VPSUBD = VEX.NDS.256.66.0F.WIG FA /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpsubd", Iop_Sub32x8 );
+ goto decode_success;
+ }
break;
case 0xFB:
@@ -24382,6 +26121,13 @@
uses_vvvv, vbi, pfx, delta, "vpsubq", Iop_Sub64x2 );
goto decode_success;
}
+ /* VPSUBQ r/m, rV, r ::: r = rV - r/m */
+ /* VPSUBQ = VEX.NDS.256.66.0F.WIG FB /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpsubq", Iop_Sub64x4 );
+ goto decode_success;
+ }
break;
case 0xFC:
@@ -24392,6 +26138,13 @@
uses_vvvv, vbi, pfx, delta, "vpaddb", Iop_Add8x16 );
goto decode_success;
}
+ /* VPADDB r/m, rV, r ::: r = rV + r/m */
+ /* VPADDB = VEX.NDS.256.66.0F.WIG FC /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpaddb", Iop_Add8x32 );
+ goto decode_success;
+ }
break;
case 0xFD:
@@ -24402,6 +26155,13 @@
uses_vvvv, vbi, pfx, delta, "vpaddw", Iop_Add16x8 );
goto decode_success;
}
+ /* VPADDW r/m, rV, r ::: r = rV + r/m */
+ /* VPADDW = VEX.NDS.256.66.0F.WIG FD /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpaddw", Iop_Add16x16 );
+ goto decode_success;
+ }
break;
case 0xFE:
@@ -24412,6 +26172,13 @@
uses_vvvv, vbi, pfx, delta, "vpaddd", Iop_Add32x4 );
goto decode_success;
}
+ /* VPADDD r/m, rV, r ::: r = rV + r/m */
+ /* VPADDD = VEX.NDS.256.66.0F.WIG FE /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpaddd", Iop_Add32x8 );
+ goto decode_success;
+ }
break;
default:
@@ -24493,85 +26260,501 @@
return res;
}
-__attribute__((noinline))
-static
-Long dis_ESC_0F38__VEX (
- /*MB_OUT*/DisResult* dres,
- /*OUT*/ Bool* uses_vvvv,
- Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
- Bool resteerCisOk,
- void* callback_opaque,
- VexArchInfo* archinfo,
- VexAbiInfo* vbi,
- Prefix pfx, Int sz, Long deltaIN
- )
+static IRTemp math_VPERMD ( IRTemp ctrlV, IRTemp dataV )
{
- IRTemp addr = IRTemp_INVALID;
- Int alen = 0;
- HChar dis_buf[50];
- Long delta = deltaIN;
- UChar opc = getUChar(delta);
- delta++;
- *uses_vvvv = False;
+ /* In the control vector, zero out all but the bottom three bits of
+ each 32-bit lane. */
+ IRExpr* cv1 = binop(Iop_ShrN32x8,
+ binop(Iop_ShlN32x8, mkexpr(ctrlV), mkU8(29)),
+ mkU8(29));
+ /* And use the resulting cleaned-up control vector as steering
+ in a Perm operation. */
+ IRTemp res = newTemp(Ity_V256);
+ assign(res, binop(Iop_Perm32x8, mkexpr(dataV), cv1));
+ return res;
+}
- switch (opc) {
+static Long dis_SHIFTX ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi, Prefix pfx, Long delta,
+ HChar* opname, IROp op8 )
+{
+ HChar dis_buf[50];
+ Int alen;
+ Int size = getRexW(pfx) ? 8 : 4;
+ IRType ty = szToITy(size);
+ IRTemp src = newTemp(ty);
+ IRTemp amt = newTemp(ty);
+ UChar rm = getUChar(delta);
- case 0x00:
- /* VPSHUFB r/m, rV, r ::: r = shuf(rV, r/m) */
- /* VPSHUFB = VEX.NDS.128.66.0F38.WIG 00 /r */
- if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
- delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex(
- uses_vvvv, vbi, pfx, delta, "vpshufb", math_PSHUFB_XMM );
- goto decode_success;
- }
- break;
+ assign( amt, getIRegV(size,pfx) );
+ if (epartIsReg(rm)) {
+ assign( src, getIRegE(size,pfx,rm) );
+ DIP("%s %s,%s,%s\n", opname, nameIRegV(size,pfx),
+ nameIRegE(size,pfx,rm), nameIRegG(size,pfx,rm));
+ delta++;
+ } else {
+ IRTemp addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( src, loadLE(ty, mkexpr(addr)) );
+ DIP("%s %s,%s,%s\n", opname, nameIRegV(size,pfx), dis_buf,
+ nameIRegG(size,pfx,rm));
+ delta += alen;
+ }
- case 0x01:
- case 0x02:
- case 0x03:
- /* VPHADDW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 01 /r */
- /* VPHADDD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 02 /r */
- /* VPHADDSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 03 /r */
- if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
- delta = dis_PHADD_128( vbi, pfx, delta, True/*isAvx*/, opc );
- *uses_vvvv = True;
- goto decode_success;
- }
- break;
+ putIRegG( size, pfx, rm,
+ binop(mkSizedOp(ty,op8), mkexpr(src),
+ narrowTo(Ity_I8, binop(mkSizedOp(ty,Iop_And8), mkexpr(amt),
+ mkU(ty,8*size-1)))) );
+ /* Flags aren't modified. */
+ *uses_vvvv = True;
+ return delta;
+}
- case 0x04:
- /* VPMADDUBSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 04 /r */
- if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
- delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex(
- uses_vvvv, vbi, pfx, delta, "vpmaddubsw",
- math_PMADDUBSW_128 );
- goto decode_success;
- }
+
+static Long dis_FMA ( VexAbiInfo* vbi, Prefix pfx, Long delta, UChar opc )
+{
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ Bool scalar = (opc & 0xF) > 7 && (opc & 1);
+ IRType ty = getRexW(pfx) ? Ity_F64 : Ity_F32;
+ IRType vty = scalar ? ty : getVexL(pfx) ? Ity_V256 : Ity_V128;
+ IRTemp vX = newTemp(vty);
+ IRTemp vY = newTemp(vty);
+ IRTemp vZ = newTemp(vty);
+ IRExpr *x[8], *y[8], *z[8];
+ IRTemp addr = IRTemp_INVALID;
+ HChar dis_buf[50];
+ Int alen = 0;
+ HChar *name;
+ HChar *suffix;
+ HChar *order;
+ Bool negateRes = False;
+ Bool negateZeven = False;
+ Bool negateZodd = False;
+ Int i, j;
+ Int count;
+ static IROp ops[] = { Iop_V256to64_0, Iop_V256to64_1,
+ Iop_V256to64_2, Iop_V256to64_3,
+ Iop_V128to64, Iop_V128HIto64 };
+
+ switch (opc & 0xF) {
+ case 0x6:
+ name = "addsub";
+ negateZeven = True;
+ break;
+ case 0x7:
+ name = "subadd";
+ negateZodd = True;
+ break;
+ case 0x8:
+ case 0x9:
+ name = "add";
+ break;
+ case 0xA:
+ case 0xB:
+ name = "sub";
+ negateZeven = True;
+ negateZodd = True;
+ break;
+ case 0xC:
+ case 0xD:
+ name = "add";
+ negateRes = True;
+ negateZeven = True;
+ negateZodd = True;
+ break;
+ case 0xE:
+ case 0xF:
+ name = "sub";
+ negateRes = True;
break;
-
- case 0x05:
- case 0x06:
- case 0x07:
- /* VPHSUBW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 05 /r */
- /* VPHSUBD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 06 /r */
- /* VPHSUBSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 07 /r */
- if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
- delta = dis_PHADD_128( vbi, pfx, delta, True/*isAvx*/, opc );
- *uses_vvvv = True;
- goto decode_success;
- }
+ default:
+ vpanic("dis_FMA(amd64)");
break;
+ }
+ switch (opc & 0xF0) {
+ case 0x90: order = "132"; break;
+ case 0xA0: order = "213"; break;
+ case 0xB0: order = "231"; break;
+ default: vpanic("dis_FMA(amd64)"); break;
+ }
+ if (scalar)
+ suffix = ty == Ity_F64 ? "sd" : "ss";
+ else
+ suffix = ty == Ity_F64 ? "pd" : "ps";
- case 0x08:
- case 0x09:
- case 0x0A:
- /* VPSIGNB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 08 /r */
- /* VPSIGNW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 09 /r */
- /* VPSIGND xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 0A /r */
- if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
- IRTemp sV = newTemp(Ity_V128);
- IRTemp dV = newTemp(Ity_V128);
- IRTemp sHi, sLo, dHi, dLo;
+ if (scalar) {
+ assign( vX, ty == Ity_F64
+ ? getXMMRegLane64F(rG, 0) : getXMMRegLane32F(rG, 0) );
+ assign( vZ, ty == Ity_F64
+ ? getXMMRegLane64F(rV, 0) : getXMMRegLane32F(rV, 0) );
+ } else {
+ assign( vX, vty == Ity_V256 ? getYMMReg(rG) : getXMMReg(rG) );
+ assign( vZ, vty == Ity_V256 ? getYMMReg(rV) : getXMMReg(rV) );
+ }
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ if (scalar)
+ assign( vY, ty == Ity_F64
+ ? getXMMRegLane64F(rE, 0) : getXMMRegLane32F(rE, 0) );
+ else
+ assign( vY, vty == Ity_V256 ? getYMMReg(rE) : getXMMReg(rE) );
+ if (vty == Ity_V256) {
+ DIP("vf%sm%s%s%s %s,%s,%s\n", negateRes ? "n" : "",
+ name, order, suffix, nameYMMReg(rE), nameYMMReg(rV),
+ nameYMMReg(rG));
+ } else {
+ DIP("vf%sm%s%s%s %s,%s,%s\n", negateRes ? "n" : "",
+ name, order, suffix, nameXMMReg(rE), nameXMMReg(rV),
+ nameXMMReg(rG));
+ }
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ assign(vY, loadLE(vty, mkexpr(addr)));
+ if (vty == Ity_V256) {
+ DIP("vf%sm%s%s%s %s,%s,%s\n", negateRes ? "n" : "",
+ name, order, suffix, dis_buf, nameYMMReg(rV),
+ nameYMMReg(rG));
+ } else {
+ DIP("vf%sm%s%s%s %s,%s,%s\n", negateRes ? "n" : "",
+ name, order, suffix, dis_buf, nameXMMReg(rV),
+ nameXMMReg(rG));
+ }
+ }
+
+ /* vX/vY/vZ now in 132 order. If it is different order, swap the
+ arguments. */
+ if ((opc & 0xF0) != 0x90) {
+ IRTemp tem = vX;
+ if ((opc & 0xF0) == 0xA0) {
+ vX = vZ;
+ vZ = vY;
+ vY = tem;
+ } else {
+ vX = vZ;
+ vZ = tem;
+ }
+ }
+
+ if (scalar) {
+ count = 1;
+ x[0] = mkexpr(vX);
+ y[0] = mkexpr(vY);
+ z[0] = mkexpr(vZ);
+ } else if (ty == Ity_F32) {
+ count = vty == Ity_V256 ? 8 : 4;
+ j = vty == Ity_V256 ? 0 : 4;
+ for (i = 0; i < count; i += 2) {
+ IRTemp tem = newTemp(Ity_I64);
+ assign(tem, unop(ops[i / 2 + j], mkexpr(vX)));
+ x[i] = unop(Iop_64to32, mkexpr(tem));
+ x[i + 1] = unop(Iop_64HIto32, mkexpr(tem));
+ tem = newTemp(Ity_I64);
+ assign(tem, unop(ops[i / 2 + j], mkexpr(vY)));
+ y[i] = unop(Iop_64to32, mkexpr(tem));
+ y[i + 1] = unop(Iop_64HIto32, mkexpr(tem));
+ tem = newTemp(Ity_I64);
+ assign(tem, unop(ops[i / 2 + j], mkexpr(vZ)));
+ z[i] = unop(Iop_64to32, mkexpr(tem));
+ z[i + 1] = unop(Iop_64HIto32, mkexpr(tem));
+ }
+ } else {
+ count = vty == Ity_V256 ? 4 : 2;
+ j = vty == Ity_V256 ? 0 : 4;
+ for (i = 0; i < count; i++) {
+ x[i] = unop(ops[i + j], mkexpr(vX));
+ y[i] = unop(ops[i + j], mkexpr(vY));
+ z[i] = unop(ops[i + j], mkexpr(vZ));
+ }
+ }
+ if (!scalar)
+ for (i = 0; i < count; i++) {
+ IROp op = ty == Ity_F64
+ ? Iop_ReinterpI64asF64 : Iop_ReinterpI32asF32;
+ x[i] = unop(op, x[i]);
+ y[i] = unop(op, y[i]);
+ z[i] = unop(op, z[i]);
+ }
+ for (i = 0; i < count; i++) {
+ if ((i & 1) ? negateZodd : negateZeven)
+ z[i] = unop(ty == Ity_F64 ? Iop_NegF64 : Iop_NegF32, z[i]);
+ x[i] = IRExpr_Qop(ty == Ity_F64 ? Iop_MAddF64 : Iop_MAddF32,
+ get_FAKE_roundingmode(), x[i], y[i], z[i]);
+ if (negateRes)
+ x[i] = unop(ty == Ity_F64 ? Iop_NegF64 : Iop_NegF32, x[i]);
+ if (ty == Ity_F64)
+ putYMMRegLane64F( rG, i, x[i] );
+ else
+ putYMMRegLane32F( rG, i, x[i] );
+ }
+ if (vty != Ity_V256)
+ putYMMRegLane128( rG, 1, mkV128(0) );
+
+ return delta;
+}
+
+
+/* Masked load. */
+static ULong dis_VMASKMOV_load ( Bool *uses_vvvv, VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, Bool isYMM, IRType ty )
+{
+ HChar dis_buf[50];
+ Int alen, i;
+ IRTemp addr;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp res[8], cond;
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ if (isYMM) {
+ DIP("%s %s,%s,%s\n", opname, dis_buf, nameYMMReg(rV), nameYMMReg(rG) );
+ } else {
+ DIP("%s %s,%s,%s\n", opname, dis_buf, nameXMMReg(rV), nameXMMReg(rG) );
+ }
+ delta += alen;
+
+ for (i = 0; i < 2 * (isYMM ? 2 : 1) * (ty == Ity_I32 ? 2 : 1); i++) {
+ res[i] = newTemp(ty);
+ cond = newTemp(Ity_I8);
+ assign( cond, unop(Iop_1Uto8,
+ binop(ty == Ity_I32 ? Iop_CmpLT32S : Iop_CmpLT64S,
+ ty == Ity_I32 ? getYMMRegLane32( rV, i )
+ : getYMMRegLane64( rV, i ),
+ mkU(ty, 0))) );
+ assign( res[i],
+ IRExpr_Mux0X(mkexpr(cond),
+ mkU(ty, 0),
+ loadLE(ty, IRExpr_Mux0X(mkexpr(cond),
+ getIReg64(R_RSP),
+ binop(Iop_Add64, mkexpr(addr),
+ mkU64(i*(ty == Ity_I32 ? 4 : 8)))))) );
+ }
+ switch (ty) {
+ case Ity_I32:
+ for (i = 0; i < 8; i++)
+ putYMMRegLane32( rG, i, (i < 4 || isYMM)
+ ? mkexpr(res[i]) : mkU32(0) );
+ break;
+ case Ity_I64:
+ for (i = 0; i < 4; i++)
+ putYMMRegLane64( rG, i, (i < 2 || isYMM)
+ ? mkexpr(res[i]) : mkU64(0) );
+ break;
+ default: vassert(0);
+ }
+
+ *uses_vvvv = True;
+ return delta;
+}
+
+
+/* Gather. */
+static ULong dis_VGATHER ( Bool *uses_vvvv, VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, Bool isYMM, Bool isVM64x, IRType ty )
+{
+ HChar dis_buf[50];
+ Int alen, i, vscale, count1, count2;
+ IRTemp addr;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ UInt rI;
+ IRType dstTy = (isYMM && (ty == Ity_I64 || !isVM64x)) ? Ity_V256 : Ity_V128;
+ IRType idxTy = (isYMM && (ty == Ity_I32 || isVM64x)) ? Ity_V256 : Ity_V128;
+ IRTemp cond;
+ addr = disAVSIBMode ( &alen, vbi, pfx, delta, dis_buf, &rI,
+ idxTy, &vscale );
+ if (addr == IRTemp_INVALID || rI == rG || rI == rV || rG == rV)
+ return delta;
+ if (dstTy == Ity_V256) {
+ DIP("%s %s,%s,%s\n", opname, nameYMMReg(rV), dis_buf, nameYMMReg(rG) );
+ } else {
+ DIP("%s %s,%s,%s\n", opname, nameXMMReg(rV), dis_buf, nameXMMReg(rG) );
+ }
+ delta += alen;
+
+ if (ty == Ity_I32) {
+ count1 = isYMM ? 8 : 4;
+ count2 = isVM64x ? count1 / 2 : count1;
+ } else {
+ count1 = count2 = isYMM ? 4 : 2;
+ }
+
+ /* First update the mask register to copies of the sign bit. */
+ if (ty == Ity_I32) {
+ if (isYMM)
+ putYMMReg( rV, binop(Iop_SarN32x8, getYMMReg( rV ), mkU8(31)) );
+ else
+ putYMMRegLoAndZU( rV, binop(Iop_SarN32x4, getXMMReg( rV ), mkU8(31)) );
+ } else {
+ for (i = 0; i < count1; i++) {
+ putYMMRegLane64( rV, i, binop(Iop_Sar64, getYMMRegLane64( rV, i ),
+ mkU8(63)) );
+ }
+ }
+
+ /* Next gather the individual elements. If any fault occurs, the
+ corresponding mask element will be set and the loop stops. */
+ for (i = 0; i < count2; i++) {
+ IRExpr *expr, *addr_expr;
+ cond = newTemp(Ity_I8);
+ assign( cond, unop(Iop_1Uto8,
+ binop(ty == Ity_I32 ? Iop_CmpLT32S : Iop_CmpLT64S,
+ ty == Ity_I32 ? getYMMRegLane32( rV, i )
+ : getYMMRegLane64( rV, i ),
+ mkU(ty, 0))) );
+ expr = ty == Ity_I32 ? getYMMRegLane32( rG, i )
+ : getYMMRegLane64( rG, i );
+ addr_expr = isVM64x ? getYMMRegLane64( rI, i )
+ : unop(Iop_32Sto64, getYMMRegLane32( rI, i ));
+ switch (vscale) {
+ case 2: addr_expr = binop(Iop_Shl64, addr_expr, mkU8(1)); break;
+ case 4: addr_expr = binop(Iop_Shl64, addr_expr, mkU8(2)); break;
+ case 8: addr_expr = binop(Iop_Shl64, addr_expr, mkU8(3)); break;
+ default: break;
+ }
+ addr_expr = binop(Iop_Add64, mkexpr(addr), addr_expr);
+ addr_expr = handleAddrOverrides(vbi, pfx, addr_expr);
+ addr_expr = IRExpr_Mux0X(mkexpr(cond), getIReg64(R_RSP), addr_expr);
+ expr = IRExpr_Mux0X(mkexpr(cond), expr, loadLE(ty, addr_expr));
+ if (ty == Ity_I32) {
+ putYMMRegLane32( rG, i, expr );
+ putYMMRegLane32( rV, i, mkU32(0) );
+ } else {
+ putYMMRegLane64( rG, i, expr);
+ putYMMRegLane64( rV, i, mkU64(0) );
+ }
+ }
+
+ if (!isYMM || (ty == Ity_I32 && isVM64x)) {
+ if (ty == Ity_I64 || isYMM)
+ putYMMRegLane128( rV, 1, mkV128(0) );
+ else if (ty == Ity_I32 && count2 == 2) {
+ putYMMRegLane64( rV, 1, mkU64(0) );
+ putYMMRegLane64( rG, 1, mkU64(0) );
+ }
+ putYMMRegLane128( rG, 1, mkV128(0) );
+ }
+
+ *uses_vvvv = True;
+ return delta;
+}
+
+
+__attribute__((noinline))
+static
+Long dis_ESC_0F38__VEX (
+ /*MB_OUT*/DisResult* dres,
+ /*OUT*/ Bool* uses_vvvv,
+ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ VexArchInfo* archinfo,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN
+ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ *uses_vvvv = False;
+
+ switch (opc) {
+
+ case 0x00:
+ /* VPSHUFB r/m, rV, r ::: r = shuf(rV, r/m) */
+ /* VPSHUFB = VEX.NDS.128.66.0F38.WIG 00 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpshufb", math_PSHUFB_XMM );
+ goto decode_success;
+ }
+ /* VPSHUFB r/m, rV, r ::: r = shuf(rV, r/m) */
+ /* VPSHUFB = VEX.NDS.256.66.0F38.WIG 00 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpshufb", math_PSHUFB_YMM );
+ goto decode_success;
+ }
+ break;
+
+ case 0x01:
+ case 0x02:
+ case 0x03:
+ /* VPHADDW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 01 /r */
+ /* VPHADDD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 02 /r */
+ /* VPHADDSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 03 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PHADD_128( vbi, pfx, delta, True/*isAvx*/, opc );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VPHADDW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 01 /r */
+ /* VPHADDD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 02 /r */
+ /* VPHADDSW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 03 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PHADD_256( vbi, pfx, delta, opc );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x04:
+ /* VPMADDUBSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 04 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpmaddubsw",
+ math_PMADDUBSW_128 );
+ goto decode_success;
+ }
+ /* VPMADDUBSW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 04 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpmaddubsw",
+ math_PMADDUBSW_256 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x05:
+ case 0x06:
+ case 0x07:
+ /* VPHSUBW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 05 /r */
+ /* VPHSUBD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 06 /r */
+ /* VPHSUBSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 07 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PHADD_128( vbi, pfx, delta, True/*isAvx*/, opc );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VPHSUBW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 05 /r */
+ /* VPHSUBD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 06 /r */
+ /* VPHSUBSW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 07 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PHADD_256( vbi, pfx, delta, opc );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x08:
+ case 0x09:
+ case 0x0A:
+ /* VPSIGNB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 08 /r */
+ /* VPSIGNW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 09 /r */
+ /* VPSIGND xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 0A /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp sHi, sLo, dHi, dLo;
sHi = sLo = dHi = dLo = IRTemp_INVALID;
UChar ch = '?';
Int laneszB = 0;
@@ -24615,6 +26798,63 @@
*uses_vvvv = True;
goto decode_success;
}
+ /* VPSIGNB ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 08 /r */
+ /* VPSIGNW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 09 /r */
+ /* VPSIGND ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 0A /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ IRTemp sV = newTemp(Ity_V256);
+ IRTemp dV = newTemp(Ity_V256);
+ IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
+ s3 = s2 = s1 = s0 = IRTemp_INVALID;
+ d3 = d2 = d1 = d0 = IRTemp_INVALID;
+ UChar ch = '?';
+ Int laneszB = 0;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+
+ switch (opc) {
+ case 0x08: laneszB = 1; ch = 'b'; break;
+ case 0x09: laneszB = 2; ch = 'w'; break;
+ case 0x0A: laneszB = 4; ch = 'd'; break;
+ default: vassert(0);
+ }
+
+ assign( dV, getYMMReg(rV) );
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getYMMReg(rE) );
+ delta += 1;
+ DIP("vpsign%c %s,%s,%s\n", ch, nameYMMReg(rE),
+ nameYMMReg(rV), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V256, mkexpr(addr)) );
+ delta += alen;
+ DIP("vpsign%c %s,%s,%s\n", ch, dis_buf,
+ nameYMMReg(rV), nameYMMReg(rG));
+ }
+
+ breakupV256to64s( dV, &d3, &d2, &d1, &d0 );
+ breakupV256to64s( sV, &s3, &s2, &s1, &s0 );
+
+ putYMMReg(
+ rG,
+ binop( Iop_V128HLtoV256,
+ binop(Iop_64HLtoV128,
+ dis_PSIGN_helper( mkexpr(s3), mkexpr(d3), laneszB ),
+ dis_PSIGN_helper( mkexpr(s2), mkexpr(d2), laneszB )
+ ),
+ binop(Iop_64HLtoV128,
+ dis_PSIGN_helper( mkexpr(s1), mkexpr(d1), laneszB ),
+ dis_PSIGN_helper( mkexpr(s0), mkexpr(d0), laneszB )
+ )
+ )
+ );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
case 0x0B:
@@ -24657,6 +26897,49 @@
*uses_vvvv = True;
goto decode_success;
}
+ /* VPMULHRSW ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 0B /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ IRTemp sV = newTemp(Ity_V256);
+ IRTemp dV = newTemp(Ity_V256);
+ IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
+ s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+
+ assign( dV, getYMMReg(rV) );
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getYMMReg(rE) );
+ delta += 1;
+ DIP("vpmulhrsw %s,%s,%s\n", nameYMMReg(rE),
+ nameYMMReg(rV), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V256, mkexpr(addr)) );
+ delta += alen;
+ DIP("vpmulhrsw %s,%s,%s\n", dis_buf,
+ nameYMMReg(rV), nameYMMReg(rG));
+ }
+
+ breakupV256to64s( dV, &d3, &d2, &d1, &d0 );
+ breakupV256to64s( sV, &s3, &s2, &s1, &s0 );
+
+ putYMMReg(
+ rG,
+ binop(Iop_V128HLtoV256,
+ binop(Iop_64HLtoV128,
+ dis_PMULHRSW_helper( mkexpr(s3), mkexpr(d3) ),
+ dis_PMULHRSW_helper( mkexpr(s2), mkexpr(d2) ) ),
+ binop(Iop_64HLtoV128,
+ dis_PMULHRSW_helper( mkexpr(s1), mkexpr(d1) ),
+ dis_PMULHRSW_helper( mkexpr(s0), mkexpr(d0) ) )
+ )
+ );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
case 0x0C:
@@ -24799,10 +27082,20 @@
}
break;
- case 0x17:
- /* VPTEST xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 17 /r */
- if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
- delta = dis_xTESTy_128( vbi, pfx, delta, True/*isAvx*/, 0 );
+ case 0x16:
+ /* VPERMPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 16 /r */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpermps", math_VPERMD );
+ goto decode_success;
+ }
+ break;
+
+ case 0x17:
+ /* VPTEST xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 17 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_xTESTy_128( vbi, pfx, delta, True/*isAvx*/, 0 );
goto decode_success;
}
/* VPTEST ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 17 /r */
@@ -24848,6 +27141,41 @@
putYMMReg(rG, res);
goto decode_success;
}
+ /* VBROADCASTSS xmm2, xmm1 = VEX.128.66.0F38.WIG 18 /r */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/
+ && epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rE = eregOfRexRM(pfx, modrm);
+ DIP("vbroadcastss %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ IRTemp t32 = newTemp(Ity_I32);
+ assign(t32, getXMMRegLane32(rE, 0));
+ IRTemp t64 = newTemp(Ity_I64);
+ assign(t64, binop(Iop_32HLto64, mkexpr(t32), mkexpr(t32)));
+ IRExpr* res = binop(Iop_64HLtoV128, mkexpr(t64), mkexpr(t64));
+ putYMMRegLoAndZU(rG, res);
+ delta++;
+ goto decode_success;
+ }
+ /* VBROADCASTSS xmm2, ymm1 = VEX.256.66.0F38.WIG 18 /r */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/
+ && epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rE = eregOfRexRM(pfx, modrm);
+ DIP("vbroadcastss %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
+ IRTemp t32 = newTemp(Ity_I32);
+ assign(t32, getXMMRegLane32(rE, 0));
+ IRTemp t64 = newTemp(Ity_I64);
+ assign(t64, binop(Iop_32HLto64, mkexpr(t32), mkexpr(t32)));
+ IRExpr* res = IRExpr_Qop(Iop_64x4toV256, mkexpr(t64), mkexpr(t64),
+ mkexpr(t64), mkexpr(t64));
+ putYMMReg(rG, res);
+ delta++;
+ goto decode_success;
+ }
break;
case 0x19:
@@ -24867,6 +27195,22 @@
putYMMReg(rG, res);
goto decode_success;
}
+ /* VBROADCASTSD xmm2, ymm1 = VEX.256.66.0F38.WIG 19 /r */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/
+ && epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rE = eregOfRexRM(pfx, modrm);
+ DIP("vbroadcastsd %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
+ IRTemp t64 = newTemp(Ity_I64);
+ assign(t64, getXMMRegLane64(rE, 0));
+ IRExpr* res = IRExpr_Qop(Iop_64x4toV256, mkexpr(t64), mkexpr(t64),
+ mkexpr(t64), mkexpr(t64));
+ putYMMReg(rG, res);
+ delta++;
+ goto decode_success;
+ }
break;
case 0x1A:
@@ -24894,6 +27238,13 @@
"vpabsb", math_PABS_XMM_pap1 );
goto decode_success;
}
+ /* VPABSB ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 1C /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_to_G_unary(
+ uses_vvvv, vbi, pfx, delta,
+ "vpabsb", math_PABS_YMM_pap1 );
+ goto decode_success;
+ }
break;
case 0x1D:
@@ -24904,6 +27255,13 @@
"vpabsw", math_PABS_XMM_pap2 );
goto decode_success;
}
+ /* VPABSW ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 1D /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_to_G_unary(
+ uses_vvvv, vbi, pfx, delta,
+ "vpabsw", math_PABS_YMM_pap2 );
+ goto decode_success;
+ }
break;
case 0x1E:
@@ -24914,6 +27272,13 @@
"vpabsd", math_PABS_XMM_pap4 );
goto decode_success;
}
+ /* VPABSD ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 1E /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_to_G_unary(
+ uses_vvvv, vbi, pfx, delta,
+ "vpabsd", math_PABS_YMM_pap4 );
+ goto decode_success;
+ }
break;
case 0x20:
@@ -24924,6 +27289,12 @@
True/*isAvx*/, False/*!xIsZ*/ );
goto decode_success;
}
+ /* VPMOVSXBW xmm2/m128, ymm1 */
+ /* VPMOVSXBW = VEX.256.66.0F38.WIG 20 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVxXBW_256( vbi, pfx, delta, False/*!xIsZ*/ );
+ goto decode_success;
+ }
break;
case 0x21:
@@ -24934,6 +27305,12 @@
True/*isAvx*/, False/*!xIsZ*/ );
goto decode_success;
}
+ /* VPMOVSXBD xmm2/m64, ymm1 */
+ /* VPMOVSXBD = VEX.256.66.0F38.WIG 21 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVxXBD_256( vbi, pfx, delta, False/*!xIsZ*/ );
+ goto decode_success;
+ }
break;
case 0x22:
@@ -24943,6 +27320,12 @@
delta = dis_PMOVSXBQ_128( vbi, pfx, delta, True/*isAvx*/ );
goto decode_success;
}
+ /* VPMOVSXBQ xmm2/m32, ymm1 */
+ /* VPMOVSXBQ = VEX.256.66.0F38.WIG 22 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVSXBQ_256( vbi, pfx, delta );
+ goto decode_success;
+ }
break;
case 0x23:
@@ -24952,6 +27335,11 @@
True/*isAvx*/, False/*!xIsZ*/ );
goto decode_success;
}
+ /* VPMOVSXWD xmm2/m128, ymm1 = VEX.256.66.0F38.WIG 23 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVxXWD_256( vbi, pfx, delta, False/*!xIsZ*/ );
+ goto decode_success;
+ }
break;
case 0x24:
@@ -24960,6 +27348,11 @@
delta = dis_PMOVSXWQ_128( vbi, pfx, delta, True/*isAvx*/ );
goto decode_success;
}
+ /* VPMOVSXWQ xmm2/m64, ymm1 = VEX.256.66.0F38.WIG 24 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVSXWQ_256( vbi, pfx, delta );
+ goto decode_success;
+ }
break;
case 0x25:
@@ -24969,6 +27362,11 @@
True/*isAvx*/, False/*!xIsZ*/ );
goto decode_success;
}
+ /* VPMOVSXDQ xmm2/m128, ymm1 = VEX.256.66.0F38.WIG 25 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVxXDQ_256( vbi, pfx, delta, False/*!xIsZ*/ );
+ goto decode_success;
+ }
break;
case 0x28:
@@ -24979,6 +27377,13 @@
"vpmuldq", math_PMULDQ_128 );
goto decode_success;
}
+ /* VPMULDQ ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 28 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta,
+ "vpmuldq", math_PMULDQ_256 );
+ goto decode_success;
+ }
break;
case 0x29:
@@ -24989,6 +27394,13 @@
uses_vvvv, vbi, pfx, delta, "vpcmpeqq", Iop_CmpEQ64x2 );
goto decode_success;
}
+ /* VPCMPEQQ r/m, rV, r ::: r = rV `eq-by-64s` r/m */
+ /* VPCMPEQQ = VEX.NDS.256.66.0F38.WIG 29 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpeqq", Iop_CmpEQ64x4 );
+ goto decode_success;
+ }
break;
case 0x2A:
@@ -25006,6 +27418,20 @@
putYMMRegLoAndZU(rD, mkexpr(tD));
goto decode_success;
}
+ /* VMOVNTDQA m256, ymm1 = VEX.256.66.0F38.WIG 2A /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ IRTemp tD = newTemp(Ity_V256);
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ gen_SEGV_if_not_32_aligned(addr);
+ assign(tD, loadLE(Ity_V256, mkexpr(addr)));
+ DIP("vmovntdqa %s,%s\n", dis_buf, nameYMMReg(rD));
+ putYMMReg(rD, mkexpr(tD));
+ goto decode_success;
+ }
break;
case 0x2B:
@@ -25018,6 +27444,48 @@
False/*!invertLeftArg*/, True/*swapArgs*/ );
goto decode_success;
}
+ /* VPACKUSDW r/m, rV, r ::: r = QNarrowBin32Sto16Ux8(rV, r/m) */
+ /* VPACKUSDW = VEX.NDS.256.66.0F38.WIG 2B /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpackusdw",
+ math_VPACKUSDW_YMM );
+ goto decode_success;
+ }
+ break;
+
+ case 0x2C:
+ /* VMASKMOVPS m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 2C /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && !epartIsReg(getUChar(delta))) {
+ delta = dis_VMASKMOV_load( uses_vvvv, vbi, pfx, delta, "vmaskmovps",
+ /*!isYMM*/False, Ity_I32 );
+ goto decode_success;
+ }
+ /* VMASKMOVPS m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 2C /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && !epartIsReg(getUChar(delta))) {
+ delta = dis_VMASKMOV_load( uses_vvvv, vbi, pfx, delta, "vmaskmovps",
+ /*isYMM*/True, Ity_I32 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x2D:
+ /* VMASKMOVPD m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 2D /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && !epartIsReg(getUChar(delta))) {
+ delta = dis_VMASKMOV_load( uses_vvvv, vbi, pfx, delta, "vmaskmovpd",
+ /*!isYMM*/False, Ity_I64 );
+ goto decode_success;
+ }
+ /* VMASKMOVPD m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.WIG 2D /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && !epartIsReg(getUChar(delta))) {
+ delta = dis_VMASKMOV_load( uses_vvvv, vbi, pfx, delta, "vmaskmovpd",
+ /*isYMM*/True, Ity_I64 );
+ goto decode_success;
+ }
break;
case 0x30:
@@ -25028,6 +27496,12 @@
True/*isAvx*/, True/*xIsZ*/ );
goto decode_success;
}
+ /* VPMOVZXBW xmm2/m128, ymm1 */
+ /* VPMOVZXBW = VEX.256.66.0F38.WIG 30 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVxXBW_256( vbi, pfx, delta, True/*xIsZ*/ );
+ goto decode_success;
+ }
break;
case 0x31:
@@ -25038,6 +27512,12 @@
True/*isAvx*/, True/*xIsZ*/ );
goto decode_success;
}
+ /* VPMOVZXBD xmm2/m64, ymm1 */
+ /* VPMOVZXBD = VEX.256.66.0F38.WIG 31 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVxXBD_256( vbi, pfx, delta, True/*xIsZ*/ );
+ goto decode_success;
+ }
break;
case 0x32:
@@ -25047,6 +27527,12 @@
delta = dis_PMOVZXBQ_128( vbi, pfx, delta, True/*isAvx*/ );
goto decode_success;
}
+ /* VPMOVZXBQ xmm2/m32, ymm1 */
+ /* VPMOVZXBQ = VEX.256.66.0F38.WIG 32 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVZXBQ_256( vbi, pfx, delta );
+ goto decode_success;
+ }
break;
case 0x33:
@@ -25057,6 +27543,12 @@
True/*isAvx*/, True/*xIsZ*/ );
goto decode_success;
}
+ /* VPMOVZXWD xmm2/m128, ymm1 */
+ /* VPMOVZXWD = VEX.256.66.0F38.WIG 33 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVxXWD_256( vbi, pfx, delta, True/*xIsZ*/ );
+ goto decode_success;
+ }
break;
case 0x34:
@@ -25065,6 +27557,11 @@
delta = dis_PMOVZXWQ_128( vbi, pfx, delta, True/*isAvx*/ );
goto decode_success;
}
+ /* VPMOVZXWQ xmm2/m64, ymm1 = VEX.256.66.0F38.WIG 34 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVZXWQ_256( vbi, pfx, delta );
+ goto decode_success;
+ }
break;
case 0x35:
@@ -25074,6 +27571,21 @@
True/*isAvx*/, True/*xIsZ*/ );
goto decode_success;
}
+ /* VPMOVZXDQ xmm2/m128, ymm1 = VEX.256.66.0F38.WIG 35 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_PMOVxXDQ_256( vbi, pfx, delta, True/*xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x36:
+ /* VPERMD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 36 /r */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpermd", math_VPERMD );
+ goto decode_success;
+ }
break;
case 0x37:
@@ -25084,6 +27596,13 @@
uses_vvvv, vbi, pfx, delta, "vpcmpgtq", Iop_CmpGT64Sx2 );
goto decode_success;
}
+ /* VPCMPGTQ r/m, rV, r ::: r = rV `>s-by-64s` r/m */
+ /* VPCMPGTQ = VEX.NDS.256.66.0F38.WIG 37 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpgtq", Iop_CmpGT64Sx4 );
+ goto decode_success;
+ }
break;
case 0x38:
@@ -25094,6 +27613,13 @@
uses_vvvv, vbi, pfx, delta, "vpminsb", Iop_Min8Sx16 );
goto decode_success;
}
+ /* VPMINSB r/m, rV, r ::: r = min-signed-8s(rV, r/m) */
+ /* VPMINSB = VEX.NDS.256.66.0F38.WIG 38 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpminsb", Iop_Min8Sx32 );
+ goto decode_success;
+ }
break;
case 0x39:
@@ -25104,6 +27630,13 @@
uses_vvvv, vbi, pfx, delta, "vpminsd", Iop_Min32Sx4 );
goto decode_success;
}
+ /* VPMINSD r/m, rV, r ::: r = min-signed-32s(rV, r/m) */
+ /* VPMINSD = VEX.NDS.256.66.0F38.WIG 39 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpminsd", Iop_Min32Sx8 );
+ goto decode_success;
+ }
break;
case 0x3A:
@@ -25114,6 +27647,13 @@
uses_vvvv, vbi, pfx, delta, "vpminuw", Iop_Min16Ux8 );
goto decode_success;
}
+ /* VPMINUW r/m, rV, r ::: r = min-unsigned-16s(rV, r/m) */
+ /* VPMINUW = VEX.NDS.256.66.0F38.WIG 3A /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpminuw", Iop_Min16Ux16 );
+ goto decode_success;
+ }
break;
case 0x3B:
@@ -25124,6 +27664,13 @@
uses_vvvv, vbi, pfx, delta, "vpminud", Iop_Min32Ux4 );
goto decode_success;
}
+ /* VPMINUD r/m, rV, r ::: r = min-unsigned-32s(rV, r/m) */
+ /* VPMINUD = VEX.NDS.256.66.0F38.WIG 3B /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpminud", Iop_Min32Ux8 );
+ goto decode_success;
+ }
break;
case 0x3C:
@@ -25134,6 +27681,13 @@
uses_vvvv, vbi, pfx, delta, "vpmaxsb", Iop_Max8Sx16 );
goto decode_success;
}
+ /* VPMAXSB r/m, rV, r ::: r = max-signed-8s(rV, r/m) */
+ /* VPMAXSB = VEX.NDS.256.66.0F38.WIG 3C /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpmaxsb", Iop_Max8Sx32 );
+ goto decode_success;
+ }
break;
case 0x3D:
@@ -25144,6 +27698,13 @@
uses_vvvv, vbi, pfx, delta, "vpmaxsd", Iop_Max32Sx4 );
goto decode_success;
}
+ /* VPMAXSD r/m, rV, r ::: r = max-signed-32s(rV, r/m) */
+ /* VPMAXSD = VEX.NDS.256.66.0F38.WIG 3D /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpmaxsd", Iop_Max32Sx8 );
+ goto decode_success;
+ }
break;
case 0x3E:
@@ -25154,6 +27715,13 @@
uses_vvvv, vbi, pfx, delta, "vpmaxuw", Iop_Max16Ux8 );
goto decode_success;
}
+ /* VPMAXUW r/m, rV, r ::: r = max-unsigned-16s(rV, r/m) */
+ /* VPMAXUW = VEX.NDS.256.66.0F38.WIG 3E /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpmaxuw", Iop_Max16Ux16 );
+ goto decode_success;
+ }
break;
case 0x3F:
@@ -25164,6 +27732,13 @@
uses_vvvv, vbi, pfx, delta, "vpmaxud", Iop_Max32Ux4 );
goto decode_success;
}
+ /* VPMAXUD r/m, rV, r ::: r = max-unsigned-32s(rV, r/m) */
+ /* VPMAXUD = VEX.NDS.256.66.0F38.WIG 3F /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpmaxud", Iop_Max32Ux8 );
+ goto decode_success;
+ }
break;
case 0x40:
@@ -25174,6 +27749,13 @@
uses_vvvv, vbi, pfx, delta, "vpmulld", Iop_Mul32x4 );
goto decode_success;
}
+ /* VPMULLD r/m, rV, r ::: r = mul-32s(rV, r/m) */
+ /* VPMULLD = VEX.NDS.256.66.0F38.WIG 40 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpmulld", Iop_Mul32x8 );
+ goto decode_success;
+ }
break;
case 0x41:
@@ -25184,60 +27766,1038 @@
}
break;
- case 0xDB:
- case 0xDC:
- case 0xDD:
- case 0xDE:
- case 0xDF:
- /* VAESIMC xmm2/m128, xmm1 = VEX.128.66.0F38.WIG DB /r */
- /* VAESENC xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DC /r */
- /* VAESENCLAST xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DD /r */
- /* VAESDEC xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DE /r */
- /* VAESDECLAST xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DF /r */
- if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
- delta = dis_AESx( vbi, pfx, delta, True/*!isAvx*/, opc );
- if (opc != 0xDB) *uses_vvvv = True;
+ case 0x45:
+ /* VPSRLVD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W0 45 /r */
+ /* VPSRLVD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 45 /r */
+ if (have66noF2noF3(pfx) && 0==getRexW(pfx)/*W0*/) {
+ delta = dis_AVX_var_shiftV_byE( vbi, pfx, delta, "vpsrlvd",
+ Iop_Shr32, 1==getVexL(pfx) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VPSRLVQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W1 45 /r */
+ /* VPSRLVQ ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W1 45 /r */
+ if (have66noF2noF3(pfx) && 1==getRexW(pfx)/*W1*/) {
+ delta = dis_AVX_var_shiftV_byE( vbi, pfx, delta, "vpsrlvq",
+ Iop_Shr64, 1==getVexL(pfx) );
+ *uses_vvvv = True;
goto decode_success;
}
break;
- default:
+ case 0x46:
+ /* VPSRAVD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W0 46 /r */
+ /* VPSRAVD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 46 /r */
+ if (have66noF2noF3(pfx) && 0==getRexW(pfx)/*W0*/) {
+ delta = dis_AVX_var_shiftV_byE( vbi, pfx, delta, "vpsravd",
+ Iop_Sar32, 1==getVexL(pfx) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
- }
-
- //decode_failure:
- return deltaIN;
-
- decode_success:
- return delta;
-}
-
-
-/*------------------------------------------------------------*/
-/*--- ---*/
-/*--- Top-level post-escape decoders: dis_ESC_0F3A__VEX ---*/
-/*--- ---*/
-/*------------------------------------------------------------*/
-
-static IRTemp math_VPERMILPS_128 ( IRTemp sV, UInt imm8 )
-{
- vassert(imm8 < 256);
- IRTemp s3, s2, s1, s0;
- s3 = s2 = s1 = s0 = IRTemp_INVALID;
- breakupV128to32s( sV, &s3, &s2, &s1, &s0 );
-# define SEL(_nn) (((_nn)==0) ? s0 : ((_nn)==1) ? s1 \
- : ((_nn)==2) ? s2 : s3)
- IRTemp res = newTemp(Ity_V128);
- assign(res, mkV128from32s( SEL((imm8 >> 6) & 3),
- SEL((imm8 >> 4) & 3),
- SEL((imm8 >> 2) & 3),
- SEL((imm8 >> 0) & 3) ));
-# undef SEL
- return res;
-}
+ case 0x47:
+ /* VPSLLVD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W0 47 /r */
+ /* VPSLLVD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 47 /r */
+ if (have66noF2noF3(pfx) && 0==getRexW(pfx)/*W0*/) {
+ delta = dis_AVX_var_shiftV_byE( vbi, pfx, delta, "vpsllvd",
+ Iop_Shl32, 1==getVexL(pfx) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VPSLLVQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W1 47 /r */
+ /* VPSLLVQ ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W1 47 /r */
+ if (have66noF2noF3(pfx) && 1==getRexW(pfx)/*W1*/) {
+ delta = dis_AVX_var_shiftV_byE( vbi, pfx, delta, "vpsllvq",
+ Iop_Shl64, 1==getVexL(pfx) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
-__attribute__((noinline))
+ case 0x58:
+ /* VPBROADCASTD xmm2/m32, xmm1 = VEX.128.66.0F38.W0 58 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp t32 = newTemp(Ity_I32);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta++;
+ DIP("vpbroadcastd %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ assign(t32, getXMMRegLane32(rE, 0));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vpbroadcastd %s,%s\n", dis_buf, nameXMMReg(rG));
+ assign(t32, loadLE(Ity_I32, mkexpr(addr)));
+ }
+ IRTemp t64 = newTemp(Ity_I64);
+ assign(t64, binop(Iop_32HLto64, mkexpr(t32), mkexpr(t32)));
+ IRExpr* res = binop(Iop_64HLtoV128, mkexpr(t64), mkexpr(t64));
+ putYMMRegLoAndZU(rG, res);
+ goto decode_success;
+ }
+ /* VPBROADCASTD xmm2/m32, ymm1 = VEX.256.66.0F38.W0 58 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp t32 = newTemp(Ity_I32);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta++;
+ DIP("vpbroadcastd %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
+ assign(t32, getXMMRegLane32(rE, 0));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vpbroadcastd %s,%s\n", dis_buf, nameYMMReg(rG));
+ assign(t32, loadLE(Ity_I32, mkexpr(addr)));
+ }
+ IRTemp t64 = newTemp(Ity_I64);
+ assign(t64, binop(Iop_32HLto64, mkexpr(t32), mkexpr(t32)));
+ IRExpr* res = IRExpr_Qop(Iop_64x4toV256, mkexpr(t64), mkexpr(t64),
+ mkexpr(t64), mkexpr(t64));
+ putYMMReg(rG, res);
+ goto decode_success;
+ }
+ break;
+
+ case 0x59:
+ /* VPBROADCASTQ xmm2/m64, xmm1 = VEX.128.66.0F38.W0 59 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp t64 = newTemp(Ity_I64);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta++;
+ DIP("vpbroadcastq %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ assign(t64, getXMMRegLane64(rE, 0));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vpbroadcastq %s,%s\n", dis_buf, nameXMMReg(rG));
+ assign(t64, loadLE(Ity_I64, mkexpr(addr)));
+ }
+ IRExpr* res = binop(Iop_64HLtoV128, mkexpr(t64), mkexpr(t64));
+ putYMMRegLoAndZU(rG, res);
+ goto decode_success;
+ }
+ /* VPBROADCASTQ xmm2/m64, ymm1 = VEX.256.66.0F38.W0 59 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp t64 = newTemp(Ity_I64);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta++;
+ DIP("vpbroadcastq %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
+ assign(t64, getXMMRegLane64(rE, 0));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vpbroadcastq %s,%s\n", dis_buf, nameYMMReg(rG));
+ assign(t64, loadLE(Ity_I64, mkexpr(addr)));
+ }
+ IRExpr* res = IRExpr_Qop(Iop_64x4toV256, mkexpr(t64), mkexpr(t64),
+ mkexpr(t64), mkexpr(t64));
+ putYMMReg(rG, res);
+ goto decode_success;
+ }
+ break;
+
+ case 0x5A:
+ /* VBROADCASTI128 m128, ymm1 = VEX.256.66.0F38.WIG 5A /r */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/
+ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vbroadcasti128 %s,%s\n", dis_buf, nameYMMReg(rG));
+ IRTemp t128 = newTemp(Ity_V128);
+ assign(t128, loadLE(Ity_V128, mkexpr(addr)));
+ putYMMReg( rG, binop(Iop_V128HLtoV256, mkexpr(t128), mkexpr(t128)) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x78:
+ /* VPBROADCASTB xmm2/m8, xmm1 = VEX.128.66.0F38.W0 78 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp t8 = newTemp(Ity_I8);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ DIP("vpbroadcastb %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ assign(t8, unop(Iop_32to8, getXMMRegLane32(rE, 0)));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vpbroadcastb %s,%s\n", dis_buf, nameXMMReg(rG));
+ assign(t8, loadLE(Ity_I8, mkexpr(addr)));
+ }
+ IRTemp t16 = newTemp(Ity_I16);
+ assign(t16, binop(Iop_8HLto16, mkexpr(t8), mkexpr(t8)));
+ IRTemp t32 = newTemp(Ity_I32);
+ assign(t32, binop(Iop_16HLto32, mkexpr(t16), mkexpr(t16)));
+ IRTemp t64 = newTemp(Ity_I64);
+ assign(t64, binop(Iop_32HLto64, mkexpr(t32), mkexpr(t32)));
+ IRExpr* res = binop(Iop_64HLtoV128, mkexpr(t64), mkexpr(t64));
+ putYMMRegLoAndZU(rG, res);
+ goto decode_success;
+ }
+ /* VPBROADCASTB xmm2/m8, ymm1 = VEX.256.66.0F38.W0 78 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp t8 = newTemp(Ity_I8);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ DIP("vpbroadcastb %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
+ assign(t8, unop(Iop_32to8, getXMMRegLane32(rE, 0)));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vpbroadcastb %s,%s\n", dis_buf, nameYMMReg(rG));
+ assign(t8, loadLE(Ity_I8, mkexpr(addr)));
+ }
+ IRTemp t16 = newTemp(Ity_I16);
+ assign(t16, binop(Iop_8HLto16, mkexpr(t8), mkexpr(t8)));
+ IRTemp t32 = newTemp(Ity_I32);
+ assign(t32, binop(Iop_16HLto32, mkexpr(t16), mkexpr(t16)));
+ IRTemp t64 = newTemp(Ity_I64);
+ assign(t64, binop(Iop_32HLto64, mkexpr(t32), mkexpr(t32)));
+ IRExpr* res = IRExpr_Qop(Iop_64x4toV256, mkexpr(t64), mkexpr(t64),
+ mkexpr(t64), mkexpr(t64));
+ putYMMReg(rG, res);
+ goto decode_success;
+ }
+ break;
+
+ case 0x79:
+ /* VPBROADCASTW xmm2/m16, xmm1 = VEX.128.66.0F38.W0 79 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp t16 = newTemp(Ity_I16);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ DIP("vpbroadcastw %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ assign(t16, unop(Iop_32to16, getXMMRegLane32(rE, 0)));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vpbroadcastw %s,%s\n", dis_buf, nameXMMReg(rG));
+ assign(t16, loadLE(Ity_I16, mkexpr(addr)));
+ }
+ IRTemp t32 = newTemp(Ity_I32);
+ assign(t32, binop(Iop_16HLto32, mkexpr(t16), mkexpr(t16)));
+ IRTemp t64 = newTemp(Ity_I64);
+ assign(t64, binop(Iop_32HLto64, mkexpr(t32), mkexpr(t32)));
+ IRExpr* res = binop(Iop_64HLtoV128, mkexpr(t64), mkexpr(t64));
+ putYMMRegLoAndZU(rG, res);
+ goto decode_success;
+ }
+ /* VPBROADCASTW xmm2/m16, ymm1 = VEX.256.66.0F38.W0 79 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp t16 = newTemp(Ity_I16);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ DIP("vpbroadcastw %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
+ assign(t16, unop(Iop_32to16, getXMMRegLane32(rE, 0)));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vpbroadcastw %s,%s\n", dis_buf, nameYMMReg(rG));
+ assign(t16, loadLE(Ity_I16, mkexpr(addr)));
+ }
+ IRTemp t32 = newTemp(Ity_I32);
+ assign(t32, binop(Iop_16HLto32, mkexpr(t16), mkexpr(t16)));
+ IRTemp t64 = newTemp(Ity_I64);
+ assign(t64, binop(Iop_32HLto64, mkexpr(t32), mkexpr(t32)));
+ IRExpr* res = IRExpr_Qop(Iop_64x4toV256, mkexpr(t64), mkexpr(t64),
+ mkexpr(t64), mkexpr(t64));
+ putYMMReg(rG, res);
+ goto decode_success;
+ }
+ break;
+
+ case 0x8C:
+ /* VPMASKMOVD m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W0 8C /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 0==getRexW(pfx)/*W0*/ && !epartIsReg(getUChar(delta))) {
+ delta = dis_VMASKMOV_load( uses_vvvv, vbi, pfx, delta, "vpmaskmovd",
+ /*!isYMM*/False, Ity_I32 );
+ goto decode_success;
+ }
+ /* VPMASKMOVD m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 8C /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 0==getRexW(pfx)/*W0*/ && !epartIsReg(getUChar(delta))) {
+ delta = dis_VMASKMOV_load( uses_vvvv, vbi, pfx, delta, "vpmaskmovd",
+ /*isYMM*/True, Ity_I32 );
+ goto decode_success;
+ }
+ /* VPMASKMOVQ m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W1 8C /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 1==getRexW(pfx)/*W1*/ && !epartIsReg(getUChar(delta))) {
+ delta = dis_VMASKMOV_load( uses_vvvv, vbi, pfx, delta, "vpmaskmovq",
+ /*!isYMM*/False, Ity_I64 );
+ goto decode_success;
+ }
+ /* VPMASKMOVQ m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W1 8C /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 1==getRexW(pfx)/*W1*/ && !epartIsReg(getUChar(delta))) {
+ delta = dis_VMASKMOV_load( uses_vvvv, vbi, pfx, delta, "vpmaskmovq",
+ /*isYMM*/True, Ity_I64 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x90:
+ /* VPGATHERDD xmm2, vm32x, xmm1 = VEX.DDS.128.66.0F38.W0 90 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 0 == getRexW(pfx)/*W0*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vpgatherdd",
+ /*!isYMM*/False, /*!isVM64x*/False, Ity_I32 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ /* VPGATHERDD ymm2, vm32y, ymm1 = VEX.DDS.256.66.0F38.W0 90 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 0 == getRexW(pfx)/*W0*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vpgatherdd",
+ /*isYMM*/True, /*!isVM64x*/False, Ity_I32 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ /* VPGATHERDQ xmm2, vm32x, xmm1 = VEX.DDS.128.66.0F38.W1 90 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 1 == getRexW(pfx)/*W1*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vpgatherdq",
+ /*!isYMM*/False, /*!isVM64x*/False, Ity_I64 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ /* VPGATHERDQ ymm2, vm32x, ymm1 = VEX.DDS.256.66.0F38.W1 90 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 1 == getRexW(pfx)/*W1*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vpgatherdq",
+ /*isYMM*/True, /*!isVM64x*/False, Ity_I64 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ break;
+
+ case 0x91:
+ /* VPGATHERQD xmm2, vm64x, xmm1 = VEX.DDS.128.66.0F38.W0 91 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 0 == getRexW(pfx)/*W0*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vpgatherqd",
+ /*!isYMM*/False, /*isVM64x*/True, Ity_I32 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ /* VPGATHERQD xmm2, vm64y, xmm1 = VEX.DDS.256.66.0F38.W0 91 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 0 == getRexW(pfx)/*W0*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vpgatherqd",
+ /*isYMM*/True, /*isVM64x*/True, Ity_I32 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ /* VPGATHERQQ xmm2, vm64x, xmm1 = VEX.DDS.128.66.0F38.W1 91 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 1 == getRexW(pfx)/*W1*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vpgatherqq",
+ /*!isYMM*/False, /*isVM64x*/True, Ity_I64 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ /* VPGATHERQQ ymm2, vm64y, ymm1 = VEX.DDS.256.66.0F38.W1 91 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 1 == getRexW(pfx)/*W1*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vpgatherqq",
+ /*isYMM*/True, /*isVM64x*/True, Ity_I64 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ break;
+
+ case 0x92:
+ /* VGATHERDPS xmm2, vm32x, xmm1 = VEX.DDS.128.66.0F38.W0 92 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 0 == getRexW(pfx)/*W0*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vgatherdps",
+ /*!isYMM*/False, /*!isVM64x*/False, Ity_I32 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ /* VGATHERDPS ymm2, vm32y, ymm1 = VEX.DDS.256.66.0F38.W0 92 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 0 == getRexW(pfx)/*W0*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vgatherdps",
+ /*isYMM*/True, /*!isVM64x*/False, Ity_I32 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ /* VGATHERDPD xmm2, vm32x, xmm1 = VEX.DDS.128.66.0F38.W1 92 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 1 == getRexW(pfx)/*W1*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vgatherdpd",
+ /*!isYMM*/False, /*!isVM64x*/False, Ity_I64 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ /* VGATHERDPD ymm2, vm32x, ymm1 = VEX.DDS.256.66.0F38.W1 92 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 1 == getRexW(pfx)/*W1*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vgatherdpd",
+ /*isYMM*/True, /*!isVM64x*/False, Ity_I64 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ break;
+
+ case 0x93:
+ /* VGATHERQPS xmm2, vm64x, xmm1 = VEX.DDS.128.66.0F38.W0 93 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 0 == getRexW(pfx)/*W0*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vgatherqps",
+ /*!isYMM*/False, /*isVM64x*/True, Ity_I32 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ /* VGATHERQPS xmm2, vm64y, xmm1 = VEX.DDS.256.66.0F38.W0 93 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 0 == getRexW(pfx)/*W0*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vgatherqps",
+ /*isYMM*/True, /*isVM64x*/True, Ity_I32 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ /* VGATHERQPD xmm2, vm64x, xmm1 = VEX.DDS.128.66.0F38.W1 93 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 1 == getRexW(pfx)/*W1*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vgatherqpd",
+ /*!isYMM*/False, /*isVM64x*/True, Ity_I64 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ /* VGATHERQPD ymm2, vm64y, ymm1 = VEX.DDS.256.66.0F38.W1 93 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 1 == getRexW(pfx)/*W1*/ && !epartIsReg(getUChar(delta))) {
+ Long delta0 = delta;
+ delta = dis_VGATHER( uses_vvvv, vbi, pfx, delta, "vgatherqpd",
+ /*isYMM*/True, /*isVM64x*/True, Ity_I64 );
+ if (delta != delta0)
+ goto decode_success;
+ }
+ break;
+
+ case 0x96 ... 0x9F:
+ case 0xA6 ... 0xAF:
+ case 0xB6 ... 0xBF:
+ /* VFMADDSUB132PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 96 /r */
+ /* VFMADDSUB132PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 96 /r */
+ /* VFMADDSUB132PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 96 /r */
+ /* VFMADDSUB132PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 96 /r */
+ /* VFMSUBADD132PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 97 /r */
+ /* VFMSUBADD132PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 97 /r */
+ /* VFMSUBADD132PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 97 /r */
+ /* VFMSUBADD132PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 97 /r */
+ /* VFMADD132PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 98 /r */
+ /* VFMADD132PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 98 /r */
+ /* VFMADD132PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 98 /r */
+ /* VFMADD132PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 98 /r */
+ /* VFMADD132SS xmm3/m32, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W0 99 /r */
+ /* VFMADD132SD xmm3/m64, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W1 99 /r */
+ /* VFMSUB132PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 9A /r */
+ /* VFMSUB132PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 9A /r */
+ /* VFMSUB132PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 9A /r */
+ /* VFMSUB132PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 9A /r */
+ /* VFMSUB132SS xmm3/m32, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W0 9B /r */
+ /* VFMSUB132SD xmm3/m64, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W1 9B /r */
+ /* VFNMADD132PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 9C /r */
+ /* VFNMADD132PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 9C /r */
+ /* VFNMADD132PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 9C /r */
+ /* VFNMADD132PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 9C /r */
+ /* VFNMADD132SS xmm3/m32, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W0 9D /r */
+ /* VFNMADD132SD xmm3/m64, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W1 9D /r */
+ /* VFNMSUB132PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 9E /r */
+ /* VFNMSUB132PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 9E /r */
+ /* VFNMSUB132PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 9E /r */
+ /* VFNMSUB132PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 9E /r */
+ /* VFNMSUB132SS xmm3/m32, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W0 9F /r */
+ /* VFNMSUB132SD xmm3/m64, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W1 9F /r */
+ /* VFMADDSUB213PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 A6 /r */
+ /* VFMADDSUB213PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 A6 /r */
+ /* VFMADDSUB213PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 A6 /r */
+ /* VFMADDSUB213PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 A6 /r */
+ /* VFMSUBADD213PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 A7 /r */
+ /* VFMSUBADD213PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 A7 /r */
+ /* VFMSUBADD213PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 A7 /r */
+ /* VFMSUBADD213PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 A7 /r */
+ /* VFMADD213PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 A8 /r */
+ /* VFMADD213PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 A8 /r */
+ /* VFMADD213PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 A8 /r */
+ /* VFMADD213PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 A8 /r */
+ /* VFMADD213SS xmm3/m32, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W0 A9 /r */
+ /* VFMADD213SD xmm3/m64, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W1 A9 /r */
+ /* VFMSUB213PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 AA /r */
+ /* VFMSUB213PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 AA /r */
+ /* VFMSUB213PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 AA /r */
+ /* VFMSUB213PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 AA /r */
+ /* VFMSUB213SS xmm3/m32, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W0 AB /r */
+ /* VFMSUB213SD xmm3/m64, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W1 AB /r */
+ /* VFNMADD213PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 AC /r */
+ /* VFNMADD213PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 AC /r */
+ /* VFNMADD213PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 AC /r */
+ /* VFNMADD213PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 AC /r */
+ /* VFNMADD213SS xmm3/m32, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W0 AD /r */
+ /* VFNMADD213SD xmm3/m64, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W1 AD /r */
+ /* VFNMSUB213PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 AE /r */
+ /* VFNMSUB213PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 AE /r */
+ /* VFNMSUB213PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 AE /r */
+ /* VFNMSUB213PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 AE /r */
+ /* VFNMSUB213SS xmm3/m32, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W0 AF /r */
+ /* VFNMSUB213SD xmm3/m64, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W1 AF /r */
+ /* VFMADDSUB231PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 B6 /r */
+ /* VFMADDSUB231PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 B6 /r */
+ /* VFMADDSUB231PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 B6 /r */
+ /* VFMADDSUB231PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 B6 /r */
+ /* VFMSUBADD231PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 B7 /r */
+ /* VFMSUBADD231PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 B7 /r */
+ /* VFMSUBADD231PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 B7 /r */
+ /* VFMSUBADD231PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 B7 /r */
+ /* VFMADD231PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 B8 /r */
+ /* VFMADD231PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 B8 /r */
+ /* VFMADD231PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 B8 /r */
+ /* VFMADD231PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 B8 /r */
+ /* VFMADD231SS xmm3/m32, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W0 B9 /r */
+ /* VFMADD231SD xmm3/m64, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W1 B9 /r */
+ /* VFMSUB231PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 BA /r */
+ /* VFMSUB231PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 BA /r */
+ /* VFMSUB231PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 BA /r */
+ /* VFMSUB231PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 BA /r */
+ /* VFMSUB231SS xmm3/m32, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W0 BB /r */
+ /* VFMSUB231SD xmm3/m64, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W1 BB /r */
+ /* VFNMADD231PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 BC /r */
+ /* VFNMADD231PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 BC /r */
+ /* VFNMADD231PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 BC /r */
+ /* VFNMADD231PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 BC /r */
+ /* VFNMADD231SS xmm3/m32, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W0 BD /r */
+ /* VFNMADD231SD xmm3/m64, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W1 BD /r */
+ /* VFNMSUB231PS xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W0 BE /r */
+ /* VFNMSUB231PS ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W0 BE /r */
+ /* VFNMSUB231PD xmm3/m128, xmm2, xmm1 = VEX.DDS.128.66.0F38.W1 BE /r */
+ /* VFNMSUB231PD ymm3/m256, ymm2, ymm1 = VEX.DDS.256.66.0F38.W1 BE /r */
+ /* VFNMSUB231SS xmm3/m32, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W0 BF /r */
+ /* VFNMSUB231SD xmm3/m64, xmm2, xmm1 = VEX.DDS.LIG.66.0F38.W1 BF /r */
+ if (have66noF2noF3(pfx)) {
+ delta = dis_FMA( vbi, pfx, delta, opc );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0xDB:
+ case 0xDC:
+ case 0xDD:
+ case 0xDE:
+ case 0xDF:
+ /* VAESIMC xmm2/m128, xmm1 = VEX.128.66.0F38.WIG DB /r */
+ /* VAESENC xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DC /r */
+ /* VAESENCLAST xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DD /r */
+ /* VAESDEC xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DE /r */
+ /* VAESDECLAST xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DF /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AESx( vbi, pfx, delta, True/*!isAvx*/, opc );
+ if (opc != 0xDB) *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0xF2:
+ /* ANDN r/m32, r32b, r32a = VEX.NDS.LZ.0F38.W0 F2 /r */
+ /* ANDN r/m64, r64b, r64a = VEX.NDS.LZ.0F38.W1 F2 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*LZ*/ && !haveREX(pfx)) {
+ Int size = getRexW(pfx) ? 8 : 4;
+ IRType ty = szToITy(size);
+ IRTemp dst = newTemp(ty);
+ IRTemp src1 = newTemp(ty);
+ IRTemp src2 = newTemp(ty);
+ UChar rm = getUChar(delta);
+
+ assign( src1, getIRegV(size,pfx) );
+ if (epartIsReg(rm)) {
+ assign( src2, getIRegE(size,pfx,rm) );
+ DIP("andn %s,%s,%s\n", nameIRegE(size,pfx,rm),
+ nameIRegV(size,pfx), nameIRegG(size,pfx,rm));
+ delta++;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( src2, loadLE(ty, mkexpr(addr)) );
+ DIP("andn %s,%s,%s\n", dis_buf, nameIRegV(size,pfx),
+ nameIRegG(size,pfx,rm));
+ delta += alen;
+ }
+
+ assign( dst, binop( mkSizedOp(ty,Iop_And8),
+ unop( mkSizedOp(ty,Iop_Not8), mkexpr(src1) ),
+ mkexpr(src2) ) );
+ putIRegG( size, pfx, rm, mkexpr(dst) );
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(size == 8
+ ? AMD64G_CC_OP_ANDN64
+ : AMD64G_CC_OP_ANDN32)) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto64(mkexpr(dst))) );
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0)) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0xF3:
+ /* BLSI r/m32, r32 = VEX.NDD.LZ.0F38.W0 F3 /3 */
+ /* BLSI r/m64, r64 = VEX.NDD.LZ.0F38.W1 F3 /3 */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*LZ*/
+ && !haveREX(pfx) && gregLO3ofRM(getUChar(delta)) == 3) {
+ Int size = getRexW(pfx) ? 8 : 4;
+ IRType ty = szToITy(size);
+ IRTemp src = newTemp(ty);
+ IRTemp dst = newTemp(ty);
+ UChar rm = getUChar(delta);
+
+ if (epartIsReg(rm)) {
+ assign( src, getIRegE(size,pfx,rm) );
+ DIP("blsi %s,%s\n", nameIRegE(size,pfx,rm),
+ nameIRegV(size,pfx));
+ delta++;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( src, loadLE(ty, mkexpr(addr)) );
+ DIP("blsi %s,%s\n", dis_buf, nameIRegV(size,pfx));
+ delta += alen;
+ }
+
+ assign( dst, binop(mkSizedOp(ty,Iop_And8),
+ binop(mkSizedOp(ty,Iop_Sub8), mkU(ty, 0),
+ mkexpr(src)), mkexpr(src)) );
+ putIRegV( size, pfx, mkexpr(dst) );
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(size == 8
+ ? AMD64G_CC_OP_BLSI64
+ : AMD64G_CC_OP_BLSI32)) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto64(mkexpr(dst))) );
+ stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto64(mkexpr(src))) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* BLSMSK r/m32, r32 = VEX.NDD.LZ.0F38.W0 F3 /2 */
+ /* BLSMSK r/m64, r64 = VEX.NDD.LZ.0F38.W1 F3 /2 */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*LZ*/
+ && !haveREX(pfx) && gregLO3ofRM(getUChar(delta)) == 2) {
+ Int size = getRexW(pfx) ? 8 : 4;
+ IRType ty = szToITy(size);
+ IRTemp src = newTemp(ty);
+ IRTemp dst = newTemp(ty);
+ UChar rm = getUChar(delta);
+
+ if (epartIsReg(rm)) {
+ assign( src, getIRegE(size,pfx,rm) );
+ DIP("blsmsk %s,%s\n", nameIRegE(size,pfx,rm),
+ nameIRegV(size,pfx));
+ delta++;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( src, loadLE(ty, mkexpr(addr)) );
+ DIP("blsmsk %s,%s\n", dis_buf, nameIRegV(size,pfx));
+ delta += alen;
+ }
+
+ assign( dst, binop(mkSizedOp(ty,Iop_Xor8),
+ binop(mkSizedOp(ty,Iop_Sub8), mkexpr(src),
+ mkU(ty, 1)), mkexpr(src)) );
+ putIRegV( size, pfx, mkexpr(dst) );
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(size == 8
+ ? AMD64G_CC_OP_BLSMSK64
+ : AMD64G_CC_OP_BLSMSK32)) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto64(mkexpr(dst))) );
+ stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto64(mkexpr(src))) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* BLSR r/m32, r32 = VEX.NDD.LZ.0F38.W0 F3 /1 */
+ /* BLSR r/m64, r64 = VEX.NDD.LZ.0F38.W1 F3 /1 */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*LZ*/
+ && !haveREX(pfx) && gregLO3ofRM(getUChar(delta)) == 1) {
+ Int size = getRexW(pfx) ? 8 : 4;
+ IRType ty = szToITy(size);
+ IRTemp src = newTemp(ty);
+ IRTemp dst = newTemp(ty);
+ UChar rm = getUChar(delta);
+
+ if (epartIsReg(rm)) {
+ assign( src, getIRegE(size,pfx,rm) );
+ DIP("blsr %s,%s\n", nameIRegE(size,pfx,rm),
+ nameIRegV(size,pfx));
+ delta++;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( src, loadLE(ty, mkexpr(addr)) );
+ DIP("blsr %s,%s\n", dis_buf, nameIRegV(size,pfx));
+ delta += alen;
+ }
+
+ assign( dst, binop(mkSizedOp(ty,Iop_And8),
+ binop(mkSizedOp(ty,Iop_Sub8), mkexpr(src),
+ mkU(ty, 1)), mkexpr(src)) );
+ putIRegV( size, pfx, mkexpr(dst) );
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(size == 8
+ ? AMD64G_CC_OP_BLSR64
+ : AMD64G_CC_OP_BLSR32)) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto64(mkexpr(dst))) );
+ stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto64(mkexpr(src))) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0xF5:
+ /* BZHI r32b, r/m32, r32a = VEX.NDS.LZ.0F38.W0 F5 /r */
+ /* BZHI r64b, r/m64, r64a = VEX.NDS.LZ.0F38.W1 F5 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*LZ*/ && !haveREX(pfx)) {
+ Int size = getRexW(pfx) ? 8 : 4;
+ IRType ty = szToITy(size);
+ IRTemp dst = newTemp(ty);
+ IRTemp src1 = newTemp(ty);
+ IRTemp src2 = newTemp(ty);
+ IRTemp start = newTemp(Ity_I8);
+ IRTemp cond = newTemp(Ity_I8);
+ UChar rm = getUChar(delta);
+
+ assign( src2, getIRegV(size,pfx) );
+ if (epartIsReg(rm)) {
+ assign( src1, getIRegE(size,pfx,rm) );
+ DIP("bzhi %s,%s,%s\n", nameIRegV(size,pfx),
+ nameIRegE(size,pfx,rm), nameIRegG(size,pfx,rm));
+ delta++;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( src1, loadLE(ty, mkexpr(addr)) );
+ DIP("bzhi %s,%s,%s\n", nameIRegV(size,pfx), dis_buf,
+ nameIRegG(size,pfx,rm));
+ delta += alen;
+ }
+
+ assign( start, narrowTo( Ity_I8, mkexpr(src2) ) );
+ assign( cond, unop(Iop_1Uto8,
+ binop(Iop_CmpLT32U,
+ unop(Iop_8Uto32, mkexpr(start)),
+ mkU32(8*size))) );
+ /* if (start < opsize) {
+ if (start == 0)
+ dst = 0;
+ else
+ dst = (src1 << (opsize-start)) u>> (opsize-start);
+ } else {
+ dst = src1;
+ } */
+ assign( dst,
+ IRExpr_Mux0X(mkexpr(cond),
+ mkexpr(src1),
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(Iop_CmpEQ8, mkexpr(start), mkU8(0))),
+ binop(mkSizedOp(ty,Iop_Shr8),
+ binop(mkSizedOp(ty,Iop_Shl8), mkexpr(src1),
+ binop(Iop_Sub8, mkU8(8*size),
+ mkexpr(start))),
+ binop(Iop_Sub8, mkU8(8*size),
+ mkexpr(start))),
+ mkU(ty, 0))) );
+ putIRegG( size, pfx, rm, mkexpr(dst) );
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(size == 8
+ ? AMD64G_CC_OP_BLSR64
+ : AMD64G_CC_OP_BLSR32)) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto64(mkexpr(dst))) );
+ stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto64(mkexpr(cond))) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* PDEP r/m32, r32b, r32a = VEX.NDS.LZ.F2.0F38.W0 F5 /r */
+ /* PDEP r/m64, r64b, r64a = VEX.NDS.LZ.F2.0F38.W1 F5 /r */
+ if (haveF2no66noF3(pfx) && 0==getVexL(pfx)/*LZ*/ && !haveREX(pfx)) {
+ Int size = getRexW(pfx) ? 8 : 4;
+ IRType ty = szToITy(size);
+ IRTemp src = newTemp(ty);
+ IRTemp mask = newTemp(ty);
+ UChar rm = getUChar(delta);
+
+ assign( src, getIRegV(size,pfx) );
+ if (epartIsReg(rm)) {
+ assign( mask, getIRegE(size,pfx,rm) );
+ DIP("pdep %s,%s,%s\n", nameIRegE(size,pfx,rm),
+ nameIRegV(size,pfx), nameIRegG(size,pfx,rm));
+ delta++;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( mask, loadLE(ty, mkexpr(addr)) );
+ DIP("pdep %s,%s,%s\n", dis_buf, nameIRegV(size,pfx),
+ nameIRegG(size,pfx,rm));
+ delta += alen;
+ }
+
+ IRExpr** args = mkIRExprVec_2( widenUto64(mkexpr(src)),
+ widenUto64(mkexpr(mask)) );
+ putIRegG( size, pfx, rm,
+ narrowTo(ty, mkIRExprCCall(Ity_I64, 0/*regparms*/,
+ "amd64g_calculate_pdep",
+ &amd64g_calculate_pdep, args)) );
+ *uses_vvvv = True;
+ /* Flags aren't modified. */
+ goto decode_success;
+ }
+ /* PEXT r/m32, r32b, r32a = VEX.NDS.LZ.F3.0F38.W0 F5 /r */
+ /* PEXT r/m64, r64b, r64a = VEX.NDS.LZ.F3.0F38.W1 F5 /r */
+ if (haveF3no66noF2(pfx) && 0==getVexL(pfx)/*LZ*/ && !haveREX(pfx)) {
+ Int size = getRexW(pfx) ? 8 : 4;
+ IRType ty = szToITy(size);
+ IRTemp src = newTemp(ty);
+ IRTemp mask = newTemp(ty);
+ UChar rm = getUChar(delta);
+
+ assign( src, getIRegV(size,pfx) );
+ if (epartIsReg(rm)) {
+ assign( mask, getIRegE(size,pfx,rm) );
+ DIP("pext %s,%s,%s\n", nameIRegE(size,pfx,rm),
+ nameIRegV(size,pfx), nameIRegG(size,pfx,rm));
+ delta++;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( mask, loadLE(ty, mkexpr(addr)) );
+ DIP("pext %s,%s,%s\n", dis_buf, nameIRegV(size,pfx),
+ nameIRegG(size,pfx,rm));
+ delta += alen;
+ }
+
+ /* First mask off bits not set in mask, they are ignored
+ and it should be fine if they contain undefined values. */
+ IRExpr* masked = binop(mkSizedOp(ty,Iop_And8),
+ mkexpr(src), mkexpr(mask));
+ IRExpr** args = mkIRExprVec_2( widenUto64(masked),
+ widenUto64(mkexpr(mask)) );
+ putIRegG( size, pfx, rm,
+ narrowTo(ty, mkIRExprCCall(Ity_I64, 0/*regparms*/,
+ "amd64g_calculate_pext",
+ &amd64g_calculate_pext, args)) );
+ *uses_vvvv = True;
+ /* Flags aren't modified. */
+ goto decode_success;
+ }
+ break;
+
+ case 0xF6:
+ /* MULX r/m32, r32b, r32a = VEX.NDD.LZ.F2.0F38.W0 F6 /r */
+ /* MULX r/m64, r64b, r64a = VEX.NDD.LZ.F2.0F38.W1 F6 /r */
+ if (haveF2no66noF3(pfx) && 0==getVexL(pfx)/*LZ*/ && !haveREX(pfx)) {
+ Int size = getRexW(pfx) ? 8 : 4;
+ IRType ty = szToITy(size);
+ IRTemp src1 = newTemp(ty);
+ IRTemp src2 = newTemp(ty);
+ IRTemp res = newTemp(size == 8 ? Ity_I128 : Ity_I64);
+ UChar rm = getUChar(delta);
+
+ assign( src1, getIRegRDX(size) );
+ if (epartIsReg(rm)) {
+ assign( src2, getIRegE(size,pfx,rm) );
+ DIP("mulx %s,%s,%s\n", nameIRegE(size,pfx,rm),
+ nameIRegV(size,pfx), nameIRegG(size,pfx,rm));
+ delta++;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( src2, loadLE(ty, mkexpr(addr)) );
+ DIP("mulx %s,%s,%s\n", dis_buf, nameIRegV(size,pfx),
+ nameIRegG(size,pfx,rm));
+ delta += alen;
+ }
+
+ assign( res, binop(size == 8 ? Iop_MullU64 : Iop_MullU32,
+ mkexpr(src1), mkexpr(src2)) );
+ putIRegV( size, pfx,
+ unop(size == 8 ? Iop_128to64 : Iop_64to32, mkexpr(res)) );
+ putIRegG( size, pfx, rm,
+ unop(size == 8 ? Iop_128HIto64 : Iop_64HIto32,
+ mkexpr(res)) );
+ *uses_vvvv = True;
+ /* Flags aren't modified. */
+ goto decode_success;
+ }
+ break;
+
+ case 0xF7:
+ /* SARX r32b, r/m32, r32a = VEX.NDS.LZ.F3.0F38.W0 F7 /r */
+ /* SARX r64b, r/m64, r64a = VEX.NDS.LZ.F3.0F38.W1 F7 /r */
+ if (haveF3no66noF2(pfx) && 0==getVexL(pfx)/*LZ*/ && !haveREX(pfx)) {
+ delta = dis_SHIFTX( uses_vvvv, vbi, pfx, delta, "sarx", Iop_Sar8 );
+ goto decode_success;
+ }
+ /* SHLX r32b, r/m32, r32a = VEX.NDS.LZ.66.0F38.W0 F7 /r */
+ /* SHLX r64b, r/m64, r64a = VEX.NDS.LZ.66.0F38.W1 F7 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*LZ*/ && !haveREX(pfx)) {
+ delta = dis_SHIFTX( uses_vvvv, vbi, pfx, delta, "shlx", Iop_Shl8 );
+ goto decode_success;
+ }
+ /* SHRX r32b, r/m32, r32a = VEX.NDS.LZ.F2.0F38.W0 F7 /r */
+ /* SHRX r64b, r/m64, r64a = VEX.NDS.LZ.F2.0F38.W1 F7 /r */
+ if (haveF2no66noF3(pfx) && 0==getVexL(pfx)/*LZ*/ && !haveREX(pfx)) {
+ delta = dis_SHIFTX( uses_vvvv, vbi, pfx, delta, "shrx", Iop_Shr8 );
+ goto decode_success;
+ }
+ /* BEXTR r32b, r/m32, r32a = VEX.NDS.LZ.0F38.W0 F7 /r */
+ /* BEXTR r64b, r/m64, r64a = VEX.NDS.LZ.0F38.W1 F7 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*LZ*/ && !haveREX(pfx)) {
+ Int size = getRexW(pfx) ? 8 : 4;
+ IRType ty = szToITy(size);
+ IRTemp dst = newTemp(ty);
+ IRTemp src1 = newTemp(ty);
+ IRTemp src2 = newTemp(ty);
+ IRTemp stle = newTemp(Ity_I16);
+ IRTemp start = newTemp(Ity_I8);
+ IRTemp len = newTemp(Ity_I8);
+ UChar rm = getUChar(delta);
+
+ assign( src2, getIRegV(size,pfx) );
+ if (epartIsReg(rm)) {
+ assign( src1, getIRegE(size,pfx,rm) );
+ DIP("bextr %s,%s,%s\n", nameIRegV(size,pfx),
+ nameIRegE(size,pfx,rm), nameIRegG(size,pfx,rm));
+ delta++;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( src1, loadLE(ty, mkexpr(addr)) );
+ DIP("bextr %s,%s,%s\n", nameIRegV(size,pfx), dis_buf,
+ nameIRegG(size,pfx,rm));
+ delta += alen;
+ }
+
+ assign( stle, narrowTo( Ity_I16, mkexpr(src2) ) );
+ assign( start, unop( Iop_16to8, mkexpr(stle) ) );
+ assign( len, unop( Iop_16HIto8, mkexpr(stle) ) );
+ /* if (start+len < opsize) {
+ if (len != 0)
+ dst = (src1 << (opsize-start-len)) u>> (opsize-len);
+ else
+ dst = 0;
+ } else {
+ if (start < opsize)
+ dst = src1 u>> start;
+ else
+ dst = 0;
+ } */
+ assign( dst,
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(Iop_CmpLT32U,
+ binop(Iop_Add32,
+ unop(Iop_8Uto32, mkexpr(start)),
+ unop(Iop_8Uto32, mkexpr(len))),
+ mkU32(8*size))),
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(Iop_CmpLT32U,
+ unop(Iop_8Uto32, mkexpr(start)),
+ mkU32(8*size))),
+ mkU(ty, 0),
+ binop(mkSizedOp(ty,Iop_Shr8), mkexpr(src1),
+ mkexpr(start))),
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(Iop_CmpEQ8, mkexpr(len), mkU8(0))),
+ binop(mkSizedOp(ty,Iop_Shr8),
+ binop(mkSizedOp(ty,Iop_Shl8), mkexpr(src1),
+ binop(Iop_Sub8,
+ binop(Iop_Sub8, mkU8(8*size),
+ mkexpr(start)),
+ mkexpr(len))),
+ binop(Iop_Sub8, mkU8(8*size),
+ mkexpr(len))),
+ mkU(ty, 0))) );
+ putIRegG( size, pfx, rm, mkexpr(dst) );
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(size == 8
+ ? AMD64G_CC_OP_ANDN64
+ : AMD64G_CC_OP_ANDN32)) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto64(mkexpr(dst))) );
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0)) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ default:
+ break;
+
+ }
+
+ //decode_failure:
+ return deltaIN;
+
+ decode_success:
+ return delta;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level post-escape decoders: dis_ESC_0F3A__VEX ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+static IRTemp math_VPERMILPS_128 ( IRTemp sV, UInt imm8 )
+{
+ vassert(imm8 < 256);
+ IRTemp s3, s2, s1, s0;
+ s3 = s2 = s1 = s0 = IRTemp_INVALID;
+ breakupV128to32s( sV, &s3, &s2, &s1, &s0 );
+# define SEL(_nn) (((_nn)==0) ? s0 : ((_nn)==1) ? s1 \
+ : ((_nn)==2) ? s2 : s3)
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, mkV128from32s( SEL((imm8 >> 6) & 3),
+ SEL((imm8 >> 4) & 3),
+ SEL((imm8 >> 2) & 3),
+ SEL((imm8 >> 0) & 3) ));
+# undef SEL
+ return res;
+}
+
+__attribute__((noinline))
static
Long dis_ESC_0F3A__VEX (
/*MB_OUT*/DisResult* dres,
@@ -25258,7 +28818,132 @@
delta++;
*uses_vvvv = False;
- switch (opc) {
+ switch (opc) {
+
+ case 0x00:
+ case 0x01:
+ /* VPERMQ imm8, ymm2/m256, ymm1 = VEX.256.66.0F3A.W1 00 /r ib */
+ /* VPERMPD imm8, ymm2/m256, ymm1 = VEX.256.66.0F3A.W1 01 /r ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/
+ && 1==getRexW(pfx)/*W1*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8 = 0;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp sV = newTemp(Ity_V256);
+ UChar *name = opc == 0 ? "vpermq" : "vpermpd";
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("%s $%u,%s,%s\n",
+ name, imm8, nameYMMReg(rE), nameYMMReg(rG));
+ assign(sV, getYMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("%s $%u,%s,%s\n",
+ name, imm8, dis_buf, nameYMMReg(rG));
+ assign(sV, loadLE(Ity_V256, mkexpr(addr)));
+ }
+ delta++;
+ IRTemp s[4];
+ s[3] = s[2] = s[1] = s[0] = IRTemp_INVALID;
+ breakupV256to64s(sV, &s[3], &s[2], &s[1], &s[0]);
+ IRTemp dV = newTemp(Ity_V256);
+ assign(dV, IRExpr_Qop(Iop_64x4toV256,
+ mkexpr(s[(imm8 >> 6) & 3]),
+ mkexpr(s[(imm8 >> 4) & 3]),
+ mkexpr(s[(imm8 >> 2) & 3]),
+ mkexpr(s[(imm8 >> 0) & 3])));
+ putYMMReg(rG, mkexpr(dV));
+ goto decode_success;
+ }
+ break;
+
+ case 0x02:
+ /* VPBLENDD imm8, xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F3A.W0 02 /r ib */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8 = 0;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ UInt i;
+ IRTemp s[4], d[4];
+ assign(sV, getXMMReg(rV));
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vpblendd $%u,%s,%s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ assign(dV, getXMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vpblendd $%u,%s,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ assign(dV, loadLE(Ity_V128, mkexpr(addr)));
+ }
+ delta++;
+ for (i = 0; i < 4; i++) {
+ s[i] = IRTemp_INVALID;
+ d[i] = IRTemp_INVALID;
+ }
+ breakupV128to32s( sV, &s[3], &s[2], &s[1], &s[0] );
+ breakupV128to32s( dV, &d[3], &d[2], &d[1], &d[0] );
+ for (i = 0; i < 4; i++)
+ putYMMRegLane32(rG, i, mkexpr((imm8 & (1<<i)) ? d[i] : s[i]));
+ putYMMRegLane128(rG, 1, mkV128(0));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VPBLENDD imm8, ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F3A.W0 02 /r ib */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8 = 0;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp sV = newTemp(Ity_V256);
+ IRTemp dV = newTemp(Ity_V256);
+ UInt i;
+ IRTemp s[8], d[8];
+ assign(sV, getYMMReg(rV));
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vpblendd $%u,%s,%s,%s\n",
+ imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ assign(dV, getYMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vpblendd $%u,%s,%s,%s\n",
+ imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ assign(dV, loadLE(Ity_V256, mkexpr(addr)));
+ }
+ delta++;
+ for (i = 0; i < 8; i++) {
+ s[i] = IRTemp_INVALID;
+ d[i] = IRTemp_INVALID;
+ }
+ breakupV256to32s( sV, &s[7], &s[6], &s[5], &s[4],
+ &s[3], &s[2], &s[1], &s[0] );
+ breakupV256to32s( dV, &d[7], &d[6], &d[5], &d[4],
+ &d[3], &d[2], &d[1], &d[0] );
+ for (i = 0; i < 8; i++)
+ putYMMRegLane32(rG, i, mkexpr((imm8 & (1<<i)) ? d[i] : s[i]));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
case 0x04:
/* VPERMILPS imm8, ymm2/m256, ymm1 = VEX.256.66.0F3A.WIG 04 /r ib */
@@ -25843,7 +29528,7 @@
delta += alen;
imm8 = getUChar(delta);
DIP("vpblendw $%u,%s,%s,%s\n",
- imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG));
assign(sE, loadLE(Ity_V128, mkexpr(addr)));
}
delta++;
@@ -25852,6 +29537,42 @@
*uses_vvvv = True;
goto decode_success;
}
+ /* VPBLENDW imm8, ymm3/m256, ymm2, ymm1 */
+ /* VPBLENDW = VEX.NDS.256.66.0F3A.WIG 0E /r ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp sV = newTemp(Ity_V256);
+ IRTemp sE = newTemp(Ity_V256);
+ IRTemp sVhi, sVlo, sEhi, sElo;
+ sVhi = sVlo = sEhi = sElo = IRTemp_INVALID;
+ assign ( sV, getYMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vpblendw $%u,%s,%s,%s\n",
+ imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ assign(sE, getYMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vpblendw $%u,%s,%s,%s\n",
+ imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ assign(sE, loadLE(Ity_V256, mkexpr(addr)));
+ }
+ delta++;
+ breakupV256toV128s( sV, &sVhi, &sVlo );
+ breakupV256toV128s( sE, &sEhi, &sElo );
+ putYMMReg( rG, binop( Iop_V128HLtoV256,
+ mkexpr( math_PBLENDW_128( sEhi, sVhi, imm8) ),
+ mkexpr( math_PBLENDW_128( sElo, sVlo, imm8) ) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
case 0x0F:
@@ -25888,6 +29609,45 @@
*uses_vvvv = True;
goto decode_success;
}
+ /* VPALIGNR imm8, ymm3/m256, ymm2, ymm1 */
+ /* VPALIGNR = VEX.NDS.256.66.0F3A.WIG 0F /r ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp sV = newTemp(Ity_V256);
+ IRTemp dV = newTemp(Ity_V256);
+ IRTemp sHi, sLo, dHi, dLo;
+ sHi = sLo = dHi = dLo = IRTemp_INVALID;
+ UInt imm8;
+
+ assign( dV, getYMMReg(rV) );
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( sV, getYMMReg(rE) );
+ imm8 = getUChar(delta+1);
+ delta += 1+1;
+ DIP("vpalignr $%d,%s,%s,%s\n", imm8, nameYMMReg(rE),
+ nameYMMReg(rV), nameYMMReg(rG));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( sV, loadLE(Ity_V256, mkexpr(addr)) );
+ imm8 = getUChar(delta+alen);
+ delta += alen+1;
+ DIP("vpalignr $%d,%s,%s,%s\n", imm8, dis_buf,
+ nameYMMReg(rV), nameYMMReg(rG));
+ }
+
+ breakupV256toV128s( dV, &dHi, &dLo );
+ breakupV256toV128s( sV, &sHi, &sLo );
+ putYMMReg( rG, binop( Iop_V128HLtoV256,
+ mkexpr( math_PALIGNR_XMM( sHi, dHi, imm8 ) ),
+ mkexpr( math_PALIGNR_XMM( sLo, dLo, imm8 ) ) )
+ );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
case 0x14:
@@ -26143,6 +29903,74 @@
}
break;
+ case 0x38:
+ /* VINSERTI128 r/m, rV, rD
+ ::: rD = insertinto(a lane in rV, 128 bits from r/m) */
+ /* VINSERTI128 = VEX.NDS.256.66.0F3A.W0 38 /r ib */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt ib = 0;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp t128 = newTemp(Ity_V128);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ assign(t128, getXMMReg(rE));
+ ib = getUChar(delta);
+ DIP("vinserti128 $%u,%s,%s,%s\n",
+ ib, nameXMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign(t128, loadLE(Ity_V128, mkexpr(addr)));
+ delta += alen;
+ ib = getUChar(delta);
+ DIP("vinserti128 $%u,%s,%s,%s\n",
+ ib, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ }
+ delta++;
+ putYMMRegLane128(rG, 0, getYMMRegLane128(rV, 0));
+ putYMMRegLane128(rG, 1, getYMMRegLane128(rV, 1));
+ putYMMRegLane128(rG, ib & 1, mkexpr(t128));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x39:
+ /* VEXTRACTI128 $lane_no, rS, r/m
+ ::: r/m:V128 = a lane of rS:V256 (RM format) */
+ /* VEXTRACTI128 = VEX.256.66.0F3A.W0 39 /r ib */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt ib = 0;
+ UInt rS = gregOfRexRM(pfx, modrm);
+ IRTemp t128 = newTemp(Ity_V128);
+ if (epartIsReg(modrm)) {
+ UInt rD = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ ib = getUChar(delta);
+ assign(t128, getYMMRegLane128(rS, ib & 1));
+ putYMMRegLoAndZU(rD, mkexpr(t128));
+ DIP("vextracti128 $%u,%s,%s\n",
+ ib, nameXMMReg(rS), nameYMMReg(rD));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ ib = getUChar(delta);
+ assign(t128, getYMMRegLane128(rS, ib & 1));
+ storeLE(mkexpr(addr), mkexpr(t128));
+ DIP("vextracti128 $%u,%s,%s\n",
+ ib, nameYMMReg(rS), dis_buf);
+ }
+ delta++;
+ /* doesn't use vvvv */
+ goto decode_success;
+ }
+ break;
+
case 0x40:
/* VDPPS imm8, xmm3/m128,xmm2,xmm1 = VEX.NDS.128.66.0F3A.WIG 40 /r ib */
if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
@@ -26280,6 +30108,46 @@
*uses_vvvv = True;
goto decode_success;
}
+ /* VMPSADBW imm8, ymm3/m256,ymm2,ymm1 */
+ /* VMPSADBW = VEX.NDS.256.66.0F3A.WIG 42 /r ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ Int imm8;
+ IRTemp src_vec = newTemp(Ity_V256);
+ IRTemp dst_vec = newTemp(Ity_V256);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp sHi, sLo, dHi, dLo;
+ sHi = sLo = dHi = dLo = IRTemp_INVALID;
+
+ assign( dst_vec, getYMMReg(rV) );
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+
+ imm8 = (Int)getUChar(delta+1);
+ assign( src_vec, getYMMReg(rE) );
+ delta += 1+1;
+ DIP( "vmpsadbw $%d, %s,%s,%s\n", imm8,
+ nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf,
+ 1/* imm8 is 1 byte after the amode */ );
+ assign( src_vec, loadLE( Ity_V256, mkexpr(addr) ) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += alen+1;
+ DIP( "vmpsadbw $%d, %s,%s,%s\n", imm8,
+ dis_buf, nameYMMReg(rV), nameYMMReg(rG) );
+ }
+
+ breakupV256toV128s( dst_vec, &dHi, &dLo );
+ breakupV256toV128s( src_vec, &sHi, &sLo );
+ putYMMReg( rG, binop( Iop_V128HLtoV256,
+ mkexpr( math_MPSADBW_128(dHi, sHi, imm8 >> 3) ),
+ mkexpr( math_MPSADBW_128(dLo, sLo, imm8) ) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
case 0x44:
@@ -26322,6 +30190,52 @@
}
break;
+ case 0x46:
+ /* VPERM2I128 imm8, ymm3/m256, ymm2, ymm1 = VEX.NDS.66.0F3A.W0 46 /r ib */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8 = 0;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp s00 = newTemp(Ity_V128);
+ IRTemp s01 = newTemp(Ity_V128);
+ IRTemp s10 = newTemp(Ity_V128);
+ IRTemp s11 = newTemp(Ity_V128);
+ assign(s00, getYMMRegLane128(rV, 0));
+ assign(s01, getYMMRegLane128(rV, 1));
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vperm2i128 $%u,%s,%s,%s\n",
+ imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ assign(s10, getYMMRegLane128(rE, 0));
+ assign(s11, getYMMRegLane128(rE, 1));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vperm2i128 $%u,%s,%s,%s\n",
+ imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ assign(s10, loadLE(Ity_V128, binop(Iop_Add64,
+ mkexpr(addr), mkU64(0))));
+ assign(s11, loadLE(Ity_V128, binop(Iop_Add64,
+ mkexpr(addr), mkU64(16))));
+ }
+ delta++;
+# define SEL(_nn) (((_nn)==0) ? s00 : ((_nn)==1) ? s01 \
+ : ((_nn)==2) ? s10 : s11)
+ putYMMRegLane128(rG, 0, mkexpr(SEL((imm8 >> 0) & 3)));
+ putYMMRegLane128(rG, 1, mkexpr(SEL((imm8 >> 4) & 3)));
+# undef SEL
+ if (imm8 & (1<<3)) putYMMRegLane128(rG, 0, mkV128(0));
+ if (imm8 & (1<<7)) putYMMRegLane128(rG, 1, mkV128(0));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
case 0x4A:
/* VBLENDVPS xmmG, xmmE/memE, xmmV, xmmIS4
::: xmmG:V128 = PBLEND(xmmE, xmmV, xmmIS4) (RMVR) */
@@ -26374,6 +30288,15 @@
*uses_vvvv = True;
goto decode_success;
}
+ /* VPBLENDVB ymmG, ymmE/memE, ymmV, ymmIS4
+ ::: ymmG:V256 = PBLEND(ymmE, ymmV, ymmIS4) (RMVR) */
+ /* VPBLENDVB = VEX.NDS.256.66.0F3A.WIG 4C /r /is4 */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VBLENDV_256 ( vbi, pfx, delta,
+ "vpblendvb", 1, Iop_SarN8x16 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
break;
case 0x60:
@@ -26402,6 +30325,44 @@
goto decode_success;
}
break;
+
+ case 0xF0:
+ /* RORX imm8, r/m32, r32a = VEX.LZ.F2.0F3A.W0 F0 /r /i */
+ /* RORX imm8, r/m64, r64a = VEX.LZ.F2.0F3A.W1 F0 /r /i */
+ if (haveF2no66noF3(pfx) && 0==getVexL(pfx)/*LZ*/ && !haveREX(pfx)) {
+ Int size = getRexW(pfx) ? 8 : 4;
+ IRType ty = szToITy(size);
+ IRTemp src = newTemp(ty);
+ UChar rm = getUChar(delta);
+ UChar imm8;
+
+ if (epartIsReg(rm)) {
+ imm8 = getUChar(delta+1);
+ assign( src, getIRegE(size,pfx,rm) );
+ DIP("rorx %d,%s,%s\n", imm8, nameIRegE(size,pfx,rm),
+ nameIRegG(size,pfx,rm));
+ delta += 2;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ imm8 = getUChar(delta+alen);
+ assign( src, loadLE(ty, mkexpr(addr)) );
+ DIP("rorx %d,%s,%s\n", imm8, dis_buf, nameIRegG(size,pfx,rm));
+ delta += alen + 1;
+ }
+ imm8 &= 8*size-1;
+
+ /* dst = (src >>u imm8) | (src << (size-imm8)) */
+ putIRegG( size, pfx, rm,
+ imm8 == 0 ? mkexpr(src)
+ : binop( mkSizedOp(ty,Iop_Or8),
+ binop( mkSizedOp(ty,Iop_Shr8), mkexpr(src),
+ mkU8(imm8) ),
+ binop( mkSizedOp(ty,Iop_Shl8), mkexpr(src),
+ mkU8(8*size-imm8) ) ) );
+ /* Flags aren't modified. */
+ goto decode_success;
+ }
+ break;
default:
break;
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/priv/host_amd64_isel.c valgrind-3.8.0.new/VEX/priv/host_amd64_isel.c
--- valgrind-3.8.0.orig/VEX/priv/host_amd64_isel.c 2012-09-12 17:37:34.513929872 +0200
+++ valgrind-3.8.0.new/VEX/priv/host_amd64_isel.c 2012-09-12 19:55:08.897532132 +0200
@@ -43,6 +43,8 @@
#include "host_generic_regs.h"
#include "host_generic_simd64.h"
#include "host_generic_simd128.h"
+#include "host_generic_simd256.h"
+#include "host_generic_maddf.h"
#include "host_amd64_defs.h"
@@ -2457,6 +2459,73 @@
return dst;
}
+ if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_NegF32) {
+ /* Sigh ... very rough code. Could do much better. */
+ /* Get the 128-bit literal 00---0 10---0 into a register
+ and xor it with the value to be negated. */
+ HReg r1 = newVRegI(env);
+ HReg dst = newVRegV(env);
+ HReg tmp = newVRegV(env);
+ HReg src = iselFltExpr(env, e->Iex.Unop.arg);
+ AMD64AMode* rsp0 = AMD64AMode_IR(0, hregAMD64_RSP());
+ addInstr(env, mk_vMOVsd_RR(src,tmp));
+ addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));
+ addInstr(env, AMD64Instr_Imm64( 1ULL<<31, r1 ));
+ addInstr(env, AMD64Instr_Push(AMD64RMI_Reg(r1)));
+ addInstr(env, AMD64Instr_SseLdSt(True, 16, dst, rsp0));
+ addInstr(env, AMD64Instr_SseReRg(Asse_XOR, tmp, dst));
+ add_to_rsp(env, 16);
+ return dst;
+ }
+
+ if (e->tag == Iex_Qop && e->Iex.Qop.details->op == Iop_MAddF32) {
+ IRQop *qop = e->Iex.Qop.details;
+ HReg dst = newVRegV(env);
+ HReg argX = iselFltExpr(env, qop->arg2);
+ HReg argY = iselFltExpr(env, qop->arg3);
+ HReg argZ = iselFltExpr(env, qop->arg4);
+ /* XXXROUNDINGFIXME */
+ /* set roundingmode here */
+ /* subq $16, %rsp -- make a space*/
+ sub_from_rsp(env, 16);
+ /* Prepare 4 arg regs:
+ leaq 0(%rsp), %rdi
+ leaq 4(%rsp), %rsi
+ leaq 8(%rsp), %rdx
+ leaq 12(%rsp), %rcx
+ */
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(0, hregAMD64_RSP()),
+ hregAMD64_RDI()));
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(4, hregAMD64_RSP()),
+ hregAMD64_RSI()));
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(8, hregAMD64_RSP()),
+ hregAMD64_RDX()));
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(12, hregAMD64_RSP()),
+ hregAMD64_RCX()));
+ /* Store the three args, at (%rsi), (%rdx) and (%rcx):
+ movss %argX, 0(%rsi)
+ movss %argY, 0(%rdx)
+ movss %argZ, 0(%rcx)
+ */
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 4, argX,
+ AMD64AMode_IR(0, hregAMD64_RSI())));
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 4, argY,
+ AMD64AMode_IR(0, hregAMD64_RDX())));
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 4, argZ,
+ AMD64AMode_IR(0, hregAMD64_RCX())));
+ /* call the helper */
+ addInstr(env, AMD64Instr_Call( Acc_ALWAYS,
+ (ULong)(HWord)h_generic_calc_MAddF32,
+ 4 ));
+ /* fetch the result from memory, using %r_argp, which the
+ register allocator will keep alive across the call. */
+ addInstr(env, AMD64Instr_SseLdSt(True/*isLoad*/, 4, dst,
+ AMD64AMode_IR(0, hregAMD64_RSP())));
+ /* and finally, clear the space */
+ add_to_rsp(env, 16);
+ return dst;
+ }
+
ppIRExpr(e);
vpanic("iselFltExpr_wrk");
}
@@ -2588,6 +2657,54 @@
}
}
+ if (e->tag == Iex_Qop && e->Iex.Qop.details->op == Iop_MAddF64) {
+ IRQop *qop = e->Iex.Qop.details;
+ HReg dst = newVRegV(env);
+ HReg argX = iselDblExpr(env, qop->arg2);
+ HReg argY = iselDblExpr(env, qop->arg3);
+ HReg argZ = iselDblExpr(env, qop->arg4);
+ /* XXXROUNDINGFIXME */
+ /* set roundingmode here */
+ /* subq $32, %rsp -- make a space*/
+ sub_from_rsp(env, 32);
+ /* Prepare 4 arg regs:
+ leaq 0(%rsp), %rdi
+ leaq 8(%rsp), %rsi
+ leaq 16(%rsp), %rdx
+ leaq 24(%rsp), %rcx
+ */
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(0, hregAMD64_RSP()),
+ hregAMD64_RDI()));
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(8, hregAMD64_RSP()),
+ hregAMD64_RSI()));
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(16, hregAMD64_RSP()),
+ hregAMD64_RDX()));
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(24, hregAMD64_RSP()),
+ hregAMD64_RCX()));
+ /* Store the three args, at (%rsi), (%rdx) and (%rcx):
+ movsd %argX, 0(%rsi)
+ movsd %argY, 0(%rdx)
+ movsd %argZ, 0(%rcx)
+ */
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 8, argX,
+ AMD64AMode_IR(0, hregAMD64_RSI())));
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 8, argY,
+ AMD64AMode_IR(0, hregAMD64_RDX())));
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 8, argZ,
+ AMD64AMode_IR(0, hregAMD64_RCX())));
+ /* call the helper */
+ addInstr(env, AMD64Instr_Call( Acc_ALWAYS,
+ (ULong)(HWord)h_generic_calc_MAddF64,
+ 4 ));
+ /* fetch the result from memory, using %r_argp, which the
+ register allocator will keep alive across the call. */
+ addInstr(env, AMD64Instr_SseLdSt(True/*isLoad*/, 8, dst,
+ AMD64AMode_IR(0, hregAMD64_RSP())));
+ /* and finally, clear the space */
+ add_to_rsp(env, 32);
+ return dst;
+ }
+
if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_RoundF64toInt) {
AMD64AMode* m8_rsp = AMD64AMode_IR(-8, hregAMD64_RSP());
HReg arg = iselDblExpr(env, e->Iex.Binop.arg2);
@@ -3404,6 +3521,7 @@
static void iselDVecExpr_wrk ( /*OUT*/HReg* rHi, /*OUT*/HReg* rLo,
ISelEnv* env, IRExpr* e )
{
+ HWord fn = 0; /* address of helper fn, if required */
vassert(e);
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_V256);
@@ -3525,6 +3643,8 @@
}
case Iop_CmpNEZ32x8: op = Asse_CMPEQ32; goto do_CmpNEZ_vector;
+ case Iop_CmpNEZ16x16: op = Asse_CMPEQ16; goto do_CmpNEZ_vector;
+ case Iop_CmpNEZ8x32: op = Asse_CMPEQ8; goto do_CmpNEZ_vector;
do_CmpNEZ_vector:
{
HReg argHi, argLo;
@@ -3599,6 +3719,37 @@
case Iop_AndV256: op = Asse_AND; goto do_SseReRg;
case Iop_OrV256: op = Asse_OR; goto do_SseReRg;
case Iop_XorV256: op = Asse_XOR; goto do_SseReRg;
+ case Iop_Add8x32: op = Asse_ADD8; goto do_SseReRg;
+ case Iop_Add16x16: op = Asse_ADD16; goto do_SseReRg;
+ case Iop_Add32x8: op = Asse_ADD32; goto do_SseReRg;
+ case Iop_Add64x4: op = Asse_ADD64; goto do_SseReRg;
+ case Iop_QAdd8Sx32: op = Asse_QADD8S; goto do_SseReRg;
+ case Iop_QAdd16Sx16: op = Asse_QADD16S; goto do_SseReRg;
+ case Iop_QAdd8Ux32: op = Asse_QADD8U; goto do_SseReRg;
+ case Iop_QAdd16Ux16: op = Asse_QADD16U; goto do_SseReRg;
+ case Iop_Avg8Ux32: op = Asse_AVG8U; goto do_SseReRg;
+ case Iop_Avg16Ux16: op = Asse_AVG16U; goto do_SseReRg;
+ case Iop_CmpEQ8x32: op = Asse_CMPEQ8; goto do_SseReRg;
+ case Iop_CmpEQ16x16: op = Asse_CMPEQ16; goto do_SseReRg;
+ case Iop_CmpEQ32x8: op = Asse_CMPEQ32; goto do_SseReRg;
+ case Iop_CmpGT8Sx32: op = Asse_CMPGT8S; goto do_SseReRg;
+ case Iop_CmpGT16Sx16: op = Asse_CMPGT16S; goto do_SseReRg;
+ case Iop_CmpGT32Sx8: op = Asse_CMPGT32S; goto do_SseReRg;
+ case Iop_Max16Sx16: op = Asse_MAX16S; goto do_SseReRg;
+ case Iop_Max8Ux32: op = Asse_MAX8U; goto do_SseReRg;
+ case Iop_Min16Sx16: op = Asse_MIN16S; goto do_SseReRg;
+ case Iop_Min8Ux32: op = Asse_MIN8U; goto do_SseReRg;
+ case Iop_MulHi16Ux16: op = Asse_MULHI16U; goto do_SseReRg;
+ case Iop_MulHi16Sx16: op = Asse_MULHI16S; goto do_SseReRg;
+ case Iop_Mul16x16: op = Asse_MUL16; goto do_SseReRg;
+ case Iop_Sub8x32: op = Asse_SUB8; goto do_SseReRg;
+ case Iop_Sub16x16: op = Asse_SUB16; goto do_SseReRg;
+ case Iop_Sub32x8: op = Asse_SUB32; goto do_SseReRg;
+ case Iop_Sub64x4: op = Asse_SUB64; goto do_SseReRg;
+ case Iop_QSub8Sx32: op = Asse_QSUB8S; goto do_SseReRg;
+ case Iop_QSub16Sx16: op = Asse_QSUB16S; goto do_SseReRg;
+ case Iop_QSub8Ux32: op = Asse_QSUB8U; goto do_SseReRg;
+ case Iop_QSub16Ux16: op = Asse_QSUB16U; goto do_SseReRg;
do_SseReRg:
{
HReg argLhi, argLlo, argRhi, argRlo;
@@ -3615,12 +3766,198 @@
return;
}
+ case Iop_ShlN16x16: op = Asse_SHL16; goto do_SseShift;
+ case Iop_ShlN32x8: op = Asse_SHL32; goto do_SseShift;
+ case Iop_ShlN64x4: op = Asse_SHL64; goto do_SseShift;
+ case Iop_SarN16x16: op = Asse_SAR16; goto do_SseShift;
+ case Iop_SarN32x8: op = Asse_SAR32; goto do_SseShift;
+ case Iop_ShrN16x16: op = Asse_SHR16; goto do_SseShift;
+ case Iop_ShrN32x8: op = Asse_SHR32; goto do_SseShift;
+ case Iop_ShrN64x4: op = Asse_SHR64; goto do_SseShift;
+ do_SseShift: {
+ HReg gregHi, gregLo;
+ iselDVecExpr(&gregHi, &gregLo, env, e->Iex.Binop.arg1);
+ AMD64RMI* rmi = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
+ AMD64AMode* rsp0 = AMD64AMode_IR(0, hregAMD64_RSP());
+ HReg ereg = newVRegV(env);
+ HReg dstHi = newVRegV(env);
+ HReg dstLo = newVRegV(env);
+ addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));
+ addInstr(env, AMD64Instr_Push(rmi));
+ addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, ereg, rsp0));
+ addInstr(env, mk_vMOVsd_RR(gregHi, dstHi));
+ addInstr(env, AMD64Instr_SseReRg(op, ereg, dstHi));
+ addInstr(env, mk_vMOVsd_RR(gregLo, dstLo));
+ addInstr(env, AMD64Instr_SseReRg(op, ereg, dstLo));
+ add_to_rsp(env, 16);
+ *rHi = dstHi;
+ *rLo = dstLo;
+ return;
+ }
+
case Iop_V128HLtoV256: {
*rHi = iselVecExpr(env, e->Iex.Binop.arg1);
*rLo = iselVecExpr(env, e->Iex.Binop.arg2);
return;
}
+ case Iop_Mul32x8: fn = (HWord)h_generic_calc_Mul32x4;
+ goto do_SseAssistedBinary;
+ case Iop_Max32Sx8: fn = (HWord)h_generic_calc_Max32Sx4;
+ goto do_SseAssistedBinary;
+ case Iop_Min32Sx8: fn = (HWord)h_generic_calc_Min32Sx4;
+ goto do_SseAssistedBinary;
+ case Iop_Max32Ux8: fn = (HWord)h_generic_calc_Max32Ux4;
+ goto do_SseAssistedBinary;
+ case Iop_Min32Ux8: fn = (HWord)h_generic_calc_Min32Ux4;
+ goto do_SseAssistedBinary;
+ case Iop_Max16Ux16: fn = (HWord)h_generic_calc_Max16Ux8;
+ goto do_SseAssistedBinary;
+ case Iop_Min16Ux16: fn = (HWord)h_generic_calc_Min16Ux8;
+ goto do_SseAssistedBinary;
+ case Iop_Max8Sx32: fn = (HWord)h_generic_calc_Max8Sx16;
+ goto do_SseAssistedBinary;
+ case Iop_Min8Sx32: fn = (HWord)h_generic_calc_Min8Sx16;
+ goto do_SseAssistedBinary;
+ case Iop_CmpEQ64x4: fn = (HWord)h_generic_calc_CmpEQ64x2;
+ goto do_SseAssistedBinary;
+ case Iop_CmpGT64Sx4: fn = (HWord)h_generic_calc_CmpGT64Sx2;
+ goto do_SseAssistedBinary;
+ do_SseAssistedBinary: {
+ /* RRRufff! RRRufff code is what we're generating here. Oh
+ well. */
+ vassert(fn != 0);
+ HReg dstHi = newVRegV(env);
+ HReg dstLo = newVRegV(env);
+ HReg argLhi, argLlo, argRhi, argRlo;
+ iselDVecExpr(&argLhi, &argLlo, env, e->Iex.Binop.arg1);
+ iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2);
+ HReg argp = newVRegI(env);
+ /* subq $160, %rsp -- make a space*/
+ sub_from_rsp(env, 160);
+ /* leaq 48(%rsp), %r_argp -- point into it */
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(48, hregAMD64_RSP()),
+ argp));
+ /* andq $-16, %r_argp -- 16-align the pointer */
+ addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
+ AMD64RMI_Imm( ~(UInt)15 ),
+ argp));
+ /* Prepare 3 arg regs:
+ leaq 0(%r_argp), %rdi
+ leaq 16(%r_argp), %rsi
+ leaq 32(%r_argp), %rdx
+ */
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(0, argp),
+ hregAMD64_RDI()));
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(16, argp),
+ hregAMD64_RSI()));
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(32, argp),
+ hregAMD64_RDX()));
+ /* Store the two high args, at (%rsi) and (%rdx):
+ movupd %argLhi, 0(%rsi)
+ movupd %argRhi, 0(%rdx)
+ */
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argLhi,
+ AMD64AMode_IR(0, hregAMD64_RSI())));
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argRhi,
+ AMD64AMode_IR(0, hregAMD64_RDX())));
+ /* Store the two low args, at 48(%rsi) and 48(%rdx):
+ movupd %argLlo, 48(%rsi)
+ movupd %argRlo, 48(%rdx)
+ */
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argLlo,
+ AMD64AMode_IR(48, hregAMD64_RSI())));
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argRlo,
+ AMD64AMode_IR(48, hregAMD64_RDX())));
+ /* call the helper */
+ addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 3 ));
+ /* Prepare 3 arg regs:
+ leaq 48(%r_argp), %rdi
+ leaq 64(%r_argp), %rsi
+ leaq 80(%r_argp), %rdx
+ */
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(48, argp),
+ hregAMD64_RDI()));
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(64, argp),
+ hregAMD64_RSI()));
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(80, argp),
+ hregAMD64_RDX()));
+ /* call the helper */
+ addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 3 ));
+ /* fetch the result from memory, using %r_argp, which the
+ register allocator will keep alive across the call. */
+ addInstr(env, AMD64Instr_SseLdSt(True/*isLoad*/, 16, dstHi,
+ AMD64AMode_IR(0, argp)));
+ addInstr(env, AMD64Instr_SseLdSt(True/*isLoad*/, 16, dstLo,
+ AMD64AMode_IR(48, argp)));
+ /* and finally, clear the space */
+ add_to_rsp(env, 160);
+ *rHi = dstHi;
+ *rLo = dstLo;
+ return;
+ }
+
+ case Iop_Perm32x8: fn = (HWord)h_generic_calc_Perm32x8;
+ goto do_SseAssistedBinary256;
+ do_SseAssistedBinary256: {
+ /* RRRufff! RRRufff code is what we're generating here. Oh
+ well. */
+ vassert(fn != 0);
+ HReg dstHi = newVRegV(env);
+ HReg dstLo = newVRegV(env);
+ HReg argLhi, argLlo, argRhi, argRlo;
+ iselDVecExpr(&argLhi, &argLlo, env, e->Iex.Binop.arg1);
+ iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2);
+ HReg argp = newVRegI(env);
+ /* subq $160, %rsp -- make a space*/
+ sub_from_rsp(env, 160);
+ /* leaq 48(%rsp), %r_argp -- point into it */
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(48, hregAMD64_RSP()),
+ argp));
+ /* andq $-16, %r_argp -- 16-align the pointer */
+ addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
+ AMD64RMI_Imm( ~(UInt)15 ),
+ argp));
+ /* Prepare 3 arg regs:
+ leaq 0(%r_argp), %rdi
+ leaq 32(%r_argp), %rsi
+ leaq 64(%r_argp), %rdx
+ */
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(0, argp),
+ hregAMD64_RDI()));
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(32, argp),
+ hregAMD64_RSI()));
+ addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(64, argp),
+ hregAMD64_RDX()));
+ /* Store the two args, at (%rsi) and (%rdx):
+ movupd %argLlo, 0(%rsi)
+ movupd %argLhi, 16(%rsi)
+ movupd %argRlo, 0(%rdx)
+ movupd %argRhi, 16(%rdx)
+ */
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argLlo,
+ AMD64AMode_IR(0, hregAMD64_RSI())));
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argLhi,
+ AMD64AMode_IR(16, hregAMD64_RSI())));
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argRlo,
+ AMD64AMode_IR(0, hregAMD64_RDX())));
+ addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argRhi,
+ AMD64AMode_IR(16, hregAMD64_RDX())));
+ /* call the helper */
+ addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 3 ));
+ /* fetch the result from memory, using %r_argp, which the
+ register allocator will keep alive across the call. */
+ addInstr(env, AMD64Instr_SseLdSt(True/*isLoad*/, 16, dstLo,
+ AMD64AMode_IR(0, argp)));
+ addInstr(env, AMD64Instr_SseLdSt(True/*isLoad*/, 16, dstHi,
+ AMD64AMode_IR(16, argp)));
+ /* and finally, clear the space */
+ add_to_rsp(env, 160);
+ *rHi = dstHi;
+ *rLo = dstLo;
+ return;
+ }
+
default:
break;
} /* switch (e->Iex.Binop.op) */
@@ -3651,6 +3988,23 @@
return;
}
+ if (e->tag == Iex_Mux0X) {
+ HReg r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
+ HReg rXhi, rXlo, r0hi, r0lo;
+ iselDVecExpr(&rXhi, &rXlo, env, e->Iex.Mux0X.exprX);
+ iselDVecExpr(&r0hi, &r0lo, env, e->Iex.Mux0X.expr0);
+ HReg dstHi = newVRegV(env);
+ HReg dstLo = newVRegV(env);
+ addInstr(env, mk_vMOVsd_RR(rXhi,dstHi));
+ addInstr(env, AMD64Instr_Test64(0xFF, r8));
+ addInstr(env, AMD64Instr_SseCMov(Acc_Z,r0hi,dstHi));
+ addInstr(env, mk_vMOVsd_RR(rXlo,dstLo));
+ addInstr(env, AMD64Instr_SseCMov(Acc_Z,r0lo,dstLo));
+ *rHi = dstHi;
+ *rLo = dstLo;
+ return;
+ }
+
//avx_fail:
vex_printf("iselDVecExpr (amd64, subarch = %s): can't reduce\n",
LibVEX_ppVexHwCaps(VexArchAMD64, env->hwcaps));
@@ -4207,7 +4561,9 @@
& ~(VEX_HWCAPS_AMD64_SSE3
| VEX_HWCAPS_AMD64_CX16
| VEX_HWCAPS_AMD64_LZCNT
- | VEX_HWCAPS_AMD64_AVX)));
+ | VEX_HWCAPS_AMD64_AVX
+ | VEX_HWCAPS_AMD64_BMI
+ | VEX_HWCAPS_AMD64_AVX2)));
/* Make up an initial environment to use. */
env = LibVEX_Alloc(sizeof(ISelEnv));
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/priv/host_generic_maddf.c valgrind-3.8.0.new/VEX/priv/host_generic_maddf.c
--- valgrind-3.8.0.orig/VEX/priv/host_generic_maddf.c 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/VEX/priv/host_generic_maddf.c 2012-09-12 19:54:55.746334068 +0200
@@ -0,0 +1,324 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin host_generic_maddf.c ---*/
+/*---------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2012 OpenWorks GbR
+ info@open-works.net
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+/* Generic helper functions for doing FMA, i.e. compute x * y + z
+ as ternary operation.
+ These are purely back-end entities and cannot be seen/referenced
+ from IR. */
+
+#include "libvex_basictypes.h"
+#include "host_generic_maddf.h"
+#include "main_util.h"
+
+/* This implementation relies on Double being more than twice as
+ precise as Float and uses rounding to odd in order to avoid problems
+ with double rounding.
+ See a paper by Boldo and Melquiond:
+ http://www.lri.fr/~melquion/doc/08-tc.pdf */
+
+#define FORCE_EVAL(X) __asm __volatile__ ("" : : "m" (X))
+
+#if defined(__x86_64__) && defined(__SSE2_MATH__)
+# define ENV_TYPE unsigned int
+/* Save current rounding mode into ENV, hold exceptions, set rounding
+ mode to rounding toward zero. */
+# define ROUNDTOZERO(env) \
+ do { \
+ unsigned int mxcsr; \
+ __asm __volatile__ ("stmxcsr %0" : "=m" (mxcsr)); \
+ (env) = mxcsr; \
+ mxcsr = (mxcsr | 0x7f80) & ~0x3f; \
+ __asm __volatile__ ("ldmxcsr %0" : : "m" (mxcsr));\
+ } while (0)
+/* Restore exceptions from ENV, return if inexact exception has been raised
+ since ROUNDTOZERO. */
+# define RESET_TESTINEXACT(env) \
+ ({ \
+ unsigned int mxcsr, ret; \
+ __asm __volatile__ ("stmxcsr %0" : "=m" (mxcsr)); \
+ ret = (mxcsr >> 5) & 1; \
+ mxcsr = (mxcsr & 0x3d) | (env); \
+ __asm __volatile__ ("ldmxcsr %0" : : "m" (mxcsr));\
+ ret; \
+ })
+/* Return if inexact exception has been raised since ROUNDTOZERO. */
+# define TESTINEXACT() \
+ ({ \
+ unsigned int mxcsr; \
+ __asm __volatile__ ("stmxcsr %0" : "=m" (mxcsr)); \
+ (mxcsr >> 5) & 1; \
+ })
+#endif
+
+#define DBL_MANT_DIG 53
+#define IEEE754_DOUBLE_BIAS 0x3ff
+
+union vg_ieee754_double {
+ Double d;
+
+ /* This is the IEEE 754 double-precision format. */
+ struct {
+#ifdef VKI_BIG_ENDIAN
+ unsigned int negative:1;
+ unsigned int exponent:11;
+ unsigned int mantissa0:20;
+ unsigned int mantissa1:32;
+#else
+ unsigned int mantissa1:32;
+ unsigned int mantissa0:20;
+ unsigned int exponent:11;
+ unsigned int negative:1;
+#
+#endif
+ } ieee;
+};
+
+void VEX_REGPARM(3)
+ h_generic_calc_MAddF32 ( /*OUT*/Float* res,
+ Float* argX, Float* argY, Float* argZ )
+{
+#ifndef ENV_TYPE
+ /* Lame fallback implementation. */
+ *res = *argX * *argY + *argZ;
+#else
+ ENV_TYPE env;
+ /* Multiplication is always exact. */
+ Double temp = (Double) *argX * (Double) *argY;
+ union vg_ieee754_double u;
+
+ ROUNDTOZERO (env);
+
+ /* Perform addition with round to odd. */
+ u.d = temp + (Double) *argZ;
+ /* Ensure the addition is not scheduled after fetestexcept call. */
+ FORCE_EVAL (u.d);
+
+ /* Reset rounding mode and test for inexact simultaneously. */
+ int j = RESET_TESTINEXACT (env);
+
+ if ((u.ieee.mantissa1 & 1) == 0 && u.ieee.exponent != 0x7ff)
+ u.ieee.mantissa1 |= j;
+
+ /* And finally truncation with round to nearest. */
+ *res = (Float) u.d;
+#endif
+}
+
+
+void VEX_REGPARM(3)
+ h_generic_calc_MAddF64 ( /*OUT*/Double* res,
+ Double* argX, Double* argY, Double* argZ )
+{
+#ifndef ENV_TYPE
+ /* Lame fallback implementation. */
+ *res = *argX * *argY + *argZ;
+#else
+ Double x = *argX, y = *argY, z = *argZ;
+ union vg_ieee754_double u, v, w;
+ int adjust = 0;
+ u.d = x;
+ v.d = y;
+ w.d = z;
+ if (UNLIKELY (u.ieee.exponent + v.ieee.exponent
+ >= 0x7ff + IEEE754_DOUBLE_BIAS - DBL_MANT_DIG)
+ || UNLIKELY (u.ieee.exponent >= 0x7ff - DBL_MANT_DIG)
+ || UNLIKELY (v.ieee.exponent >= 0x7ff - DBL_MANT_DIG)
+ || UNLIKELY (w.ieee.exponent >= 0x7ff - DBL_MANT_DIG)
+ || UNLIKELY (u.ieee.exponent + v.ieee.exponent
+ <= IEEE754_DOUBLE_BIAS + DBL_MANT_DIG)) {
+ /* If z is Inf, but x and y are finite, the result should be
+ z rather than NaN. */
+ if (w.ieee.exponent == 0x7ff
+ && u.ieee.exponent != 0x7ff
+ && v.ieee.exponent != 0x7ff) {
+ *res = (z + x) + y;
+ return;
+ }
+ /* If x or y or z is Inf/NaN, or if fma will certainly overflow,
+ or if x * y is less than half of DBL_DENORM_MIN,
+ compute as x * y + z. */
+ if (u.ieee.exponent == 0x7ff
+ || v.ieee.exponent == 0x7ff
+ || w.ieee.exponent == 0x7ff
+ || u.ieee.exponent + v.ieee.exponent > 0x7ff + IEEE754_DOUBLE_BIAS
+ || u.ieee.exponent + v.ieee.exponent
+ < IEEE754_DOUBLE_BIAS - DBL_MANT_DIG - 2) {
+ *res = x * y + z;
+ return;
+ }
+ if (u.ieee.exponent + v.ieee.exponent
+ >= 0x7ff + IEEE754_DOUBLE_BIAS - DBL_MANT_DIG) {
+ /* Compute 1p-53 times smaller result and multiply
+ at the end. */
+ if (u.ieee.exponent > v.ieee.exponent)
+ u.ieee.exponent -= DBL_MANT_DIG;
+ else
+ v.ieee.exponent -= DBL_MANT_DIG;
+ /* If x + y exponent is very large and z exponent is very small,
+ it doesn't matter if we don't adjust it. */
+ if (w.ieee.exponent > DBL_MANT_DIG)
+ w.ieee.exponent -= DBL_MANT_DIG;
+ adjust = 1;
+ } else if (w.ieee.exponent >= 0x7ff - DBL_MANT_DIG) {
+ /* Similarly.
+ If z exponent is very large and x and y exponents are
+ very small, it doesn't matter if we don't adjust it. */
+ if (u.ieee.exponent > v.ieee.exponent) {
+ if (u.ieee.exponent > DBL_MANT_DIG)
+ u.ieee.exponent -= DBL_MANT_DIG;
+ } else if (v.ieee.exponent > DBL_MANT_DIG)
+ v.ieee.exponent -= DBL_MANT_DIG;
+ w.ieee.exponent -= DBL_MANT_DIG;
+ adjust = 1;
+ } else if (u.ieee.exponent >= 0x7ff - DBL_MANT_DIG) {
+ u.ieee.exponent -= DBL_MANT_DIG;
+ if (v.ieee.exponent)
+ v.ieee.exponent += DBL_MANT_DIG;
+ else
+ v.d *= 0x1p53;
+ } else if (v.ieee.exponent >= 0x7ff - DBL_MANT_DIG) {
+ v.ieee.exponent -= DBL_MANT_DIG;
+ if (u.ieee.exponent)
+ u.ieee.exponent += DBL_MANT_DIG;
+ else
+ u.d *= 0x1p53;
+ } else /* if (u.ieee.exponent + v.ieee.exponent
+ <= IEEE754_DOUBLE_BIAS + DBL_MANT_DIG) */ {
+ if (u.ieee.exponent > v.ieee.exponent)
+ u.ieee.exponent += 2 * DBL_MANT_DIG;
+ else
+ v.ieee.exponent += 2 * DBL_MANT_DIG;
+ if (w.ieee.exponent <= 4 * DBL_MANT_DIG + 4) {
+ if (w.ieee.exponent)
+ w.ieee.exponent += 2 * DBL_MANT_DIG;
+ else
+ w.d *= 0x1p106;
+ adjust = -1;
+ }
+ /* Otherwise x * y should just affect inexact
+ and nothing else. */
+ }
+ x = u.d;
+ y = v.d;
+ z = w.d;
+ }
+ /* Multiplication m1 + m2 = x * y using Dekker's algorithm. */
+#define C ((1 << (DBL_MANT_DIG + 1) / 2) + 1)
+ Double x1 = x * C;
+ Double y1 = y * C;
+ Double m1 = x * y;
+ x1 = (x - x1) + x1;
+ y1 = (y - y1) + y1;
+ Double x2 = x - x1;
+ Double y2 = y - y1;
+ Double m2 = (((x1 * y1 - m1) + x1 * y2) + x2 * y1) + x2 * y2;
+
+ /* Addition a1 + a2 = z + m1 using Knuth's algorithm. */
+ Double a1 = z + m1;
+ Double t1 = a1 - z;
+ Double t2 = a1 - t1;
+ t1 = m1 - t1;
+ t2 = z - t2;
+ Double a2 = t1 + t2;
+
+ ENV_TYPE env;
+ ROUNDTOZERO (env);
+
+ /* Perform m2 + a2 addition with round to odd. */
+ u.d = a2 + m2;
+
+ if (UNLIKELY (adjust < 0)) {
+ if ((u.ieee.mantissa1 & 1) == 0)
+ u.ieee.mantissa1 |= TESTINEXACT ();
+ v.d = a1 + u.d;
+ /* Ensure the addition is not scheduled after fetestexcept call. */
+ FORCE_EVAL (v.d);
+ }
+
+ /* Reset rounding mode and test for inexact simultaneously. */
+ int j = RESET_TESTINEXACT (env) != 0;
+
+ if (LIKELY (adjust == 0)) {
+ if ((u.ieee.mantissa1 & 1) == 0 && u.ieee.exponent != 0x7ff)
+ u.ieee.mantissa1 |= j;
+ /* Result is a1 + u.d. */
+ *res = a1 + u.d;
+ } else if (LIKELY (adjust > 0)) {
+ if ((u.ieee.mantissa1 & 1) == 0 && u.ieee.exponent != 0x7ff)
+ u.ieee.mantissa1 |= j;
+ /* Result is a1 + u.d, scaled up. */
+ *res = (a1 + u.d) * 0x1p53;
+ } else {
+ /* If a1 + u.d is exact, the only rounding happens during
+ scaling down. */
+ if (j == 0) {
+ *res = v.d * 0x1p-106;
+ return;
+ }
+ /* If result rounded to zero is not subnormal, no double
+ rounding will occur. */
+ if (v.ieee.exponent > 106) {
+ *res = (a1 + u.d) * 0x1p-106;
+ return;
+ }
+ /* If v.d * 0x1p-106 with round to zero is a subnormal above
+ or equal to DBL_MIN / 2, then v.d * 0x1p-106 shifts mantissa
+ down just by 1 bit, which means v.ieee.mantissa1 |= j would
+ change the round bit, not sticky or guard bit.
+ v.d * 0x1p-106 never normalizes by shifting up,
+ so round bit plus sticky bit should be already enough
+ for proper rounding. */
+ if (v.ieee.exponent == 106) {
+ /* v.ieee.mantissa1 & 2 is LSB bit of the result before rounding,
+ v.ieee.mantissa1 & 1 is the round bit and j is our sticky
+ bit. In round-to-nearest 001 rounds down like 00,
+ 011 rounds up, even though 01 rounds down (thus we need
+ to adjust), 101 rounds down like 10 and 111 rounds up
+ like 11. */
+ if ((v.ieee.mantissa1 & 3) == 1) {
+ v.d *= 0x1p-106;
+ if (v.ieee.negative)
+ *res = v.d - 0x1p-1074;
+ else
+ *res = v.d + 0x1p-1074;
+ } else
+ *res = v.d * 0x1p-106;
+ return;
+ }
+ v.ieee.mantissa1 |= j;
+ *res = v.d * 0x1p-106;
+ return;
+ }
+#endif
+}
+
+/*---------------------------------------------------------------*/
+/*--- end host_generic_maddf.c --*/
+/*---------------------------------------------------------------*/
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/priv/host_generic_maddf.h valgrind-3.8.0.new/VEX/priv/host_generic_maddf.h
--- valgrind-3.8.0.orig/VEX/priv/host_generic_maddf.h 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/VEX/priv/host_generic_maddf.h 2012-09-12 19:54:55.685333150 +0200
@@ -0,0 +1,52 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin host_generic_maddf.h ---*/
+/*---------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2012 OpenWorks GbR
+ info@open-works.net
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+/* Generic helper functions for doing FMA, i.e. compute x * y + z
+ as ternary operation.
+ These are purely back-end entities and cannot be seen/referenced
+ from IR. */
+
+#ifndef __VEX_HOST_GENERIC_MADDF_H
+#define __VEX_HOST_GENERIC_MADDF_H
+
+#include "libvex_basictypes.h"
+
+extern VEX_REGPARM(3)
+ void h_generic_calc_MAddF32 ( /*OUT*/Float*, Float*, Float*, Float* );
+
+extern VEX_REGPARM(3)
+ void h_generic_calc_MAddF64 ( /*OUT*/Double*, Double*, Double*,
+ Double* );
+
+#endif /* ndef __VEX_HOST_GENERIC_MADDF_H */
+
+/*---------------------------------------------------------------*/
+/*--- end host_generic_maddf.h --*/
+/*---------------------------------------------------------------*/
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/priv/host_generic_simd256.c valgrind-3.8.0.new/VEX/priv/host_generic_simd256.c
--- valgrind-3.8.0.orig/VEX/priv/host_generic_simd256.c 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/VEX/priv/host_generic_simd256.c 2012-09-12 19:53:20.976906747 +0200
@@ -0,0 +1,57 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin host_generic_simd256.c ---*/
+/*---------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2012 OpenWorks GbR
+ info@open-works.net
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+/* Generic helper functions for doing 256-bit SIMD arithmetic in cases
+ where the instruction selectors cannot generate code in-line.
+ These are purely back-end entities and cannot be seen/referenced
+ from IR. */
+
+#include "libvex_basictypes.h"
+#include "host_generic_simd256.h"
+
+
+void VEX_REGPARM(3)
+ h_generic_calc_Perm32x8 ( /*OUT*/V256* res,
+ V256* argL, V256* argR )
+{
+ res->w32[0] = argL->w32[ argR->w32[0] & 7 ];
+ res->w32[1] = argL->w32[ argR->w32[1] & 7 ];
+ res->w32[2] = argL->w32[ argR->w32[2] & 7 ];
+ res->w32[3] = argL->w32[ argR->w32[3] & 7 ];
+ res->w32[4] = argL->w32[ argR->w32[4] & 7 ];
+ res->w32[5] = argL->w32[ argR->w32[5] & 7 ];
+ res->w32[6] = argL->w32[ argR->w32[6] & 7 ];
+ res->w32[7] = argL->w32[ argR->w32[7] & 7 ];
+}
+
+
+/*---------------------------------------------------------------*/
+/*--- end host_generic_simd256.c ---*/
+/*---------------------------------------------------------------*/
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/priv/host_generic_simd256.h valgrind-3.8.0.new/VEX/priv/host_generic_simd256.h
--- valgrind-3.8.0.orig/VEX/priv/host_generic_simd256.h 1970-01-01 01:00:00.000000000 +0100
+++ valgrind-3.8.0.new/VEX/priv/host_generic_simd256.h 2012-09-12 19:53:20.956906446 +0200
@@ -0,0 +1,55 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin host_generic_simd256.h ---*/
+/*---------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2012 OpenWorks GbR
+ info@open-works.net
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+/* Generic helper functions for doing 256-bit SIMD arithmetic in cases
+ where the instruction selectors cannot generate code in-line.
+ These are purely back-end entities and cannot be seen/referenced
+ as clean helper functions from IR.
+
+ These will get called from generated code and therefore should be
+ well behaved -- no floating point or mmx insns, just straight
+ integer code.
+
+ Each function implements the correspondingly-named IR primop.
+*/
+
+#ifndef __VEX_HOST_GENERIC_SIMD256_H
+#define __VEX_HOST_GENERIC_SIMD256_H
+
+#include "libvex_basictypes.h"
+
+extern VEX_REGPARM(3)
+ void h_generic_calc_Perm32x8 ( /*OUT*/V256*, V256*, V256* );
+
+#endif /* ndef __VEX_HOST_GENERIC_SIMD256_H */
+
+/*---------------------------------------------------------------*/
+/*--- end host_generic_simd256.h ---*/
+/*---------------------------------------------------------------*/
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/priv/ir_defs.c valgrind-3.8.0.new/VEX/priv/ir_defs.c
--- valgrind-3.8.0.orig/VEX/priv/ir_defs.c 2012-09-12 17:37:34.511929841 +0200
+++ valgrind-3.8.0.new/VEX/priv/ir_defs.c 2012-09-12 19:55:08.894532087 +0200
@@ -1013,6 +1013,68 @@
case Iop_NotV256: vex_printf("NotV256"); return;
case Iop_CmpNEZ64x4: vex_printf("CmpNEZ64x4"); return;
case Iop_CmpNEZ32x8: vex_printf("CmpNEZ32x8"); return;
+ case Iop_CmpNEZ16x16: vex_printf("CmpNEZ16x16"); return;
+ case Iop_CmpNEZ8x32: vex_printf("CmpNEZ8x32"); return;
+
+ case Iop_Add8x32: vex_printf("Add8x32"); return;
+ case Iop_Add16x16: vex_printf("Add16x16"); return;
+ case Iop_Add32x8: vex_printf("Add32x8"); return;
+ case Iop_Add64x4: vex_printf("Add64x4"); return;
+ case Iop_Sub8x32: vex_printf("Sub8x32"); return;
+ case Iop_Sub16x16: vex_printf("Sub16x16"); return;
+ case Iop_Sub32x8: vex_printf("Sub32x8"); return;
+ case Iop_Sub64x4: vex_printf("Sub64x4"); return;
+ case Iop_QAdd8Ux32: vex_printf("QAdd8Ux32"); return;
+ case Iop_QAdd16Ux16: vex_printf("QAdd16Ux16"); return;
+ case Iop_QAdd8Sx32: vex_printf("QAdd8Sx32"); return;
+ case Iop_QAdd16Sx16: vex_printf("QAdd16Sx16"); return;
+ case Iop_QSub8Ux32: vex_printf("QSub8Ux32"); return;
+ case Iop_QSub16Ux16: vex_printf("QSub16Ux16"); return;
+ case Iop_QSub8Sx32: vex_printf("QSub8Sx32"); return;
+ case Iop_QSub16Sx16: vex_printf("QSub16Sx16"); return;
+
+ case Iop_Mul16x16: vex_printf("Mul16x16"); return;
+ case Iop_Mul32x8: vex_printf("Mul32x8"); return;
+ case Iop_MulHi16Ux16: vex_printf("MulHi16Ux16"); return;
+ case Iop_MulHi16Sx16: vex_printf("MulHi16Sx16"); return;
+
+ case Iop_Avg8Ux32: vex_printf("Avg8Ux32"); return;
+ case Iop_Avg16Ux16: vex_printf("Avg16Ux16"); return;
+
+ case Iop_Max8Sx32: vex_printf("Max8Sx32"); return;
+ case Iop_Max16Sx16: vex_printf("Max16Sx16"); return;
+ case Iop_Max32Sx8: vex_printf("Max32Sx8"); return;
+ case Iop_Max8Ux32: vex_printf("Max8Ux32"); return;
+ case Iop_Max16Ux16: vex_printf("Max16Ux16"); return;
+ case Iop_Max32Ux8: vex_printf("Max32Ux8"); return;
+
+ case Iop_Min8Sx32: vex_printf("Min8Sx32"); return;
+ case Iop_Min16Sx16: vex_printf("Min16Sx16"); return;
+ case Iop_Min32Sx8: vex_printf("Min32Sx8"); return;
+ case Iop_Min8Ux32: vex_printf("Min8Ux32"); return;
+ case Iop_Min16Ux16: vex_printf("Min16Ux16"); return;
+ case Iop_Min32Ux8: vex_printf("Min32Ux8"); return;
+
+ case Iop_CmpEQ8x32: vex_printf("CmpEQ8x32"); return;
+ case Iop_CmpEQ16x16: vex_printf("CmpEQ16x16"); return;
+ case Iop_CmpEQ32x8: vex_printf("CmpEQ32x8"); return;
+ case Iop_CmpEQ64x4: vex_printf("CmpEQ64x4"); return;
+ case Iop_CmpGT8Sx32: vex_printf("CmpGT8Sx32"); return;
+ case Iop_CmpGT16Sx16: vex_printf("CmpGT16Sx16"); return;
+ case Iop_CmpGT32Sx8: vex_printf("CmpGT32Sx8"); return;
+ case Iop_CmpGT64Sx4: vex_printf("CmpGT64Sx4"); return;
+
+ case Iop_ShlN16x16: vex_printf("ShlN16x16"); return;
+ case Iop_ShlN32x8: vex_printf("ShlN32x8"); return;
+ case Iop_ShlN64x4: vex_printf("ShlN64x4"); return;
+ case Iop_ShrN16x16: vex_printf("ShrN16x16"); return;
+ case Iop_ShrN32x8: vex_printf("ShrN32x8"); return;
+ case Iop_ShrN64x4: vex_printf("ShrN64x4"); return;
+ case Iop_SarN16x16: vex_printf("SarN16x16"); return;
+ case Iop_SarN32x8: vex_printf("SarN32x8"); return;
+
+ case Iop_Perm32x8: vex_printf("Perm32x8"); return;
+
default: vpanic("ppIROp(1)");
}
@@ -2828,6 +2890,26 @@
case Iop_XorV256:
case Iop_Max32Fx8: case Iop_Min32Fx8:
case Iop_Max64Fx4: case Iop_Min64Fx4:
+ case Iop_Add8x32: case Iop_Add16x16:
+ case Iop_Add32x8: case Iop_Add64x4:
+ case Iop_Sub8x32: case Iop_Sub16x16:
+ case Iop_Sub32x8: case Iop_Sub64x4:
+ case Iop_Mul16x16: case Iop_Mul32x8:
+ case Iop_MulHi16Ux16: case Iop_MulHi16Sx16:
+ case Iop_Avg8Ux32: case Iop_Avg16Ux16:
+ case Iop_Max8Sx32: case Iop_Max16Sx16: case Iop_Max32Sx8:
+ case Iop_Max8Ux32: case Iop_Max16Ux16: case Iop_Max32Ux8:
+ case Iop_Min8Sx32: case Iop_Min16Sx16: case Iop_Min32Sx8:
+ case Iop_Min8Ux32: case Iop_Min16Ux16: case Iop_Min32Ux8:
+ case Iop_CmpEQ8x32: case Iop_CmpEQ16x16:
+ case Iop_CmpEQ32x8: case Iop_CmpEQ64x4:
+ case Iop_CmpGT8Sx32: case Iop_CmpGT16Sx16:
+ case Iop_CmpGT32Sx8: case Iop_CmpGT64Sx4:
+ case Iop_QAdd8Ux32: case Iop_QAdd16Ux16:
+ case Iop_QAdd8Sx32: case Iop_QAdd16Sx16:
+ case Iop_QSub8Ux32: case Iop_QSub16Ux16:
+ case Iop_QSub8Sx32: case Iop_QSub16Sx16:
+ case Iop_Perm32x8:
BINARY(Ity_V256,Ity_V256, Ity_V256);
case Iop_V256toV128_1: case Iop_V256toV128_0:
@@ -2841,9 +2923,17 @@
case Iop_Sqrt32Fx8:
case Iop_Sqrt64Fx4:
case Iop_Recip32Fx8:
+ case Iop_CmpNEZ8x32: case Iop_CmpNEZ16x16:
case Iop_CmpNEZ64x4: case Iop_CmpNEZ32x8:
UNARY(Ity_V256, Ity_V256);
+ case Iop_ShlN16x16: case Iop_ShlN32x8:
+ case Iop_ShlN64x4:
+ case Iop_ShrN16x16: case Iop_ShrN32x8:
+ case Iop_ShrN64x4:
+ case Iop_SarN16x16: case Iop_SarN32x8:
+ BINARY(Ity_V256,Ity_I8, Ity_V256);
+
default:
ppIROp(op);
vpanic("typeOfPrimop");
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/priv/main_main.c valgrind-3.8.0.new/VEX/priv/main_main.c
--- valgrind-3.8.0.orig/VEX/priv/main_main.c 2012-09-12 17:37:34.509929813 +0200
+++ valgrind-3.8.0.new/VEX/priv/main_main.c 2012-09-12 19:54:35.356026975 +0200
@@ -1140,6 +1140,14 @@
case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16
| VEX_HWCAPS_AMD64_LZCNT | VEX_HWCAPS_AMD64_AVX:
return "amd64-sse3-cx16-lzcnt-avx";
+ case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16
+ | VEX_HWCAPS_AMD64_LZCNT | VEX_HWCAPS_AMD64_AVX
+ | VEX_HWCAPS_AMD64_BMI:
+ return "amd64-sse3-cx16-lzcnt-avx-bmi";
+ case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16
+ | VEX_HWCAPS_AMD64_LZCNT | VEX_HWCAPS_AMD64_AVX
+ | VEX_HWCAPS_AMD64_BMI | VEX_HWCAPS_AMD64_AVX2:
+ return "amd64-sse3-cx16-lzcnt-avx2-bmi";
default:
return NULL;
}
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/pub/libvex_basictypes.h valgrind-3.8.0.new/VEX/pub/libvex_basictypes.h
--- valgrind-3.8.0.orig/VEX/pub/libvex_basictypes.h 2012-09-12 17:37:34.507929780 +0200
+++ valgrind-3.8.0.new/VEX/pub/libvex_basictypes.h 2012-09-12 19:53:20.865905075 +0200
@@ -75,6 +75,16 @@
}
V128;
+/* A union for doing 256-bit vector primitives conveniently. */
+typedef
+ union {
+ UChar w8[32];
+ UShort w16[16];
+ UInt w32[8];
+ ULong w64[4];
+ }
+ V256;
+
/* Floating point. */
typedef float Float; /* IEEE754 single-precision (32-bit) value */
typedef double Double; /* IEEE754 double-precision (64-bit) value */
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/pub/libvex.h valgrind-3.8.0.new/VEX/pub/libvex.h
--- valgrind-3.8.0.orig/VEX/pub/libvex.h 2012-09-12 17:37:34.507929781 +0200
+++ valgrind-3.8.0.new/VEX/pub/libvex.h 2012-09-12 19:54:35.345026811 +0200
@@ -82,6 +82,8 @@
#define VEX_HWCAPS_AMD64_CX16 (1<<6) /* cmpxchg16b support */
#define VEX_HWCAPS_AMD64_LZCNT (1<<7) /* SSE4a LZCNT insn */
#define VEX_HWCAPS_AMD64_AVX (1<<8) /* AVX instructions */
+#define VEX_HWCAPS_AMD64_BMI (1<<9) /* BMI1 instructions */
+#define VEX_HWCAPS_AMD64_AVX2 (1<<10) /* AVX2 instructions */
/* ppc32: baseline capability is integer only */
#define VEX_HWCAPS_PPC32_F (1<<8) /* basic (non-optional) FP */
diff -ruN '--exclude=*.orig' '--exclude=autom4te.cache' valgrind-3.8.0.orig/VEX/pub/libvex_ir.h valgrind-3.8.0.new/VEX/pub/libvex_ir.h
--- valgrind-3.8.0.orig/VEX/pub/libvex_ir.h 2012-09-12 17:37:34.507929781 +0200
+++ valgrind-3.8.0.new/VEX/pub/libvex_ir.h 2012-09-12 19:55:08.861531590 +0200
@@ -1450,7 +1450,34 @@
Iop_NotV256,
/* MISC (vector integer cmp != 0) */
- Iop_CmpNEZ32x8, Iop_CmpNEZ64x4,
+ Iop_CmpNEZ8x32, Iop_CmpNEZ16x16, Iop_CmpNEZ32x8, Iop_CmpNEZ64x4,
+
+ Iop_Add8x32, Iop_Add16x16, Iop_Add32x8, Iop_Add64x4,
+ Iop_Sub8x32, Iop_Sub16x16, Iop_Sub32x8, Iop_Sub64x4,
+
+ Iop_CmpEQ8x32, Iop_CmpEQ16x16, Iop_CmpEQ32x8, Iop_CmpEQ64x4,
+ Iop_CmpGT8Sx32, Iop_CmpGT16Sx16, Iop_CmpGT32Sx8, Iop_CmpGT64Sx4,
+
+ Iop_ShlN16x16, Iop_ShlN32x8, Iop_ShlN64x4,
+ Iop_ShrN16x16, Iop_ShrN32x8, Iop_ShrN64x4,
+ Iop_SarN16x16, Iop_SarN32x8,
+
+ Iop_Max8Sx32, Iop_Max16Sx16, Iop_Max32Sx8,
+ Iop_Max8Ux32, Iop_Max16Ux16, Iop_Max32Ux8,
+ Iop_Min8Sx32, Iop_Min16Sx16, Iop_Min32Sx8,
+ Iop_Min8Ux32, Iop_Min16Ux16, Iop_Min32Ux8,
+
+ Iop_Mul16x16, Iop_Mul32x8,
+ Iop_MulHi16Ux16, Iop_MulHi16Sx16,
+
+ Iop_QAdd8Ux32, Iop_QAdd16Ux16,
+ Iop_QAdd8Sx32, Iop_QAdd16Sx16,
+ Iop_QSub8Ux32, Iop_QSub16Ux16,
+ Iop_QSub8Sx32, Iop_QSub16Sx16,
+
+ Iop_Avg8Ux32, Iop_Avg16Ux16,
+
+ Iop_Perm32x8,
/* ------------------ 256-bit SIMD FP. ------------------ */
Iop_Add64Fx4,
distrib
>
Mageia
>
3
>
i586
>
media
>
core-release-src
>
by-pkgid
>
942f36be6b50523b0497d9f09dbcf35b
>
files
>
3
