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kernel-2.6.18-238.el5.src.rpm

From: Bhavna Sarathy <bnagendr@redhat.com>
Date: Thu, 5 Aug 2010 18:04:19 -0400
Subject: [edac] amd64_edac: simplify ECC override handling
Message-id: <20100805181001.6566.87381.sendpatchset@localhost.localdomain>
Patchwork-id: 27421
O-Subject: [RHEL5.6 PATCH 7/10] amd64_edac - Simplify ECC override handling
Bugzilla: 568576
RH-Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com>

>From 68de92fe602bbb0136734b3e67e1e2551c7dd2e7 Mon Sep 17 00:00:00 2001
From: Borislav Petkov <borislav.petkov@amd.com>
Date: Tue, 3 Aug 2010 00:25:39 +0200
Subject: [PATCH] amd64_edac: Simplify ECC override handling

(Upstream commit d95cf4de6a1c9c1025ac375bc6d2da6af18fdf35)

No need for clearing ecc_enable_override and checking it in two places.
Instead, simply check it during probing and act accordingly. Also,
rename the flag bitfields according to the functionality they actually
represent. What is more, make sure original BIOS ECC settings are
restored when the module is unloaded.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index ebe20ea..5b2825e 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2382,14 +2382,14 @@ static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on)
 
                if (on) {
                        if (msrs[idx].l & K8_MSR_MCGCTL_NBE)
-                               pvt->flags.ecc_report = 1;
+                               pvt->flags.nb_mce_enable = 1;
 
                        msrs[idx].l |= K8_MSR_MCGCTL_NBE;
                } else {
                        /*
-                        * Turn off ECC reporting only when it was off before
+                        * Turn off NB MCE reporting only if it was off before
                         */
-                       if (!pvt->flags.ecc_report)
+                       if (!pvt->flags.nb_mce_enable)
                                msrs[idx].l &= ~K8_MSR_MCGCTL_NBE;
                }
                idx++;
@@ -2401,23 +2401,12 @@ static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on)
        return 0;
 }
 
-/*
- * Only if 'ecc_enable_override' is set AND BIOS had ECC disabled, do "we"
- * enable it.
- */
 static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
 {
        struct amd64_pvt *pvt = mci->pvt_info;
        int err = 0;
        u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
 
-       if (!ecc_enable_override)
-               return;
-
-       amd64_printk(KERN_WARNING,
-               "'ecc_enable_override' parameter is active, "
-               "Enabling AMD ECC hardware now: CAUTION\n");
-
        err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCTL, &value);
        if (err)
                debugf0("Reading K8_NBCTL failed\n");
@@ -2446,6 +2435,8 @@ static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
                        "This node reports that DRAM ECC is "
                        "currently Disabled; ENABLING now\n");
 
+		pvt->flags.nb_ecc_prev = 0;
+
                /* Attempt to turn on DRAM ECC Enable */
                value |= K8_NBCFG_ECC_ENABLE;
                pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value);
@@ -2462,7 +2453,10 @@ static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
                        amd64_printk(KERN_DEBUG,
                                "Hardware accepted DRAM ECC Enable\n");
                }
+	} else {
+		pvt->flags.nb_ecc_prev = 1;
        }
+
        debugf0("NBCFG(2)= 0x%x  CHIPKILL= %s ECC_ENABLE= %s\n", value,
                (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
                (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
@@ -2484,12 +2478,21 @@ static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
        value &= ~mask;
        value |= pvt->old_nbctl;
 
-       /* restore the NB Enable MCGCTL bit */
        pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value);
 
+	/* restore previous BIOS DRAM ECC "off" setting which we force-enabled */
+	if (!pvt->flags.nb_ecc_prev) {
+		err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value);
+		if (err)
+			debugf0("Reading K8_NBCFG failed\n");
+
+		value &= ~K8_NBCFG_ECC_ENABLE;
+		pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value);
+	}
+
+	/* restore the NB Enable MCGCTL bit */
        if (amd64_toggle_ecc_err_reporting(pvt, OFF))
-               amd64_printk(KERN_WARNING, "Error restoring ECC reporting over "
-                                          "MCGCTL!\n");
+		amd64_printk(KERN_WARNING, "Error restoring NB MCGCTL settings!\n");
 }
 
 /*
@@ -2533,8 +2536,9 @@ static int amd64_check_ecc_enabled(struct amd64_pvt *pvt)
                if (!ecc_enable_override) {
 			amd64_printk(KERN_NOTICE, "%s", ecc_msg);
                        return -ENODEV;
+		} else {
+			amd64_printk(KERN_WARNING, "Forcing ECC checking on!\n");
 	       }
-	       ecc_enable_override = 0;
        }
        return 0;
 }
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 3b94ab7..3f90154 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -494,8 +494,9 @@ struct amd64_pvt {
 
        /* misc settings */
        struct flags {
-               unsigned long cf8_extcfg:1;
-               unsigned long ecc_report:1;
+		unsigned long cf8_extcfg:1;
+		unsigned long nb_mce_enable:1;
+		unsigned long nb_ecc_prev:1;
        } flags;
 };