From: John Feeney <jfeeney@redhat.com> Date: Thu, 27 Aug 2009 17:02:05 -0400 Subject: [net] tg3: refrain from touching MPS Message-id: 4A96F44D.7060106@redhat.com O-Subject: [RHEL5.5 PATCH] Refrain from touching MPS in tg3 Bugzilla: 516123 RH-Acked-by: David Miller <davem@redhat.com> RH-Acked-by: Neil Horman <nhorman@redhat.com> RH-Acked-by: Dean Nelson <dnelson@redhat.com> bz516123 https://bugzilla.redhat.com/bugzilla/show_bug.cgi?id=516123 Broadcom 5761 does not work Description of problem: The network interface associated with BCM5761 does not get an ip address. Solution: Broadcom provided the patch. From the bz: "Reprogramming the MPS value in the device control register is an error. This value is a result of PCIe link negotiation and should not be modified. This patch changes the code to only modify those bits mentioned in the comment" ("no snoop" and "relax ordering"). Upstream status: http://marc.info/?l=linux-netdev&m=125123258431742&w=2 Brew: Successfully built in Brew for all architectures (task_1945385) Testing: I tested the patch on hp-z400-02.rhts.bos.redhat.com (BCM5761) and Broadcom tested on 5761 system (Dell T7500). Additionally, I tested a T5500 w/BCM5761, hp-dl320g6-01 w/BCM5715, and dell-pesc440-01 w/BCM5754. All got ip addresses. Acks would be appreciated. Thanks. diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index f2e71e5..3540a1d 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -5752,6 +5752,8 @@ static int tg3_chip_reset(struct tg3 *tp) udelay(120); if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) { + u16 val16; + if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { int i; u32 cfg_val; @@ -5765,12 +5767,22 @@ static int tg3_chip_reset(struct tg3 *tp) cfg_val | (1 << 15)); } - /* Set PCIE max payload size to 128 bytes and - * clear the "no snoop" and "relaxed ordering" bits. - */ + /* Clear the "no snoop" and "relaxed ordering" bits. */ + pci_read_config_word(tp->pdev, + tp->pcie_cap + PCI_EXP_DEVCTL, + &val16); + val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | + PCI_EXP_DEVCTL_NOSNOOP_EN); + /* + * Older PCIe devices only support the 128 byte + * MPS setting. Enforce the restriction. + */ + if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || + (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)) + val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; pci_write_config_word(tp->pdev, tp->pcie_cap + PCI_EXP_DEVCTL, - 0); + val16); pcie_set_readrq(tp->pdev, 4096);