From: Andy Gospodarek <gospo@redhat.com>
Subject: [RHEL5.1 PATCH] netxen: initial support for NetXen 10GbE NIC
Date: Wed, 6 Jun 2007 15:17:42 -0400
Bugzilla: 231724
Message-Id: <20070606191741.GF5927@gospo.rdu.redhat.com>
Changelog: [net] netxen: initial support for NetXen 10GbE NIC
It should be the latest netxen upstream driver including one of the
patches submitted on Friday (but not the ones Jeff et al didn't like).
This also depends on Jeff's recent patch to make skbuff.h changes posted
earlier today.
Jarod and Konrad have been testing this pretty heavily in Westford with
good results.
This will resolve BZ 231724.
CONFIG_NETXEN_NIC=m
---
MAINTAINERS | 7
drivers/net/Kconfig | 6
drivers/net/Makefile | 1
drivers/net/netxen/Makefile | 36
drivers/net/netxen/netxen_nic.h | 1158 +++++++++++++++++++++++
drivers/net/netxen/netxen_nic_ethtool.c | 758 +++++++++++++++
drivers/net/netxen/netxen_nic_hdr.h | 690 +++++++++++++
drivers/net/netxen/netxen_nic_hw.c | 1186 +++++++++++++++++++++++
drivers/net/netxen/netxen_nic_hw.h | 510 ++++++++++
drivers/net/netxen/netxen_nic_init.c | 1541 +++++++++++++++++++++++++++++++
drivers/net/netxen/netxen_nic_isr.c | 200 ++++
drivers/net/netxen/netxen_nic_main.c | 1272 +++++++++++++++++++++++++
drivers/net/netxen/netxen_nic_niu.c | 916 ++++++++++++++++++
drivers/net/netxen/netxen_nic_phan_reg.h | 172 +++
14 files changed, 8453 insertions(+)
--- linux-2.6.18.x86_64/MAINTAINERS.rhel5
+++ linux-2.6.18.x86_64/MAINTAINERS
@@ -2091,6 +2091,13 @@ L: netdev@vger.kernel.org
T: git kernel.org:/pub/scm/linux/kernel/git/linville/wireless-2.6.git
S: Maintained
+NETXEN (1/10) GbE SUPPORT
+P: Amit S. Kale
+M: amitkale@netxen.com
+L: netdev@vger.kernel.org
+W: http://www.netxen.com
+S: Supported
+
IPVS
P: Wensong Zhang
M: wensong@linux-vs.org
--- linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_hw.h.rhel5
+++ linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_hw.h
@@ -0,0 +1,510 @@
+/*
+ * Copyright (C) 2003 - 2006 NetXen, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
+ * MA 02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.
+ *
+ * Contact Information:
+ * info@netxen.com
+ * NetXen,
+ * 3965 Freedom Circle, Fourth floor,
+ * Santa Clara, CA 95054
+ *
+ *
+ * Structures, enums, and macros for the MAC
+ *
+ */
+
+#ifndef __NETXEN_NIC_HW_H_
+#define __NETXEN_NIC_HW_H_
+
+#include "netxen_nic_hdr.h"
+
+/* Hardware memory size of 128 meg */
+#define NETXEN_MEMADDR_MAX (128 * 1024 * 1024)
+
+#ifndef readq
+static inline u64 readq(void __iomem * addr)
+{
+ return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
+}
+#endif
+
+#ifndef writeq
+static inline void writeq(u64 val, void __iomem * addr)
+{
+ writel(((u32) (val)), (addr));
+ writel(((u32) (val >> 32)), (addr + 4));
+}
+#endif
+
+static inline void netxen_nic_hw_block_write64(u64 __iomem * data_ptr,
+ u64 __iomem * addr,
+ int num_words)
+{
+ int num;
+ for (num = 0; num < num_words; num++) {
+ writeq(readq((void __iomem *)data_ptr), addr);
+ addr++;
+ data_ptr++;
+ }
+}
+
+static inline void netxen_nic_hw_block_read64(u64 __iomem * data_ptr,
+ u64 __iomem * addr, int num_words)
+{
+ int num;
+ for (num = 0; num < num_words; num++) {
+ writeq(readq((void __iomem *)addr), data_ptr);
+ addr++;
+ data_ptr++;
+ }
+
+}
+
+struct netxen_adapter;
+
+#define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20)
+
+#define NETXEN_NIC_LOCKED_READ_REG(X, Y) \
+ addr = pci_base_offset(adapter, X); \
+ *(u32 *)Y = readl((void __iomem*) addr);
+
+struct netxen_port;
+void netxen_nic_set_link_parameters(struct netxen_adapter *adapter);
+void netxen_nic_flash_print(struct netxen_adapter *adapter);
+int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off,
+ void *data, int len);
+void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
+ unsigned long off, int data);
+int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off,
+ void *data, int len);
+
+typedef u8 netxen_ethernet_macaddr_t[6];
+
+/* Nibble or Byte mode for phy interface (GbE mode only) */
+typedef enum {
+ NETXEN_NIU_10_100_MB = 0,
+ NETXEN_NIU_1000_MB
+} netxen_niu_gbe_ifmode_t;
+
+#define _netxen_crb_get_bit(var, bit) ((var >> bit) & 0x1)
+
+/*
+ * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
+ *
+ * Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
+ * Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
+ * Bit 2 : enable_rx => 1:enable frame recv, 0:disable
+ * Bit 3 : rx_synced => R/O: recv enable synched to recv stream
+ * Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
+ * Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
+ * Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
+ * Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
+ * Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
+ * Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
+ * Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
+ * Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
+ */
+
+#define netxen_gb_enable_tx(config_word) \
+ ((config_word) |= 1 << 0)
+#define netxen_gb_enable_rx(config_word) \
+ ((config_word) |= 1 << 2)
+#define netxen_gb_tx_flowctl(config_word) \
+ ((config_word) |= 1 << 4)
+#define netxen_gb_rx_flowctl(config_word) \
+ ((config_word) |= 1 << 5)
+#define netxen_gb_tx_reset_pb(config_word) \
+ ((config_word) |= 1 << 16)
+#define netxen_gb_rx_reset_pb(config_word) \
+ ((config_word) |= 1 << 17)
+#define netxen_gb_tx_reset_mac(config_word) \
+ ((config_word) |= 1 << 18)
+#define netxen_gb_rx_reset_mac(config_word) \
+ ((config_word) |= 1 << 19)
+#define netxen_gb_soft_reset(config_word) \
+ ((config_word) |= 1 << 31)
+
+#define netxen_gb_unset_tx_flowctl(config_word) \
+ ((config_word) &= ~(1 << 4))
+#define netxen_gb_unset_rx_flowctl(config_word) \
+ ((config_word) &= ~(1 << 5))
+
+#define netxen_gb_get_tx_synced(config_word) \
+ _netxen_crb_get_bit((config_word), 1)
+#define netxen_gb_get_rx_synced(config_word) \
+ _netxen_crb_get_bit((config_word), 3)
+#define netxen_gb_get_tx_flowctl(config_word) \
+ _netxen_crb_get_bit((config_word), 4)
+#define netxen_gb_get_rx_flowctl(config_word) \
+ _netxen_crb_get_bit((config_word), 5)
+#define netxen_gb_get_soft_reset(config_word) \
+ _netxen_crb_get_bit((config_word), 31)
+
+/*
+ * NIU GB MAC Config Register 1 (applies to GB0, GB1, GB2, GB3)
+ *
+ * Bit 0 : duplex => 1:full duplex mode, 0:half duplex
+ * Bit 1 : crc_enable => 1:append CRC to xmit frames, 0:dont append
+ * Bit 2 : padshort => 1:pad short frames and add CRC, 0:dont pad
+ * Bit 4 : checklength => 1:check framelen with actual,0:dont check
+ * Bit 5 : hugeframes => 1:allow oversize xmit frames, 0:dont allow
+ * Bits 8-9 : intfmode => 01:nibble (10/100), 10:byte (1000)
+ * Bits 12-15 : preamblelen => preamble field length in bytes, default 7
+ */
+
+#define netxen_gb_set_duplex(config_word) \
+ ((config_word) |= 1 << 0)
+#define netxen_gb_set_crc_enable(config_word) \
+ ((config_word) |= 1 << 1)
+#define netxen_gb_set_padshort(config_word) \
+ ((config_word) |= 1 << 2)
+#define netxen_gb_set_checklength(config_word) \
+ ((config_word) |= 1 << 4)
+#define netxen_gb_set_hugeframes(config_word) \
+ ((config_word) |= 1 << 5)
+#define netxen_gb_set_preamblelen(config_word, val) \
+ ((config_word) &= ~(0xf<<12), (config_word) |= (val & 0xf)<< 12)
+#define netxen_gb_set_intfmode(config_word, val) \
+ ((config_word) &= ~(0xf<<8), (config_word) |= (val & 0x3) << 8)
+
+#define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16)
+
+#define netxen_gb_set_mii_mgmt_clockselect(config_word, val) \
+ ((config_word) &= ~(0x7<<0), (config_word) |= (val & 0x7) << 0)
+#define netxen_gb_mii_mgmt_reset(config_word) \
+ ((config_word) |= 1 << 31)
+
+/*
+ * NIU XG Pause Ctl Register
+ *
+ * Bit 0 : xg0_mask => 1:disable tx pause frames
+ * Bit 1 : xg0_request => 1:request single pause frame
+ * Bit 2 : xg0_on_off => 1:request is pause on, 0:off
+ * Bit 3 : xg1_mask => 1:disable tx pause frames
+ * Bit 4 : xg1_request => 1:request single pause frame
+ * Bit 5 : xg1_on_off => 1:request is pause on, 0:off
+ */
+
+#define netxen_xg_set_xg0_mask(config_word) \
+ ((config_word) |= 1 << 0)
+#define netxen_xg_set_xg1_mask(config_word) \
+ ((config_word) |= 1 << 3)
+
+#define netxen_xg_get_xg0_mask(config_word) \
+ _netxen_crb_get_bit((config_word), 0)
+#define netxen_xg_get_xg1_mask(config_word) \
+ _netxen_crb_get_bit((config_word), 3)
+
+#define netxen_xg_unset_xg0_mask(config_word) \
+ ((config_word) &= ~(1 << 0))
+#define netxen_xg_unset_xg1_mask(config_word) \
+ ((config_word) &= ~(1 << 3))
+
+/*
+ * NIU GBe Pause Ctl Register
+ *
+ * Bit 0 : gb0_mask => 1:disable tx pause frames
+ * Bit 1 : gb0_pause_req => 1:send pause on, 0:send pause off
+ * Bit 2 : gb1_mask => 1:disable tx pause frames
+ * Bit 3 : gb1_pause_req:1 => 1:send pause on, 0:send pause off
+ * Bit 4 : gb2_mask => 1:disable tx pause frames
+ * Bit 5 : gb2_pause_req => 1:send pause on, 0:send pause off
+ * Bit 6 : gb3_mask => 1:disable tx pause frames
+ * Bit 7 : gb3_pause_req => 1:send pause on, 0:send pause off
+ */
+#define netxen_gb_set_gb0_mask(config_word) \
+ ((config_word) |= 1 << 0)
+#define netxen_gb_set_gb1_mask(config_word) \
+ ((config_word) |= 1 << 2)
+#define netxen_gb_set_gb2_mask(config_word) \
+ ((config_word) |= 1 << 4)
+#define netxen_gb_set_gb3_mask(config_word) \
+ ((config_word) |= 1 << 6)
+
+#define netxen_gb_get_gb0_mask(config_word) \
+ _netxen_crb_get_bit((config_word), 0)
+#define netxen_gb_get_gb1_mask(config_word) \
+ _netxen_crb_get_bit((config_word), 2)
+#define netxen_gb_get_gb2_mask(config_word) \
+ _netxen_crb_get_bit((config_word), 4)
+#define netxen_gb_get_gb3_mask(config_word) \
+ _netxen_crb_get_bit((config_word), 6)
+
+#define netxen_gb_unset_gb0_mask(config_word) \
+ ((config_word) &= ~(1 << 0))
+#define netxen_gb_unset_gb1_mask(config_word) \
+ ((config_word) &= ~(1 << 2))
+#define netxen_gb_unset_gb2_mask(config_word) \
+ ((config_word) &= ~(1 << 4))
+#define netxen_gb_unset_gb3_mask(config_word) \
+ ((config_word) &= ~(1 << 6))
+
+/*
+ * NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
+ * Bit 0 : read_cycle => 1:perform single read cycle, 0:no-op
+ * Bit 1 : scan_cycle => 1:perform continuous read cycles, 0:no-op
+ */
+#define netxen_gb_mii_mgmt_set_read_cycle(config_word) \
+ ((config_word) |= 1 << 0)
+#define netxen_gb_mii_mgmt_reg_addr(config_word, val) \
+ ((config_word) &= ~(0x1f<<0), (config_word) |= (val & 0x1f)<< 0)
+#define netxen_gb_mii_mgmt_phy_addr(config_word, val) \
+ ((config_word) &= ~(0x1f<<8), (config_word) |= (val & 0x1f)<< 8)
+
+/*
+ * NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
+ * Read-only register.
+ * Bit 0 : busy => 1:performing an MII mgmt cycle, 0:idle
+ * Bit 1 : scanning => 1:scan operation in progress, 0:idle
+ * Bit 2 : notvalid => :mgmt result data not yet valid, 0:idle
+ */
+
+#define netxen_get_gb_mii_mgmt_busy(config_word) \
+ _netxen_crb_get_bit(config_word, 0)
+#define netxen_get_gb_mii_mgmt_scanning(config_word) \
+ _netxen_crb_get_bit(config_word, 1)
+#define netxen_get_gb_mii_mgmt_notvalid(config_word) \
+ _netxen_crb_get_bit(config_word, 2)
+
+/*
+ * PHY-Specific MII control/status registers.
+ */
+typedef enum {
+ NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL = 0,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS = 1,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 = 2,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 = 3,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG = 4,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART = 5,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE = 6,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT = 7,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE = 8,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL = 9,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS = 10,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS = 15,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL = 16,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS = 17,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE = 18,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS = 19,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE = 20,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT = 21,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL = 24,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE = 25,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET = 26,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE = 27
+} netxen_niu_phy_register_t;
+
+/*
+ * PHY-Specific Status Register (reg 17).
+ *
+ * Bit 0 : jabber => 1:jabber detected, 0:not
+ * Bit 1 : polarity => 1:polarity reversed, 0:normal
+ * Bit 2 : recvpause => 1:receive pause enabled, 0:disabled
+ * Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled
+ * Bit 4 : energydetect => 1:sleep, 0:active
+ * Bit 5 : downshift => 1:downshift, 0:no downshift
+ * Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
+ * Bits 7-9 : cablelen => not valid in 10Mb/s mode
+ * 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
+ * Bit 10 : link => 1:link up, 0:link down
+ * Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet
+ * Bit 12 : pagercvd => 1:page received, 0:page not received
+ * Bit 13 : duplex => 1:full duplex, 0:half duplex
+ * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
+ */
+
+#define netxen_get_phy_cablelen(config_word) (((config_word) >> 7) & 0x07)
+#define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
+
+#define netxen_set_phy_speed(config_word, val) \
+ ((config_word) &= ~(0x3<<14), (config_word) |= (val & 0x3)<< 14)
+#define netxen_set_phy_duplex(config_word) \
+ ((config_word) |= 1 << 13)
+#define netxen_clear_phy_duplex(config_word) \
+ ((config_word) &= ~(1 << 13))
+
+#define netxen_get_phy_jabber(config_word) \
+ _netxen_crb_get_bit(config_word, 0)
+#define netxen_get_phy_polarity(config_word) \
+ _netxen_crb_get_bit(config_word, 1)
+#define netxen_get_phy_recvpause(config_word) \
+ _netxen_crb_get_bit(config_word, 2)
+#define netxen_get_phy_xmitpause(config_word) \
+ _netxen_crb_get_bit(config_word, 3)
+#define netxen_get_phy_energydetect(config_word) \
+ _netxen_crb_get_bit(config_word, 4)
+#define netxen_get_phy_downshift(config_word) \
+ _netxen_crb_get_bit(config_word, 5)
+#define netxen_get_phy_crossover(config_word) \
+ _netxen_crb_get_bit(config_word, 6)
+#define netxen_get_phy_link(config_word) \
+ _netxen_crb_get_bit(config_word, 10)
+#define netxen_get_phy_resolved(config_word) \
+ _netxen_crb_get_bit(config_word, 11)
+#define netxen_get_phy_pagercvd(config_word) \
+ _netxen_crb_get_bit(config_word, 12)
+#define netxen_get_phy_duplex(config_word) \
+ _netxen_crb_get_bit(config_word, 13)
+
+/*
+ * Interrupt Register definition
+ * This definition applies to registers 18 and 19 (int enable and int status).
+ * Bit 0 : jabber
+ * Bit 1 : polarity_changed
+ * Bit 4 : energy_detect
+ * Bit 5 : downshift
+ * Bit 6 : mdi_xover_changed
+ * Bit 7 : fifo_over_underflow
+ * Bit 8 : false_carrier
+ * Bit 9 : symbol_error
+ * Bit 10: link_status_changed
+ * Bit 11: autoneg_completed
+ * Bit 12: page_received
+ * Bit 13: duplex_changed
+ * Bit 14: speed_changed
+ * Bit 15: autoneg_error
+ */
+
+#define netxen_get_phy_int_jabber(config_word) \
+ _netxen_crb_get_bit(config_word, 0)
+#define netxen_get_phy_int_polarity_changed(config_word) \
+ _netxen_crb_get_bit(config_word, 1)
+#define netxen_get_phy_int_energy_detect(config_word) \
+ _netxen_crb_get_bit(config_word, 4)
+#define netxen_get_phy_int_downshift(config_word) \
+ _netxen_crb_get_bit(config_word, 5)
+#define netxen_get_phy_int_mdi_xover_changed(config_word) \
+ _netxen_crb_get_bit(config_word, 6)
+#define netxen_get_phy_int_fifo_over_underflow(config_word) \
+ _netxen_crb_get_bit(config_word, 7)
+#define netxen_get_phy_int_false_carrier(config_word) \
+ _netxen_crb_get_bit(config_word, 8)
+#define netxen_get_phy_int_symbol_error(config_word) \
+ _netxen_crb_get_bit(config_word, 9)
+#define netxen_get_phy_int_link_status_changed(config_word) \
+ _netxen_crb_get_bit(config_word, 10)
+#define netxen_get_phy_int_autoneg_completed(config_word) \
+ _netxen_crb_get_bit(config_word, 11)
+#define netxen_get_phy_int_page_received(config_word) \
+ _netxen_crb_get_bit(config_word, 12)
+#define netxen_get_phy_int_duplex_changed(config_word) \
+ _netxen_crb_get_bit(config_word, 13)
+#define netxen_get_phy_int_speed_changed(config_word) \
+ _netxen_crb_get_bit(config_word, 14)
+#define netxen_get_phy_int_autoneg_error(config_word) \
+ _netxen_crb_get_bit(config_word, 15)
+
+#define netxen_set_phy_int_link_status_changed(config_word) \
+ ((config_word) |= 1 << 10)
+#define netxen_set_phy_int_autoneg_completed(config_word) \
+ ((config_word) |= 1 << 11)
+#define netxen_set_phy_int_speed_changed(config_word) \
+ ((config_word) |= 1 << 14)
+
+/*
+ * NIU Mode Register.
+ * Bit 0 : enable FibreChannel
+ * Bit 1 : enable 10/100/1000 Ethernet
+ * Bit 2 : enable 10Gb Ethernet
+ */
+
+#define netxen_get_niu_enable_ge(config_word) \
+ _netxen_crb_get_bit(config_word, 1)
+
+/* Promiscous mode options (GbE mode only) */
+typedef enum {
+ NETXEN_NIU_PROMISC_MODE = 0,
+ NETXEN_NIU_NON_PROMISC_MODE
+} netxen_niu_prom_mode_t;
+
+/*
+ * NIU GB Drop CRC Register
+ *
+ * Bit 0 : drop_gb0 => 1:drop pkts with bad CRCs, 0:pass them on
+ * Bit 1 : drop_gb1 => 1:drop pkts with bad CRCs, 0:pass them on
+ * Bit 2 : drop_gb2 => 1:drop pkts with bad CRCs, 0:pass them on
+ * Bit 3 : drop_gb3 => 1:drop pkts with bad CRCs, 0:pass them on
+ */
+
+#define netxen_set_gb_drop_gb0(config_word) \
+ ((config_word) |= 1 << 0)
+#define netxen_set_gb_drop_gb1(config_word) \
+ ((config_word) |= 1 << 1)
+#define netxen_set_gb_drop_gb2(config_word) \
+ ((config_word) |= 1 << 2)
+#define netxen_set_gb_drop_gb3(config_word) \
+ ((config_word) |= 1 << 3)
+
+#define netxen_clear_gb_drop_gb0(config_word) \
+ ((config_word) &= ~(1 << 0))
+#define netxen_clear_gb_drop_gb1(config_word) \
+ ((config_word) &= ~(1 << 1))
+#define netxen_clear_gb_drop_gb2(config_word) \
+ ((config_word) &= ~(1 << 2))
+#define netxen_clear_gb_drop_gb3(config_word) \
+ ((config_word) &= ~(1 << 3))
+
+/*
+ * NIU XG MAC Config Register
+ *
+ * Bit 0 : tx_enable => 1:enable frame xmit, 0:disable
+ * Bit 2 : rx_enable => 1:enable frame recv, 0:disable
+ * Bit 4 : soft_reset => 1:reset the MAC , 0:no-op
+ * Bit 27: xaui_framer_reset
+ * Bit 28: xaui_rx_reset
+ * Bit 29: xaui_tx_reset
+ * Bit 30: xg_ingress_afifo_reset
+ * Bit 31: xg_egress_afifo_reset
+ */
+
+#define netxen_xg_soft_reset(config_word) \
+ ((config_word) |= 1 << 4)
+
+
+/* Set promiscuous mode for a GbE interface */
+int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
+ netxen_niu_prom_mode_t mode);
+int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
+ netxen_niu_prom_mode_t mode);
+
+/* get/set the MAC address for a given MAC */
+int netxen_niu_macaddr_get(struct netxen_adapter *adapter,
+ netxen_ethernet_macaddr_t * addr);
+int netxen_niu_macaddr_set(struct netxen_adapter *adapter,
+ netxen_ethernet_macaddr_t addr);
+
+/* XG versons */
+int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter,
+ netxen_ethernet_macaddr_t * addr);
+int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter,
+ netxen_ethernet_macaddr_t addr);
+
+/* Generic enable for GbE ports. Will detect the speed of the link. */
+int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port);
+
+int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port);
+
+/* Disable a GbE interface */
+int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter);
+
+int netxen_niu_disable_xg_port(struct netxen_adapter *adapter);
+
+#endif /* __NETXEN_NIC_HW_H_ */
--- linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_main.c.rhel5
+++ linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_main.c
@@ -0,0 +1,1272 @@
+/*
+ * Copyright (C) 2003 - 2006 NetXen, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
+ * MA 02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.
+ *
+ * Contact Information:
+ * info@netxen.com
+ * NetXen,
+ * 3965 Freedom Circle, Fourth floor,
+ * Santa Clara, CA 95054
+ *
+ *
+ * Main source file for NetXen NIC Driver on Linux
+ *
+ */
+
+#include <linux/vmalloc.h>
+#include <linux/highmem.h>
+#include "netxen_nic_hw.h"
+
+#include "netxen_nic.h"
+#include "netxen_nic_phan_reg.h"
+
+#include <linux/dma-mapping.h>
+#include <linux/vmalloc.h>
+
+MODULE_DESCRIPTION("NetXen Multi port (1/10) Gigabit Network Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(NETXEN_NIC_LINUX_VERSIONID);
+
+#ifdef CONFIG_PPC
+static int nx_ppc_msi_enable = 0; /* by default donot enable msi */
+#endif
+
+char netxen_nic_driver_name[] = "netxen-nic";
+static char netxen_nic_driver_string[] = "NetXen Network Driver version "
+ NETXEN_NIC_LINUX_VERSIONID;
+
+#define NETXEN_NETDEV_WEIGHT 120
+#define NETXEN_ADAPTER_UP_MAGIC 777
+#define NETXEN_NIC_PEG_TUNE 0
+
+u8 nx_p2_id = NX_P2_C0;
+
+#define DMA_32BIT_MASK 0x00000000ffffffffULL
+#define DMA_35BIT_MASK 0x00000007ffffffffULL
+
+/* Local functions to NetXen NIC driver */
+static int __devinit netxen_nic_probe(struct pci_dev *pdev,
+ const struct pci_device_id *ent);
+static void __devexit netxen_nic_remove(struct pci_dev *pdev);
+static int netxen_nic_open(struct net_device *netdev);
+static int netxen_nic_close(struct net_device *netdev);
+static int netxen_nic_xmit_frame(struct sk_buff *, struct net_device *);
+static void netxen_tx_timeout(struct net_device *netdev);
+static void netxen_tx_timeout_task(unsigned long adapid);
+static void netxen_watchdog(unsigned long);
+static int netxen_handle_int(struct netxen_adapter *, struct net_device *);
+static int netxen_nic_poll(struct net_device *dev, int *budget);
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void netxen_nic_poll_controller(struct net_device *netdev);
+#endif
+static irqreturn_t netxen_intr(int irq, void *data, struct pt_regs *regs);
+
+int physical_port[] = {0, 1, 2, 3};
+
+/* PCI Device ID Table */
+static struct pci_device_id netxen_pci_tbl[] __devinitdata = {
+ {PCI_DEVICE(0x4040, 0x0001)},
+ {PCI_DEVICE(0x4040, 0x0002)},
+ {PCI_DEVICE(0x4040, 0x0003)},
+ {PCI_DEVICE(0x4040, 0x0004)},
+ {PCI_DEVICE(0x4040, 0x0005)},
+ {PCI_DEVICE(0x4040, 0x0024)},
+ {PCI_DEVICE(0x4040, 0x0025)},
+ {0,}
+};
+
+MODULE_DEVICE_TABLE(pci, netxen_pci_tbl);
+
+struct workqueue_struct *netxen_workq;
+static void netxen_watchdog(unsigned long);
+
+static inline void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
+ uint32_t crb_producer)
+{
+ switch (adapter->portnum) {
+ case 0:
+ writel(crb_producer, NETXEN_CRB_NORMALIZE
+ (adapter, CRB_CMD_PRODUCER_OFFSET));
+ return;
+ case 1:
+ writel(crb_producer, NETXEN_CRB_NORMALIZE
+ (adapter, CRB_CMD_PRODUCER_OFFSET_1));
+ return;
+ case 2:
+ writel(crb_producer, NETXEN_CRB_NORMALIZE
+ (adapter, CRB_CMD_PRODUCER_OFFSET_2));
+ return;
+ case 3:
+ writel(crb_producer, NETXEN_CRB_NORMALIZE
+ (adapter, CRB_CMD_PRODUCER_OFFSET_3));
+ return;
+ default:
+ printk(KERN_WARNING "We tried to update "
+ "CRB_CMD_PRODUCER_OFFSET for invalid "
+ "PCI function id %d\n",
+ adapter->portnum);
+ return;
+ }
+}
+
+static inline void netxen_nic_update_cmd_consumer(struct netxen_adapter *adapter,
+ u32 crb_consumer)
+{
+ switch (adapter->portnum) {
+ case 0:
+ writel(crb_consumer, NETXEN_CRB_NORMALIZE
+ (adapter, CRB_CMD_CONSUMER_OFFSET));
+ return;
+ case 1:
+ writel(crb_consumer, NETXEN_CRB_NORMALIZE
+ (adapter, CRB_CMD_CONSUMER_OFFSET_1));
+ return;
+ case 2:
+ writel(crb_consumer, NETXEN_CRB_NORMALIZE
+ (adapter, CRB_CMD_CONSUMER_OFFSET_2));
+ return;
+ case 3:
+ writel(crb_consumer, NETXEN_CRB_NORMALIZE
+ (adapter, CRB_CMD_CONSUMER_OFFSET_3));
+ return;
+ default:
+ printk(KERN_WARNING "We tried to update "
+ "CRB_CMD_PRODUCER_OFFSET for invalid "
+ "PCI function id %d\n",
+ adapter->portnum);
+ return;
+ }
+}
+
+#define ADAPTER_LIST_SIZE 12
+int netxen_cards_found;
+
+/*
+ * netxen_nic_probe()
+ *
+ * The Linux system will invoke this after identifying the vendor ID and
+ * device Id in the pci_tbl supported by this module.
+ *
+ * A quad port card has one operational PCI config space, (function 0),
+ * which is used to access all four ports.
+ *
+ * This routine will initialize the adapter, and setup the global parameters
+ * along with the port's specific structure.
+ */
+static int __devinit
+netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ struct net_device *netdev = NULL;
+ struct netxen_adapter *adapter = NULL;
+ void __iomem *mem_ptr0 = NULL;
+ void __iomem *mem_ptr1 = NULL;
+ void __iomem *mem_ptr2 = NULL;
+ unsigned long first_page_group_end;
+ unsigned long first_page_group_start;
+
+
+ u8 __iomem *db_ptr = NULL;
+ unsigned long mem_base, mem_len, db_base, db_len;
+ int pci_using_dac, i = 0, err;
+ int ring;
+ struct netxen_recv_context *recv_ctx = NULL;
+ struct netxen_rcv_desc_ctx *rcv_desc = NULL;
+ struct netxen_cmd_buffer *cmd_buf_arr = NULL;
+ u64 mac_addr[FLASH_NUM_PORTS + 1];
+ int valid_mac = 0;
+ u32 val;
+ int pci_func_id = PCI_FUNC(pdev->devfn);
+
+ printk(KERN_INFO "%s \n", netxen_nic_driver_string);
+
+#ifdef CONFIG_PPC
+ if (nx_ppc_msi_enable && (pdev->class != 0x020000)) {
+#else /* !CONFIG_PPC */
+ if (pdev->class != 0x020000) {
+#endif /* CONFIG_PPC */
+ printk(KERN_ERR"NetXen function %d, class %x will not"
+ "be enabled.\n",pci_func_id, pdev->class);
+ return -ENODEV;
+ }
+ if ((err = pci_enable_device(pdev)))
+ return err;
+ if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
+ err = -ENODEV;
+ goto err_out_disable_pdev;
+ }
+
+ if ((err = pci_request_regions(pdev, netxen_nic_driver_name)))
+ goto err_out_disable_pdev;
+
+ pci_set_master(pdev);
+ pci_read_config_byte(pdev, PCI_REVISION_ID, &nx_p2_id);
+ if (nx_p2_id == NX_P2_C1 &&
+ (pci_set_dma_mask(pdev, DMA_35BIT_MASK) == 0) &&
+ (pci_set_consistent_dma_mask(pdev, DMA_35BIT_MASK) == 0)) {
+ pci_using_dac = 1;
+ } else {
+ if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) ||
+ (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)))
+ goto err_out_free_res;
+
+ pci_using_dac = 0;
+ }
+
+
+ netdev = alloc_etherdev(sizeof(struct netxen_adapter));
+ if(!netdev) {
+ printk(KERN_ERR"%s: Failed to allocate memory for the "
+ "device block.Check system memory resource"
+ " usage.\n", netxen_nic_driver_name);
+ goto err_out_free_res;
+ }
+
+ SET_MODULE_OWNER(netdev);
+ SET_NETDEV_DEV(netdev, &pdev->dev);
+
+ adapter = netdev->priv;
+ memset(adapter, 0 , sizeof(struct netxen_adapter));
+
+ adapter->ahw.pdev = pdev;
+ adapter->ahw.pci_func = pci_func_id;
+ spin_lock_init(&adapter->tx_lock);
+ spin_lock_init(&adapter->lock);
+
+ /* remap phys address */
+ mem_base = pci_resource_start(pdev, 0); /* 0 is for BAR 0 */
+ mem_len = pci_resource_len(pdev, 0);
+
+ /* 128 Meg of memory */
+ if (mem_len == NETXEN_PCI_128MB_SIZE) {
+ mem_ptr0 = ioremap(mem_base, FIRST_PAGE_GROUP_SIZE);
+ mem_ptr1 = ioremap(mem_base + SECOND_PAGE_GROUP_START,
+ SECOND_PAGE_GROUP_SIZE);
+ mem_ptr2 = ioremap(mem_base + THIRD_PAGE_GROUP_START,
+ THIRD_PAGE_GROUP_SIZE);
+ first_page_group_start = FIRST_PAGE_GROUP_START;
+ first_page_group_end = FIRST_PAGE_GROUP_END;
+ } else if (mem_len == NETXEN_PCI_32MB_SIZE) {
+ mem_ptr1 = ioremap(mem_base, SECOND_PAGE_GROUP_SIZE);
+ mem_ptr2 = ioremap(mem_base + THIRD_PAGE_GROUP_START -
+ SECOND_PAGE_GROUP_START, THIRD_PAGE_GROUP_SIZE);
+ first_page_group_start = 0;
+ first_page_group_end = 0;
+ } else {
+ err = -EIO;
+ goto err_out_free_netdev;
+ }
+
+ if (((mem_ptr0 == 0UL) && (mem_len == NETXEN_PCI_128MB_SIZE)) ||
+ (mem_ptr1 == 0UL) || (mem_ptr2 == 0UL)) {
+ DPRINTK(ERR,
+ "Cannot remap adapter memory aborting.:"
+ "0 -> %p, 1 -> %p, 2 -> %p\n",
+ mem_ptr0, mem_ptr1, mem_ptr2);
+
+ err = -EIO;
+ goto err_out_iounmap;
+ }
+ db_base = pci_resource_start(pdev, 4); /* doorbell is on bar 4 */
+ db_len = pci_resource_len(pdev, 4);
+
+ if (db_len == 0) {
+ printk(KERN_ERR "%s: doorbell is disabled\n",
+ netxen_nic_driver_name);
+ err = -EIO;
+ goto err_out_iounmap;
+ }
+ DPRINTK(INFO, "doorbell ioremap from %lx a size of %lx\n", db_base,
+ db_len);
+
+ db_ptr = ioremap(db_base, NETXEN_DB_MAPSIZE_BYTES);
+ if (!db_ptr) {
+ printk(KERN_ERR "%s: Failed to allocate doorbell map.",
+ netxen_nic_driver_name);
+ err = -EIO;
+ goto err_out_iounmap;
+ }
+ DPRINTK(INFO, "doorbell ioremaped at %p\n", db_ptr);
+
+ adapter->ahw.pci_base0 = mem_ptr0;
+ adapter->ahw.first_page_group_start = first_page_group_start;
+ adapter->ahw.first_page_group_end = first_page_group_end;
+ adapter->ahw.pci_base1 = mem_ptr1;
+ adapter->ahw.pci_base2 = mem_ptr2;
+ adapter->ahw.db_base = db_ptr;
+ adapter->ahw.db_len = db_len;
+
+ adapter->netdev = netdev;
+ adapter->pdev = pdev;
+ adapter->portnum = pci_func_id;
+
+ netdev->open = netxen_nic_open;
+ netdev->stop = netxen_nic_close;
+ netdev->hard_start_xmit = netxen_nic_xmit_frame;
+ netdev->get_stats = netxen_nic_get_stats;
+ netdev->set_multicast_list = netxen_nic_set_multi;
+ netdev->set_mac_address = netxen_nic_set_mac;
+ netdev->change_mtu = netxen_nic_change_mtu;
+ netdev->tx_timeout = netxen_tx_timeout;
+ netdev->watchdog_timeo = HZ;
+
+ netxen_nic_change_mtu(netdev, netdev->mtu);
+
+ SET_ETHTOOL_OPS(netdev, &netxen_nic_ethtool_ops);
+ netdev->poll = netxen_nic_poll;
+ netdev->weight = NETXEN_NETDEV_WEIGHT;
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ netdev->poll_controller = netxen_nic_poll_controller;
+#endif
+ /* ScatterGather support */
+ netdev->features = NETIF_F_SG;
+ netdev->features |= NETIF_F_IP_CSUM;
+ netdev->features |= NETIF_F_TSO;
+
+ if (pci_using_dac)
+ netdev->features |= NETIF_F_HIGHDMA;
+
+#ifdef CONFIG_PCI_MSI
+ if (pci_enable_msi(pdev)) {
+ adapter->flags &= ~NETXEN_NIC_MSI_ENABLED;
+ printk(KERN_WARNING "%s: unable to allocate MSI interrupt"
+ " error\n", netxen_nic_driver_name);
+ } else
+ adapter->flags |= NETXEN_NIC_MSI_ENABLED;
+#endif
+
+ netdev->irq = pdev->irq;
+ INIT_WORK(&adapter->tx_timeout_task,
+ (void (*)(void *))netxen_tx_timeout_task, netdev);
+
+ /*
+ * Set the CRB window to invalid. If any register in window 0 is
+ * accessed it should set the window to 0 and then reset it to 1.
+ */
+ adapter->curr_window = 255;
+
+ /* initialize the adapter */
+ netxen_initialize_adapter_hw(adapter);
+
+#ifdef CONFIG_PPC
+ if ((adapter->ahw.boardcfg.board_type ==
+ NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) &&
+ (pci_func_id == 2))
+ goto err_out_free_adapter;
+#endif /* CONFIG_PPC */
+
+ /*
+ * Adapter in our case is quad port so initialize it before
+ * initializing the ports
+ */
+
+ netxen_initialize_adapter_ops(adapter);
+
+ adapter->max_tx_desc_count = MAX_CMD_DESCRIPTORS_HOST;
+ if ((adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB35_4G) ||
+ (adapter->ahw.boardcfg.board_type ==
+ NETXEN_BRDTYPE_P2_SB31_2G))
+ adapter->max_rx_desc_count = MAX_RCV_DESCRIPTORS_1G;
+ else
+ adapter->max_rx_desc_count = MAX_RCV_DESCRIPTORS;
+ adapter->max_jumbo_rx_desc_count = MAX_JUMBO_RCV_DESCRIPTORS;
+ adapter->max_lro_rx_desc_count = MAX_LRO_RCV_DESCRIPTORS;
+
+ cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
+ if (cmd_buf_arr == NULL) {
+ printk(KERN_ERR
+ "%s: Could not allocate cmd_buf_arr memory:%d\n",
+ netxen_nic_driver_name, (int)TX_RINGSIZE);
+ err = -ENOMEM;
+ goto err_out_free_adapter;
+ }
+ memset(cmd_buf_arr, 0, TX_RINGSIZE);
+ adapter->cmd_buf_arr = cmd_buf_arr;
+
+ for (i = 0; i < MAX_RCV_CTX; ++i) {
+ recv_ctx = &adapter->recv_ctx[i];
+ for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
+ rcv_desc = &recv_ctx->rcv_desc[ring];
+ switch (RCV_DESC_TYPE(ring)) {
+ case RCV_DESC_NORMAL:
+ rcv_desc->max_rx_desc_count =
+ adapter->max_rx_desc_count;
+ rcv_desc->flags = RCV_DESC_NORMAL;
+ rcv_desc->dma_size = RX_DMA_MAP_LEN;
+ rcv_desc->skb_size = MAX_RX_BUFFER_LENGTH;
+ break;
+
+ case RCV_DESC_JUMBO:
+ rcv_desc->max_rx_desc_count =
+ adapter->max_jumbo_rx_desc_count;
+ rcv_desc->flags = RCV_DESC_JUMBO;
+ rcv_desc->dma_size = RX_JUMBO_DMA_MAP_LEN;
+ rcv_desc->skb_size = MAX_RX_JUMBO_BUFFER_LENGTH;
+ break;
+
+ case RCV_RING_LRO:
+ rcv_desc->max_rx_desc_count =
+ adapter->max_lro_rx_desc_count;
+ rcv_desc->flags = RCV_DESC_LRO;
+ rcv_desc->dma_size = RX_LRO_DMA_MAP_LEN;
+ rcv_desc->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
+ break;
+
+ }
+ rcv_desc->rx_buf_arr = (struct netxen_rx_buffer *)
+ vmalloc(RCV_BUFFSIZE);
+
+ if (rcv_desc->rx_buf_arr == NULL) {
+ printk(KERN_ERR "%s: Could not allocate"
+ "rcv_desc->rx_buf_arr memory:%d\n",
+ netxen_nic_driver_name,
+ (int)RCV_BUFFSIZE);
+ err = -ENOMEM;
+ goto err_out_free_rx_buffer;
+ }
+ memset(rcv_desc->rx_buf_arr, 0, RCV_BUFFSIZE);
+ }
+
+ }
+
+ netxen_initialize_adapter_sw(adapter); /* initialize the buffers in adapter */
+
+ /* Mezz cards have PCI function 0,2,3 enabled */
+ if ((adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ)
+ && (pci_func_id >= 2))
+ adapter->portnum = pci_func_id - 2;
+
+#ifdef CONFIG_IA64
+ if(adapter->portnum == 0) {
+ netxen_pinit_from_rom(adapter, 0);
+ udelay(500);
+ netxen_load_firmware(adapter);
+ }
+#endif
+
+ init_timer(&adapter->watchdog_timer);
+ adapter->ahw.xg_linkup = 0;
+ adapter->watchdog_timer.function = &netxen_watchdog;
+ adapter->watchdog_timer.data = (unsigned long)adapter;
+ INIT_WORK(&adapter->watchdog_task,
+ (void (*)(void *))netxen_watchdog_task, adapter);
+ adapter->ahw.pdev = pdev;
+ adapter->proc_cmd_buf_counter = 0;
+ adapter->ahw.revision_id = nx_p2_id;
+
+ /* make sure Window == 1 */
+ netxen_nic_pci_change_crbwindow(adapter, 1);
+
+ netxen_nic_update_cmd_producer(adapter, 0);
+ netxen_nic_update_cmd_consumer(adapter, 0);
+ writel(0, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_CMD_ADDR_LO));
+
+ if (netxen_is_flash_supported(adapter) == 0 &&
+ netxen_get_flash_mac_addr(adapter, mac_addr) == 0)
+ valid_mac = 1;
+ else
+ valid_mac = 0;
+
+ if (valid_mac) {
+ unsigned char *p = (unsigned char *)&mac_addr[adapter->portnum];
+ netdev->dev_addr[0] = *(p + 5);
+ netdev->dev_addr[1] = *(p + 4);
+ netdev->dev_addr[2] = *(p + 3);
+ netdev->dev_addr[3] = *(p + 2);
+ netdev->dev_addr[4] = *(p + 1);
+ netdev->dev_addr[5] = *(p + 0);
+
+ if (!is_valid_ether_addr(netdev->dev_addr)) {
+ printk(KERN_ERR "%s: Bad MAC address "
+ "%02x:%02x:%02x:%02x:%02x:%02x.\n",
+ netxen_nic_driver_name,
+ netdev->dev_addr[0],
+ netdev->dev_addr[1],
+ netdev->dev_addr[2],
+ netdev->dev_addr[3],
+ netdev->dev_addr[4],
+ netdev->dev_addr[5]);
+ } else {
+ if (adapter->macaddr_set)
+ adapter->macaddr_set(adapter,
+ netdev->dev_addr);
+ }
+ }
+
+ if (adapter->portnum == 0) {
+ err = netxen_initialize_adapter_offload(adapter);
+ if (err)
+ goto err_out_free_rx_buffer;
+ val = readl(NETXEN_CRB_NORMALIZE(adapter,
+ NETXEN_CAM_RAM(0x1fc)));
+ if (val == 0x55555555) {
+ /* This is the first boot after power up */
+ val = readl(NETXEN_CRB_NORMALIZE(adapter,
+ NETXEN_ROMUSB_GLB_SW_RESET));
+ printk(KERN_INFO"NetXen: read 0x%08x for reset reg.\n",val);
+ if (val != 0x80000f) {
+ /* clear the register for future unloads/loads */
+ writel(0, NETXEN_CRB_NORMALIZE(adapter,
+ NETXEN_CAM_RAM(0x1fc)));
+ printk(KERN_ERR "ERROR in NetXen HW init sequence.\n");
+ err = -ENODEV;
+ goto err_out_free_dev;
+ }
+
+ /* clear the register for future unloads/loads */
+ writel(0, NETXEN_CRB_NORMALIZE(adapter,
+ NETXEN_CAM_RAM(0x1fc)));
+ }
+ printk(KERN_INFO "State: 0x%0x\n",
+ readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)));
+
+ /*
+ * Tell the hardware our version number.
+ */
+ i = (_NETXEN_NIC_LINUX_MAJOR << 16)
+ | ((_NETXEN_NIC_LINUX_MINOR << 8))
+ | (_NETXEN_NIC_LINUX_SUBVERSION);
+ writel(i, NETXEN_CRB_NORMALIZE(adapter, CRB_DRIVER_VERSION));
+
+ /* Unlock the HW, prompting the boot sequence */
+ writel(1,
+ NETXEN_CRB_NORMALIZE(adapter,
+ NETXEN_ROMUSB_GLB_PEGTUNE_DONE));
+ /* Handshake with the card before we register the devices. */
+ netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE);
+ }
+
+ /*
+ * See if the firmware gave us a virtual-physical port mapping.
+ */
+ i = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_V2P(adapter->portnum)));
+ if (i != 0x55555555)
+ physical_port[adapter->portnum] = i;
+
+ netif_carrier_off(netdev);
+ netif_stop_queue(netdev);
+
+ if ((err = register_netdev(netdev))) {
+ printk(KERN_ERR "%s: register_netdev failed port #%d"
+ " aborting\n", netxen_nic_driver_name,
+ adapter->portnum);
+ err = -EIO;
+ goto err_out_free_dev;
+ }
+
+ pci_set_drvdata(pdev, adapter);
+
+ switch (adapter->ahw.board_type) {
+ case NETXEN_NIC_GBE:
+ printk(KERN_INFO "%s: QUAD GbE board initialized\n",
+ netxen_nic_driver_name);
+ break;
+
+ case NETXEN_NIC_XGBE:
+ printk(KERN_INFO "%s: XGbE board initialized\n",
+ netxen_nic_driver_name);
+ break;
+ }
+
+ adapter->driver_mismatch = 0;
+
+ return 0;
+
+err_out_free_dev:
+ if (adapter->portnum == 0)
+ netxen_free_adapter_offload(adapter);
+
+err_out_free_rx_buffer:
+ for (i = 0; i < MAX_RCV_CTX; ++i) {
+ recv_ctx = &adapter->recv_ctx[i];
+ for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
+ rcv_desc = &recv_ctx->rcv_desc[ring];
+ if (rcv_desc->rx_buf_arr != NULL) {
+ vfree(rcv_desc->rx_buf_arr);
+ rcv_desc->rx_buf_arr = NULL;
+ }
+ }
+ }
+ vfree(cmd_buf_arr);
+
+err_out_free_adapter:
+#ifdef CONFIG_PCI_MSI
+ if (adapter->flags & NETXEN_NIC_MSI_ENABLED)
+ pci_disable_msi(pdev);
+#endif
+
+ pci_set_drvdata(pdev, NULL);
+
+ if (db_ptr)
+ iounmap(db_ptr);
+
+err_out_iounmap:
+ if (mem_ptr0)
+ iounmap(mem_ptr0);
+ if (mem_ptr1)
+ iounmap(mem_ptr1);
+ if (mem_ptr2)
+ iounmap(mem_ptr2);
+
+err_out_free_netdev:
+ free_netdev(netdev);
+
+err_out_free_res:
+ pci_release_regions(pdev);
+
+err_out_disable_pdev:
+ pci_disable_device(pdev);
+ return err;
+}
+
+static void __devexit netxen_nic_remove(struct pci_dev *pdev)
+{
+ struct netxen_adapter *adapter;
+ struct net_device *netdev;
+ struct netxen_rx_buffer *buffer;
+ struct netxen_recv_context *recv_ctx;
+ struct netxen_rcv_desc_ctx *rcv_desc;
+ int i;
+ int ctxid, ring;
+
+ adapter = pci_get_drvdata(pdev);
+ if (adapter == NULL)
+ return;
+
+ netdev = adapter->netdev;
+
+ netxen_nic_disable_int(adapter);
+ if (adapter->irq)
+ free_irq(adapter->irq, adapter);
+
+ if (adapter->stop_port)
+ adapter->stop_port(adapter);
+
+#ifdef CONFIG_PCI_MSI
+ if ((adapter->flags & NETXEN_NIC_MSI_ENABLED))
+ pci_disable_msi(pdev);
+#endif
+
+ if (adapter->portnum == 0)
+ netxen_free_adapter_offload(adapter);
+
+ if(adapter->portnum == 0) {
+ /* leave the hw in the same state as reboot */
+ writel(0, NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
+ netxen_pinit_from_rom(adapter, 0);
+ udelay(500);
+ netxen_load_firmware(adapter);
+ netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE);
+ }
+
+ if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC)
+ netxen_free_hw_resources(adapter);
+
+ for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
+ recv_ctx = &adapter->recv_ctx[ctxid];
+ for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
+ rcv_desc = &recv_ctx->rcv_desc[ring];
+ for (i = 0; i < rcv_desc->max_rx_desc_count; ++i) {
+ buffer = &(rcv_desc->rx_buf_arr[i]);
+ if (buffer->state == NETXEN_BUFFER_FREE)
+ continue;
+ pci_unmap_single(pdev, buffer->dma,
+ rcv_desc->dma_size,
+ PCI_DMA_FROMDEVICE);
+ if (buffer->skb != NULL)
+ dev_kfree_skb_any(buffer->skb);
+ }
+ vfree(rcv_desc->rx_buf_arr);
+ }
+ }
+
+ unregister_netdev(netdev);
+
+ vfree(adapter->cmd_buf_arr);
+
+ iounmap(adapter->ahw.db_base);
+ iounmap(adapter->ahw.pci_base0);
+ iounmap(adapter->ahw.pci_base1);
+ iounmap(adapter->ahw.pci_base2);
+
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ pci_set_drvdata(pdev, NULL);
+
+ free_netdev(netdev);
+}
+
+/*
+ * Called when a network interface is made active
+ * @returns 0 on success, negative value on failure
+ */
+static int netxen_nic_open(struct net_device *netdev)
+{
+ struct netxen_adapter *adapter = (struct netxen_adapter *)netdev->priv;
+ int err = 0;
+ int ctx, ring;
+
+ if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) {
+ err = netxen_init_firmware(adapter);
+ if (err != 0) {
+ printk(KERN_ERR "Failed to init firmware\n");
+ return -EIO;
+ }
+ netxen_nic_flash_print(adapter);
+
+ /* setup all the resources for the Phantom... */
+ /* this include the descriptors for rcv, tx, and status */
+ netxen_nic_clear_stats(adapter);
+ err = netxen_nic_hw_resources(adapter);
+ if (err) {
+ printk(KERN_ERR "Error in setting hw resources:%d\n",
+ err);
+ return err;
+ }
+ for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
+ for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++)
+ netxen_post_rx_buffers(adapter, ctx, ring);
+ }
+ adapter->irq = adapter->ahw.pdev->irq;
+ err = request_irq(adapter->ahw.pdev->irq, netxen_intr,
+ SA_SHIRQ | SA_SAMPLE_RANDOM, netdev->name,
+ adapter);
+ if (err) {
+ printk(KERN_ERR "request_irq failed with: %d\n", err);
+ netxen_free_hw_resources(adapter);
+ return err;
+ }
+
+ adapter->is_up = NETXEN_ADAPTER_UP_MAGIC;
+ }
+ if (!adapter->driver_mismatch)
+ mod_timer(&adapter->watchdog_timer, jiffies);
+
+ netxen_nic_enable_int(adapter);
+
+ /* Done here again so that even if phantom sw overwrote it,
+ * we set it */
+ if (adapter->macaddr_set)
+ adapter->macaddr_set(adapter, netdev->dev_addr);
+ if (adapter->init_port
+ && adapter->init_port(adapter, adapter->portnum) != 0) {
+ del_timer_sync(&adapter->watchdog_timer);
+ printk(KERN_ERR "%s: Failed to initialize port %d\n",
+ netxen_nic_driver_name, adapter->portnum);
+ return -EIO;
+ }
+
+ netxen_nic_set_link_parameters(adapter);
+
+ netxen_nic_set_multi(netdev);
+ if (adapter->set_mtu)
+ adapter->set_mtu(adapter, netdev->mtu);
+
+ if (!adapter->driver_mismatch)
+ netif_start_queue(netdev);
+
+ return 0;
+}
+
+/*
+ * netxen_nic_close - Disables a network interface entry point
+ */
+static int netxen_nic_close(struct net_device *netdev)
+{
+ struct netxen_adapter *adapter = netdev_priv(netdev);
+ int i, j;
+ struct netxen_cmd_buffer *cmd_buff;
+ struct netxen_skb_frag *buffrag;
+
+ netif_carrier_off(netdev);
+ netif_stop_queue(netdev);
+
+ cmd_buff = adapter->cmd_buf_arr;
+ for (i = 0; i < adapter->max_tx_desc_count; i++) {
+ buffrag = cmd_buff->frag_array;
+ if (buffrag->dma) {
+ pci_unmap_single(adapter->pdev, buffrag->dma,
+ buffrag->length, PCI_DMA_TODEVICE);
+ buffrag->dma = (u64) NULL;
+ }
+ for (j = 0; j < cmd_buff->frag_count; j++) {
+ buffrag++;
+ if (buffrag->dma) {
+ pci_unmap_page(adapter->pdev, buffrag->dma,
+ buffrag->length,
+ PCI_DMA_TODEVICE);
+ buffrag->dma = (u64) NULL;
+ }
+ }
+ /* Free the skb we received in netxen_nic_xmit_frame */
+ if (cmd_buff->skb) {
+ dev_kfree_skb_any(cmd_buff->skb);
+ cmd_buff->skb = NULL;
+ }
+ cmd_buff++;
+ }
+ FLUSH_SCHEDULED_WORK();
+ del_timer_sync(&adapter->watchdog_timer);
+
+ return 0;
+}
+
+static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
+{
+ struct netxen_adapter *adapter = netdev_priv(netdev);
+ struct netxen_hardware_context *hw = &adapter->ahw;
+ unsigned int first_seg_len = skb->len - skb->data_len;
+ struct netxen_skb_frag *buffrag;
+ unsigned int i;
+
+ u32 producer = 0;
+ u32 saved_producer = 0;
+ struct cmd_desc_type0 *hwdesc;
+ int k;
+ struct netxen_cmd_buffer *pbuf = NULL;
+ static int dropped_packet = 0;
+ int frag_count;
+ u32 local_producer = 0;
+ u32 max_tx_desc_count = 0;
+ u32 last_cmd_consumer = 0;
+ int no_of_desc;
+
+ adapter->stats.xmitcalled++;
+ frag_count = skb_shinfo(skb)->nr_frags + 1;
+
+ if (unlikely(skb->len <= 0)) {
+ dev_kfree_skb_any(skb);
+ adapter->stats.badskblen++;
+ return NETDEV_TX_OK;
+ }
+
+ if (frag_count > MAX_BUFFERS_PER_CMD) {
+ printk("%s: %s netxen_nic_xmit_frame: frag_count (%d)"
+ "too large, can handle only %d frags\n",
+ netxen_nic_driver_name, netdev->name,
+ frag_count, MAX_BUFFERS_PER_CMD);
+ adapter->stats.txdropped++;
+ if ((++dropped_packet & 0xff) == 0xff)
+ printk("%s: %s droppped packets = %d\n",
+ netxen_nic_driver_name, netdev->name,
+ dropped_packet);
+
+ return NETDEV_TX_OK;
+ }
+
+ /*
+ * Everything is set up. Now, we just need to transmit it out.
+ * Note that we have to copy the contents of buffer over to
+ * right place. Later on, this can be optimized out by de-coupling the
+ * producer index from the buffer index.
+ */
+ retry_getting_window:
+ spin_lock_bh(&adapter->tx_lock);
+ if (adapter->total_threads >= MAX_XMIT_PRODUCERS) {
+ spin_unlock_bh(&adapter->tx_lock);
+ /*
+ * Yield CPU
+ */
+ if (!in_atomic())
+ schedule();
+ else {
+ for (i = 0; i < 20; i++)
+ cpu_relax(); /*This a nop instr on i386 */
+ }
+ goto retry_getting_window;
+ }
+ local_producer = adapter->cmd_producer;
+ /* There 4 fragments per descriptor */
+ no_of_desc = (frag_count + 3) >> 2;
+ if (netdev->features & NETIF_F_TSO) {
+ if (skb_shinfo(skb)->gso_size > 0) {
+ no_of_desc++;
+ if (((skb->nh.iph)->ihl * sizeof(u32)) +
+ ((skb->h.th)->doff * sizeof(u32)) +
+ sizeof(struct ethhdr) >
+ (sizeof(struct cmd_desc_type0) - 2)) {
+ no_of_desc++;
+ }
+ }
+ }
+ k = adapter->cmd_producer;
+ max_tx_desc_count = adapter->max_tx_desc_count;
+ last_cmd_consumer = adapter->last_cmd_consumer;
+ if ((k + no_of_desc) >=
+ ((last_cmd_consumer <= k) ? last_cmd_consumer + max_tx_desc_count :
+ last_cmd_consumer)) {
+ netif_stop_queue(netdev);
+ adapter->flags |= NETXEN_NETDEV_STATUS;
+ spin_unlock_bh(&adapter->tx_lock);
+ return NETDEV_TX_BUSY;
+ }
+ k = get_index_range(k, max_tx_desc_count, no_of_desc);
+ adapter->cmd_producer = k;
+ adapter->total_threads++;
+ adapter->num_threads++;
+
+ spin_unlock_bh(&adapter->tx_lock);
+ /* Copy the descriptors into the hardware */
+ producer = local_producer;
+ saved_producer = producer;
+ hwdesc = &hw->cmd_desc_head[producer];
+ memset(hwdesc, 0, sizeof(struct cmd_desc_type0));
+ /* Take skb->data itself */
+ pbuf = &adapter->cmd_buf_arr[producer];
+ if ((netdev->features & NETIF_F_TSO) && skb_shinfo(skb)->gso_size > 0) {
+ pbuf->mss = skb_shinfo(skb)->gso_size;
+ hwdesc->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
+ } else {
+ pbuf->mss = 0;
+ hwdesc->mss = 0;
+ }
+ pbuf->total_length = skb->len;
+ pbuf->skb = skb;
+ pbuf->cmd = TX_ETHER_PKT;
+ pbuf->frag_count = frag_count;
+ pbuf->port = adapter->portnum;
+ buffrag = &pbuf->frag_array[0];
+ buffrag->dma = pci_map_single(adapter->pdev, skb->data, first_seg_len,
+ PCI_DMA_TODEVICE);
+ buffrag->length = first_seg_len;
+ netxen_set_cmd_desc_totallength(hwdesc, skb->len);
+ netxen_set_cmd_desc_num_of_buff(hwdesc, frag_count);
+ netxen_set_cmd_desc_opcode(hwdesc, TX_ETHER_PKT);
+
+ netxen_set_cmd_desc_port(hwdesc, adapter->portnum);
+ netxen_set_cmd_desc_ctxid(hwdesc, adapter->portnum);
+ hwdesc->buffer1_length = cpu_to_le16(first_seg_len);
+ hwdesc->addr_buffer1 = cpu_to_le64(buffrag->dma);
+
+ for (i = 1, k = 1; i < frag_count; i++, k++) {
+ struct skb_frag_struct *frag;
+ int len, temp_len;
+ unsigned long offset;
+ dma_addr_t temp_dma;
+
+ /* move to next desc. if there is a need */
+ if ((i & 0x3) == 0) {
+ k = 0;
+ producer = get_next_index(producer,
+ adapter->max_tx_desc_count);
+ hwdesc = &hw->cmd_desc_head[producer];
+ memset(hwdesc, 0, sizeof(struct cmd_desc_type0));
+ }
+ frag = &skb_shinfo(skb)->frags[i - 1];
+ len = frag->size;
+ offset = frag->page_offset;
+
+ temp_len = len;
+ temp_dma = pci_map_page(adapter->pdev, frag->page, offset,
+ len, PCI_DMA_TODEVICE);
+
+ buffrag++;
+ buffrag->dma = temp_dma;
+ buffrag->length = temp_len;
+
+ DPRINTK(INFO, "for loop. i=%d k=%d\n", i, k);
+ switch (k) {
+ case 0:
+ hwdesc->buffer1_length = cpu_to_le16(temp_len);
+ hwdesc->addr_buffer1 = cpu_to_le64(temp_dma);
+ break;
+ case 1:
+ hwdesc->buffer2_length = cpu_to_le16(temp_len);
+ hwdesc->addr_buffer2 = cpu_to_le64(temp_dma);
+ break;
+ case 2:
+ hwdesc->buffer3_length = cpu_to_le16(temp_len);
+ hwdesc->addr_buffer3 = cpu_to_le64(temp_dma);
+ break;
+ case 3:
+ hwdesc->buffer4_length = cpu_to_le16(temp_len);
+ hwdesc->addr_buffer4 = cpu_to_le64(temp_dma);
+ break;
+ }
+ frag++;
+ }
+ producer = get_next_index(producer, adapter->max_tx_desc_count);
+
+ /* might change opcode to TX_TCP_LSO */
+ netxen_tso_check(adapter, &hw->cmd_desc_head[saved_producer], skb);
+
+ /* For LSO, we need to copy the MAC/IP/TCP headers into
+ * the descriptor ring
+ */
+ if (netxen_get_cmd_desc_opcode(&hw->cmd_desc_head[saved_producer])
+ == TX_TCP_LSO) {
+ int hdr_len, first_hdr_len, more_hdr;
+ hdr_len = hw->cmd_desc_head[saved_producer].total_hdr_length;
+ if (hdr_len > (sizeof(struct cmd_desc_type0) - 2)) {
+ first_hdr_len = sizeof(struct cmd_desc_type0) - 2;
+ more_hdr = 1;
+ } else {
+ first_hdr_len = hdr_len;
+ more_hdr = 0;
+ }
+ /* copy the MAC/IP/TCP headers to the cmd descriptor list */
+ hwdesc = &hw->cmd_desc_head[producer];
+
+ /* copy the first 64 bytes */
+ memcpy(((void *)hwdesc) + 2,
+ (void *)(skb->data), first_hdr_len);
+ producer = get_next_index(producer, max_tx_desc_count);
+
+ if (more_hdr) {
+ hwdesc = &hw->cmd_desc_head[producer];
+ /* copy the next 64 bytes - should be enough except
+ * for pathological case
+ */
+ skb_copy_from_linear_data_offset(skb, first_hdr_len,
+ hwdesc,
+ (hdr_len -
+ first_hdr_len));
+ producer = get_next_index(producer, max_tx_desc_count);
+ }
+ }
+
+ i = netxen_get_cmd_desc_totallength(&hw->cmd_desc_head[saved_producer]);
+
+ hw->cmd_desc_head[saved_producer].flags_opcode =
+ cpu_to_le16(hw->cmd_desc_head[saved_producer].flags_opcode);
+ hw->cmd_desc_head[saved_producer].num_of_buffers_total_length =
+ cpu_to_le32(hw->cmd_desc_head[saved_producer].
+ num_of_buffers_total_length);
+
+ spin_lock_bh(&adapter->tx_lock);
+ adapter->stats.txbytes += i;
+
+ /* Code to update the adapter considering how many producer threads
+ are currently working */
+ if ((--adapter->num_threads) == 0) {
+ /* This is the last thread */
+ u32 crb_producer = adapter->cmd_producer;
+ netxen_nic_update_cmd_producer(adapter, crb_producer);
+ wmb();
+ adapter->total_threads = 0;
+ }
+
+ adapter->stats.xmitfinished++;
+ spin_unlock_bh(&adapter->tx_lock);
+
+ netdev->trans_start = jiffies;
+
+ DPRINTK(INFO, "wrote CMD producer %x to phantom\n", producer);
+
+ DPRINTK(INFO, "Done. Send\n");
+ return NETDEV_TX_OK;
+}
+
+static void netxen_watchdog(unsigned long v)
+{
+ struct netxen_adapter *adapter = (struct netxen_adapter *)v;
+
+ SCHEDULE_WORK(&adapter->watchdog_task);
+}
+
+static void netxen_tx_timeout(struct net_device *netdev)
+{
+ struct netxen_adapter *adapter = (struct netxen_adapter *)
+ netdev_priv(netdev);
+ SCHEDULE_WORK(&adapter->tx_timeout_task);
+}
+
+static void netxen_tx_timeout_task(unsigned long adapid)
+{
+ struct net_device *netdev = (struct net_device *)adapid;
+ struct netxen_adapter *adapter = (struct netxen_adapter *)
+ netdev_priv(netdev);
+ unsigned long flags;
+
+ printk(KERN_ERR "%s %s: transmit timeout, resetting.\n",
+ netxen_nic_driver_name, adapter->netdev->name);
+
+ spin_lock_irqsave(&adapter->lock, flags);
+ netxen_nic_close(adapter->netdev);
+ netxen_nic_open(adapter->netdev);
+ spin_unlock_irqrestore(&adapter->lock, flags);
+ adapter->netdev->trans_start = jiffies;
+ netif_wake_queue(adapter->netdev);
+}
+
+static int
+netxen_handle_int(struct netxen_adapter *adapter, struct net_device *netdev)
+{
+ u32 ret = 0;
+
+ DPRINTK(INFO, "Entered handle ISR\n");
+ adapter->stats.ints++;
+
+ if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
+ int count = 0;
+ u32 mask;
+ u32 our_int = 0;
+ our_int = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_INT_VECTOR));
+ /* not our interrupt */
+ if ((our_int & (0x80 << adapter->portnum)) == 0)
+ return ret;
+ netxen_nic_disable_int(adapter);
+ /* Window = 0 or 1 */
+ do {
+ writel(0xffffffff, PCI_OFFSET_SECOND_RANGE(adapter,
+ ISR_INT_TARGET_STATUS));
+ mask = readl(pci_base_offset(adapter, ISR_INT_VECTOR));
+ } while (((mask & 0x80) != 0) && (++count < 32));
+ if ((mask & 0x80) != 0)
+ printk("Could not disable interrupt completely\n");
+
+ }
+
+ if (netxen_nic_rx_has_work(adapter) || netxen_nic_tx_has_work(adapter)) {
+ if (netif_rx_schedule_prep(netdev)) {
+ /*
+ * Interrupts are already disabled.
+ */
+ __netif_rx_schedule(netdev);
+ } else {
+ static unsigned int intcount = 0;
+ if ((++intcount & 0xfff) == 0xfff)
+ printk(KERN_ERR
+ "%s: %s interrupt %d while in poll\n",
+ netxen_nic_driver_name, netdev->name,
+ intcount);
+ }
+ ret = 1;
+ }
+
+ if (ret == 0) {
+ netxen_nic_enable_int(adapter);
+ }
+
+ return ret;
+}
+
+/*
+ * netxen_intr - Interrupt Handler
+ * @irq: interrupt number
+ * data points to adapter stucture (which may be handling more than 1 port
+ */
+static irqreturn_t netxen_intr(int irq, void *data, struct pt_regs *regs)
+{
+ struct netxen_adapter *adapter;
+ struct net_device *netdev;
+
+ if (unlikely(!irq)) {
+ return IRQ_NONE; /* Not our interrupt */
+ }
+
+ adapter = (struct netxen_adapter *)data;
+ netdev = adapter->netdev;
+ /* process our status queue (for all 4 ports) */
+ if (netif_running(netdev))
+ netxen_handle_int(adapter, netdev);
+
+ return IRQ_HANDLED;
+}
+
+static int netxen_nic_poll(struct net_device *netdev, int *budget)
+{
+ struct netxen_adapter *adapter = netdev_priv(netdev);
+ int work_to_do = min(*budget, netdev->quota);
+ int done = 1;
+ int ctx;
+ int this_work_done;
+ int work_done = 0;
+
+ DPRINTK(INFO, "polling for %d descriptors\n", *budget);
+
+ work_done = 0;
+ for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
+ /*
+ * Fairness issue. This will give undue weight to the
+ * receive context 0.
+ */
+
+ /*
+ * To avoid starvation, we give each of our receivers,
+ * a fraction of the quota. Sometimes, it might happen that we
+ * have enough quota to process every packet, but since all the
+ * packets are on one context, it gets only half of the quota,
+ * and ends up not processing it.
+ */
+ this_work_done = netxen_process_rcv_ring(adapter, ctx,
+ work_to_do /
+ MAX_RCV_CTX);
+ work_done += this_work_done;
+ }
+
+ netdev->quota -= work_done;
+ *budget -= work_done;
+
+ if (work_done >= work_to_do && netxen_nic_rx_has_work(adapter) != 0)
+ done = 0;
+
+ if (netxen_process_cmd_ring((unsigned long)adapter) == 0)
+ done = 0;
+
+ DPRINTK(INFO, "new work_done: %d work_to_do: %d\n",
+ work_done, work_to_do);
+ if (done) {
+ netif_rx_complete(netdev);
+ netxen_nic_enable_int(adapter);
+ }
+
+ return !done;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void netxen_nic_poll_controller(struct net_device *netdev)
+{
+ struct netxen_adapter *adapter = netdev_priv(netdev);
+ disable_irq(adapter->irq);
+ netxen_intr(adapter->irq, adapter, NULL);
+ enable_irq(adapter->irq);
+}
+#endif
+
+static struct pci_driver netxen_driver = {
+ .name = netxen_nic_driver_name,
+ .id_table = netxen_pci_tbl,
+ .probe = netxen_nic_probe,
+ .remove = __devexit_p(netxen_nic_remove)
+};
+
+/* Driver Registration on NetXen card */
+
+static int __init netxen_init_module(void)
+{
+ if ((netxen_workq = create_singlethread_workqueue("netxen")) == 0)
+ return -ENOMEM;
+
+ return pci_register_driver(&netxen_driver);
+}
+
+module_init(netxen_init_module);
+
+static void __exit netxen_exit_module(void)
+{
+ /*
+ * Wait for some time to allow the dma to drain, if any.
+ */
+ pci_unregister_driver(&netxen_driver);
+ destroy_workqueue(netxen_workq);
+}
+
+module_exit(netxen_exit_module);
--- linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_init.c.rhel5
+++ linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_init.c
@@ -0,0 +1,1541 @@
+/*
+ * Copyright (C) 2003 - 2006 NetXen, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
+ * MA 02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.
+ *
+ * Contact Information:
+ * info@netxen.com
+ * NetXen,
+ * 3965 Freedom Circle, Fourth floor,
+ * Santa Clara, CA 95054
+ *
+ *
+ * Source file for NIC routines to initialize the Phantom Hardware
+ *
+ */
+
+#include <linux/netdevice.h>
+#include <linux/delay.h>
+#include "netxen_nic.h"
+#include "netxen_nic_hw.h"
+#include "netxen_nic_phan_reg.h"
+
+struct crb_addr_pair {
+ u32 addr;
+ u32 data;
+};
+
+unsigned long last_schedule_time;
+
+#define NETXEN_MAX_CRB_XFORM 60
+static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
+#define NETXEN_ADDR_ERROR (0xffffffff)
+
+#define crb_addr_transform(name) \
+ crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
+ NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
+
+#define NETXEN_NIC_XDMA_RESET 0x8000ff
+
+static inline void
+netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
+ unsigned long off, int *data)
+{
+ void __iomem *addr = pci_base_offset(adapter, off);
+ writel(*data, addr);
+}
+
+static void crb_addr_transform_setup(void)
+{
+ crb_addr_transform(XDMA);
+ crb_addr_transform(TIMR);
+ crb_addr_transform(SRE);
+ crb_addr_transform(SQN3);
+ crb_addr_transform(SQN2);
+ crb_addr_transform(SQN1);
+ crb_addr_transform(SQN0);
+ crb_addr_transform(SQS3);
+ crb_addr_transform(SQS2);
+ crb_addr_transform(SQS1);
+ crb_addr_transform(SQS0);
+ crb_addr_transform(RPMX7);
+ crb_addr_transform(RPMX6);
+ crb_addr_transform(RPMX5);
+ crb_addr_transform(RPMX4);
+ crb_addr_transform(RPMX3);
+ crb_addr_transform(RPMX2);
+ crb_addr_transform(RPMX1);
+ crb_addr_transform(RPMX0);
+ crb_addr_transform(ROMUSB);
+ crb_addr_transform(SN);
+ crb_addr_transform(QMN);
+ crb_addr_transform(QMS);
+ crb_addr_transform(PGNI);
+ crb_addr_transform(PGND);
+ crb_addr_transform(PGN3);
+ crb_addr_transform(PGN2);
+ crb_addr_transform(PGN1);
+ crb_addr_transform(PGN0);
+ crb_addr_transform(PGSI);
+ crb_addr_transform(PGSD);
+ crb_addr_transform(PGS3);
+ crb_addr_transform(PGS2);
+ crb_addr_transform(PGS1);
+ crb_addr_transform(PGS0);
+ crb_addr_transform(PS);
+ crb_addr_transform(PH);
+ crb_addr_transform(NIU);
+ crb_addr_transform(I2Q);
+ crb_addr_transform(EG);
+ crb_addr_transform(MN);
+ crb_addr_transform(MS);
+ crb_addr_transform(CAS2);
+ crb_addr_transform(CAS1);
+ crb_addr_transform(CAS0);
+ crb_addr_transform(CAM);
+ crb_addr_transform(C2C1);
+ crb_addr_transform(C2C0);
+ crb_addr_transform(SMB);
+}
+
+int netxen_init_firmware(struct netxen_adapter *adapter)
+{
+ u32 state = 0, loops = 0, err = 0;
+
+ /* Window 1 call */
+ state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
+
+ if (state == PHAN_INITIALIZE_ACK)
+ return 0;
+
+ while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
+ udelay(100);
+ /* Window 1 call */
+ state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
+
+ loops++;
+ }
+ if (loops >= 2000) {
+ printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
+ state);
+ err = -EIO;
+ return err;
+ }
+ /* Window 1 call */
+ writel(MPORT_MULTI_FUNCTION_MODE,
+ NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE));
+ writel(PHAN_INITIALIZE_ACK,
+ NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
+
+ return err;
+}
+
+#define NETXEN_ADDR_LIMIT 0xffffffffULL
+
+void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
+ struct pci_dev **used_dev)
+{
+ void *addr;
+
+ addr = pci_alloc_consistent(pdev, sz, ptr);
+ if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) {
+ *used_dev = pdev;
+ return addr;
+ }
+ pci_free_consistent(pdev, sz, addr, *ptr);
+ addr = pci_alloc_consistent(NULL, sz, ptr);
+ *used_dev = NULL;
+ return addr;
+}
+
+void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
+{
+ int ctxid, ring;
+ u32 i;
+ u32 num_rx_bufs = 0;
+ struct netxen_rcv_desc_ctx *rcv_desc;
+
+ DPRINTK(INFO, "initializing some queues: %p\n", adapter);
+ for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
+ for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
+ struct netxen_rx_buffer *rx_buf;
+ rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring];
+ rcv_desc->rcv_free = rcv_desc->max_rx_desc_count;
+ rcv_desc->begin_alloc = 0;
+ rx_buf = rcv_desc->rx_buf_arr;
+ num_rx_bufs = rcv_desc->max_rx_desc_count;
+ /*
+ * Now go through all of them, set reference handles
+ * and put them in the queues.
+ */
+ for (i = 0; i < num_rx_bufs; i++) {
+ rx_buf->ref_handle = i;
+ rx_buf->state = NETXEN_BUFFER_FREE;
+ DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:"
+ "%p\n", ctxid, i, rx_buf);
+ rx_buf++;
+ }
+ }
+ }
+}
+
+void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
+{
+ int ports = 0;
+ struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
+
+ if (netxen_nic_get_board_info(adapter) != 0)
+ printk("%s: Error getting board config info.\n",
+ netxen_nic_driver_name);
+ get_brd_port_by_type(board_info->board_type, &ports);
+ if (ports == 0)
+ printk(KERN_ERR "%s: Unknown board type\n",
+ netxen_nic_driver_name);
+ adapter->ahw.max_ports = ports;
+}
+
+void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
+{
+ switch (adapter->ahw.board_type) {
+ case NETXEN_NIC_GBE:
+ adapter->enable_phy_interrupts =
+ netxen_niu_gbe_enable_phy_interrupts;
+ adapter->disable_phy_interrupts =
+ netxen_niu_gbe_disable_phy_interrupts;
+ adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
+ adapter->macaddr_set = netxen_niu_macaddr_set;
+ adapter->set_mtu = netxen_nic_set_mtu_gb;
+ adapter->set_promisc = netxen_niu_set_promiscuous_mode;
+ adapter->unset_promisc = netxen_niu_set_promiscuous_mode;
+ adapter->phy_read = netxen_niu_gbe_phy_read;
+ adapter->phy_write = netxen_niu_gbe_phy_write;
+ adapter->init_niu = netxen_nic_init_niu_gb;
+ adapter->stop_port = netxen_niu_disable_gbe_port;
+ break;
+
+ case NETXEN_NIC_XGBE:
+ adapter->enable_phy_interrupts =
+ netxen_niu_xgbe_enable_phy_interrupts;
+ adapter->disable_phy_interrupts =
+ netxen_niu_xgbe_disable_phy_interrupts;
+ adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
+ adapter->macaddr_set = netxen_niu_xg_macaddr_set;
+ adapter->set_mtu = netxen_nic_set_mtu_xgb;
+ adapter->init_port = netxen_niu_xg_init_port;
+ adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
+ adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
+ adapter->stop_port = netxen_niu_disable_xg_port;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*
+ * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
+ * address to external PCI CRB address.
+ */
+u32 netxen_decode_crb_addr(u32 addr)
+{
+ int i;
+ u32 base_addr, offset, pci_base;
+
+ crb_addr_transform_setup();
+
+ pci_base = NETXEN_ADDR_ERROR;
+ base_addr = addr & 0xfff00000;
+ offset = addr & 0x000fffff;
+
+ for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
+ if (crb_addr_xform[i] == base_addr) {
+ pci_base = i << 20;
+ break;
+ }
+ }
+ if (pci_base == NETXEN_ADDR_ERROR)
+ return pci_base;
+ else
+ return (pci_base + offset);
+}
+
+static long rom_max_timeout = 100;
+static long rom_lock_timeout = 10000;
+static long rom_write_timeout = 700;
+
+static inline int rom_lock(struct netxen_adapter *adapter)
+{
+ int iter;
+ u32 done = 0;
+ int timeout = 0;
+
+ while (!done) {
+ /* acquire semaphore2 from PCI HW block */
+ netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
+ &done);
+ if (done == 1)
+ break;
+ if (timeout >= rom_lock_timeout)
+ return -EIO;
+
+ timeout++;
+ /*
+ * Yield CPU
+ */
+ if (!in_atomic())
+ schedule();
+ else {
+ for (iter = 0; iter < 20; iter++)
+ cpu_relax(); /*This a nop instr on i386 */
+ }
+ }
+ netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
+ return 0;
+}
+
+int netxen_wait_rom_done(struct netxen_adapter *adapter)
+{
+ long timeout = 0;
+ long done = 0;
+
+ while (done == 0) {
+ done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
+ done &= 2;
+ timeout++;
+ if (timeout >= rom_max_timeout) {
+ printk("Timeout reached waiting for rom done");
+ return -EIO;
+ }
+ }
+ return 0;
+}
+
+static inline int netxen_rom_wren(struct netxen_adapter *adapter)
+{
+ /* Set write enable latch in ROM status register */
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
+ M25P_INSTR_WREN);
+ if (netxen_wait_rom_done(adapter)) {
+ return -1;
+ }
+ return 0;
+}
+
+static inline unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
+ unsigned int addr)
+{
+ unsigned int data = 0xdeaddead;
+ data = netxen_nic_reg_read(adapter, addr);
+ return data;
+}
+
+static inline int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
+{
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
+ M25P_INSTR_RDSR);
+ if (netxen_wait_rom_done(adapter)) {
+ return -1;
+ }
+ return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
+}
+
+static inline void netxen_rom_unlock(struct netxen_adapter *adapter)
+{
+ u32 val;
+
+ /* release semaphore2 */
+ netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
+
+}
+
+int netxen_rom_wip_poll(struct netxen_adapter *adapter)
+{
+ long timeout = 0;
+ long wip = 1;
+ int val;
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
+ while (wip != 0) {
+ val = netxen_do_rom_rdsr(adapter);
+ wip = val & 1;
+ timeout++;
+ if (timeout > rom_max_timeout) {
+ return -1;
+ }
+ }
+ return 0;
+}
+
+static inline int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
+ int data)
+{
+ if (netxen_rom_wren(adapter)) {
+ return -1;
+ }
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
+ M25P_INSTR_PP);
+ if (netxen_wait_rom_done(adapter)) {
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
+ return -1;
+ }
+
+ return netxen_rom_wip_poll(adapter);
+}
+
+static inline int
+do_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
+{
+ if (jiffies > (last_schedule_time + (8 * HZ))) {
+ last_schedule_time = jiffies;
+ schedule();
+ }
+
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
+ udelay(100); /* prevent bursting on CRB */
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
+ if (netxen_wait_rom_done(adapter)) {
+ printk("Error waiting for rom done\n");
+ return -EIO;
+ }
+ /* reset abyte_cnt and dummy_byte_cnt */
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
+ udelay(100); /* prevent bursting on CRB */
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
+
+ *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
+ return 0;
+}
+
+static inline int
+do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
+ u8 *bytes, size_t size)
+{
+ int addridx;
+ int ret = 0;
+
+ for (addridx = addr; addridx < (addr + size); addridx += 4) {
+ ret = do_rom_fast_read(adapter, addridx, (int *)bytes);
+ if (ret != 0)
+ break;
+ *(int *)bytes = cpu_to_le32(*(int *)bytes);
+ bytes += 4;
+ }
+
+ return ret;
+}
+
+int
+netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
+ u8 *bytes, size_t size)
+{
+ int ret;
+
+ ret = rom_lock(adapter);
+ if (ret < 0)
+ return ret;
+
+ ret = do_rom_fast_read_words(adapter, addr, bytes, size);
+
+ netxen_rom_unlock(adapter);
+ return ret;
+}
+
+int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
+{
+ int ret;
+
+ if (rom_lock(adapter) != 0)
+ return -EIO;
+
+ ret = do_rom_fast_read(adapter, addr, valp);
+ netxen_rom_unlock(adapter);
+ return ret;
+}
+
+int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
+{
+ int ret = 0;
+
+ if (rom_lock(adapter) != 0) {
+ return -1;
+ }
+ ret = do_rom_fast_write(adapter, addr, data);
+ netxen_rom_unlock(adapter);
+ return ret;
+}
+
+static inline int do_rom_fast_write_words(struct netxen_adapter *adapter,
+ int addr, u8 *bytes, size_t size)
+{
+ int addridx = addr;
+ int ret = 0;
+
+ while (addridx < (addr + size)) {
+ int last_attempt = 0;
+ int timeout = 0;
+ int data;
+
+ data = le32_to_cpu((*(u32*)bytes));
+ ret = do_rom_fast_write(adapter, addridx, data);
+ if (ret < 0)
+ return ret;
+
+ while(1) {
+ int data1;
+
+ ret = do_rom_fast_read(adapter, addridx, &data1);
+ if (ret < 0)
+ return ret;
+
+ if (data1 == data)
+ break;
+
+ if (timeout++ >= rom_write_timeout) {
+ if (last_attempt++ < 4) {
+ ret = do_rom_fast_write(adapter,
+ addridx, data);
+ if (ret < 0)
+ return ret;
+ }
+ else {
+ printk(KERN_INFO "Data write did not "
+ "succeed at address 0x%x\n", addridx);
+ break;
+ }
+ }
+ }
+
+ bytes += 4;
+ addridx += 4;
+ }
+
+ return ret;
+}
+
+int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
+ u8 *bytes, size_t size)
+{
+ int ret = 0;
+
+ ret = rom_lock(adapter);
+ if (ret < 0)
+ return ret;
+
+ ret = do_rom_fast_write_words(adapter, addr, bytes, size);
+ netxen_rom_unlock(adapter);
+
+ return ret;
+}
+
+int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
+{
+ int ret;
+
+ ret = netxen_rom_wren(adapter);
+ if (ret < 0)
+ return ret;
+
+ netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
+
+ ret = netxen_wait_rom_done(adapter);
+ if (ret < 0)
+ return ret;
+
+ return netxen_rom_wip_poll(adapter);
+}
+
+int netxen_rom_rdsr(struct netxen_adapter *adapter)
+{
+ int ret;
+
+ ret = rom_lock(adapter);
+ if (ret < 0)
+ return ret;
+
+ ret = netxen_do_rom_rdsr(adapter);
+ netxen_rom_unlock(adapter);
+ return ret;
+}
+
+int netxen_backup_crbinit(struct netxen_adapter *adapter)
+{
+ int ret = FLASH_SUCCESS;
+ int val;
+ char *buffer = kmalloc(FLASH_SECTOR_SIZE, GFP_KERNEL);
+
+ if (!buffer)
+ return -ENOMEM;
+ /* unlock sector 63 */
+ val = netxen_rom_rdsr(adapter);
+ val = val & 0xe3;
+ ret = netxen_rom_wrsr(adapter, val);
+ if (ret != FLASH_SUCCESS)
+ goto out_kfree;
+
+ ret = netxen_rom_wip_poll(adapter);
+ if (ret != FLASH_SUCCESS)
+ goto out_kfree;
+
+ /* copy sector 0 to sector 63 */
+ ret = netxen_rom_fast_read_words(adapter, CRBINIT_START,
+ buffer, FLASH_SECTOR_SIZE);
+ if (ret != FLASH_SUCCESS)
+ goto out_kfree;
+
+ ret = netxen_rom_fast_write_words(adapter, FIXED_START,
+ buffer, FLASH_SECTOR_SIZE);
+ if (ret != FLASH_SUCCESS)
+ goto out_kfree;
+
+ /* lock sector 63 */
+ val = netxen_rom_rdsr(adapter);
+ if (!(val & 0x8)) {
+ val |= (0x1 << 2);
+ /* lock sector 63 */
+ if (netxen_rom_wrsr(adapter, val) == 0) {
+ ret = netxen_rom_wip_poll(adapter);
+ if (ret != FLASH_SUCCESS)
+ goto out_kfree;
+
+ /* lock SR writes */
+ ret = netxen_rom_wip_poll(adapter);
+ if (ret != FLASH_SUCCESS)
+ goto out_kfree;
+ }
+ }
+
+out_kfree:
+ kfree(buffer);
+ return ret;
+}
+
+int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
+{
+ netxen_rom_wren(adapter);
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
+ M25P_INSTR_SE);
+ if (netxen_wait_rom_done(adapter)) {
+ netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
+ return -1;
+ }
+ return netxen_rom_wip_poll(adapter);
+}
+
+void check_erased_flash(struct netxen_adapter *adapter, int addr)
+{
+ int i;
+ int val;
+ int count = 0, erased_errors = 0;
+ int range;
+
+ range = (addr == USER_START) ? FIXED_START : addr + FLASH_SECTOR_SIZE;
+
+ for (i = addr; i < range; i += 4) {
+ netxen_rom_fast_read(adapter, i, &val);
+ if (val != 0xffffffff)
+ erased_errors++;
+ count++;
+ }
+
+ if (erased_errors)
+ printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
+ "for sector address: %x\n", erased_errors, count, addr);
+}
+
+int netxen_rom_se(struct netxen_adapter *adapter, int addr)
+{
+ int ret = 0;
+ if (rom_lock(adapter) != 0) {
+ return -1;
+ }
+ ret = netxen_do_rom_se(adapter, addr);
+ netxen_rom_unlock(adapter);
+ msleep(30);
+ check_erased_flash(adapter, addr);
+
+ return ret;
+}
+
+int
+netxen_flash_erase_sections(struct netxen_adapter *adapter, int start, int end)
+{
+ int ret = FLASH_SUCCESS;
+ int i;
+
+ for (i = start; i < end; i++) {
+ ret = netxen_rom_se(adapter, i * FLASH_SECTOR_SIZE);
+ if (ret)
+ break;
+ ret = netxen_rom_wip_poll(adapter);
+ if (ret < 0)
+ return ret;
+ }
+
+ return ret;
+}
+
+int
+netxen_flash_erase_secondary(struct netxen_adapter *adapter)
+{
+ int ret = FLASH_SUCCESS;
+ int start, end;
+
+ start = SECONDARY_START / FLASH_SECTOR_SIZE;
+ end = USER_START / FLASH_SECTOR_SIZE;
+ ret = netxen_flash_erase_sections(adapter, start, end);
+
+ return ret;
+}
+
+int
+netxen_flash_erase_primary(struct netxen_adapter *adapter)
+{
+ int ret = FLASH_SUCCESS;
+ int start, end;
+
+ start = PRIMARY_START / FLASH_SECTOR_SIZE;
+ end = SECONDARY_START / FLASH_SECTOR_SIZE;
+ ret = netxen_flash_erase_sections(adapter, start, end);
+
+ return ret;
+}
+
+void netxen_halt_pegs(struct netxen_adapter *adapter)
+{
+ netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
+ netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
+ netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
+ netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
+}
+
+int netxen_flash_unlock(struct netxen_adapter *adapter)
+{
+ int ret = 0;
+
+ ret = netxen_rom_wrsr(adapter, 0);
+ if (ret < 0)
+ return ret;
+
+ ret = netxen_rom_wren(adapter);
+ if (ret < 0)
+ return ret;
+
+ return ret;
+}
+
+#define NETXEN_BOARDTYPE 0x4008
+#define NETXEN_BOARDNUM 0x400c
+#define NETXEN_CHIPNUM 0x4010
+#define NETXEN_ROMBUS_RESET 0xFFFFFFFF
+#define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL
+#define NETXEN_ROM_FOUND_INIT 0x400
+
+int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
+{
+ int addr, val, status;
+ int n, i;
+ int init_delay = 0;
+ struct crb_addr_pair *buf;
+ u32 off;
+
+ /* resetall */
+ status = netxen_nic_get_board_info(adapter);
+ if (status)
+ printk("%s: netxen_pinit_from_rom: Error getting board info\n",
+ netxen_nic_driver_name);
+
+ netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
+ NETXEN_ROMBUS_RESET);
+
+ if (verbose) {
+ int val;
+ if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
+ printk("P2 ROM board type: 0x%08x\n", val);
+ else
+ printk("Could not read board type\n");
+ if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
+ printk("P2 ROM board num: 0x%08x\n", val);
+ else
+ printk("Could not read board number\n");
+ if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
+ printk("P2 ROM chip num: 0x%08x\n", val);
+ else
+ printk("Could not read chip number\n");
+ }
+
+ if (netxen_rom_fast_read(adapter, 0, &n) == 0
+ && (n & NETXEN_ROM_FIRST_BARRIER)) {
+ n &= ~NETXEN_ROM_ROUNDUP;
+ if (n < NETXEN_ROM_FOUND_INIT) {
+ if (verbose)
+ printk("%s: %d CRB init values found"
+ " in ROM.\n", netxen_nic_driver_name, n);
+ } else {
+ printk("%s:n=0x%x Error! NetXen card flash not"
+ " initialized.\n", __FUNCTION__, n);
+ return -EIO;
+ }
+ buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
+ if (buf == NULL) {
+ printk("%s: netxen_pinit_from_rom: Unable to calloc "
+ "memory.\n", netxen_nic_driver_name);
+ return -ENOMEM;
+ }
+ for (i = 0; i < n; i++) {
+ if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0
+ || netxen_rom_fast_read(adapter, 8 * i + 8,
+ &addr) != 0)
+ return -EIO;
+
+ buf[i].addr = addr;
+ buf[i].data = val;
+
+ if (verbose)
+ printk("%s: PCI: 0x%08x == 0x%08x\n",
+ netxen_nic_driver_name, (unsigned int)
+ netxen_decode_crb_addr(addr), val);
+ }
+ for (i = 0; i < n; i++) {
+
+ off = netxen_decode_crb_addr(buf[i].addr);
+ if (off == NETXEN_ADDR_ERROR) {
+ printk(KERN_ERR"CRB init value out of range %x\n",
+ buf[i].addr);
+ continue;
+ }
+ off += NETXEN_PCI_CRBSPACE;
+ /* skipping cold reboot MAGIC */
+ if (off == NETXEN_CAM_RAM(0x1fc))
+ continue;
+
+ /* After writing this register, HW needs time for CRB */
+ /* to quiet down (else crb_window returns 0xffffffff) */
+ if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
+ init_delay = 1;
+ /* hold xdma in reset also */
+ buf[i].data = NETXEN_NIC_XDMA_RESET;
+ }
+
+ if (ADDR_IN_WINDOW1(off)) {
+ writel(buf[i].data,
+ NETXEN_CRB_NORMALIZE(adapter, off));
+ } else {
+ netxen_nic_pci_change_crbwindow(adapter, 0);
+ writel(buf[i].data,
+ pci_base_offset(adapter, off));
+
+ netxen_nic_pci_change_crbwindow(adapter, 1);
+ }
+ if (init_delay == 1) {
+ ssleep(1);
+ init_delay = 0;
+ }
+ msleep(1);
+ }
+ kfree(buf);
+
+ /* disable_peg_cache_all */
+
+ /* unreset_net_cache */
+ netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val,
+ 4);
+ netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
+ (val & 0xffffff0f));
+ /* p2dn replyCount */
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
+ /* disable_peg_cache 0 */
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_CRB_PEG_NET_D + 0x4c, 8);
+ /* disable_peg_cache 1 */
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_CRB_PEG_NET_I + 0x4c, 8);
+
+ /* peg_clr_all */
+
+ /* peg_clr 0 */
+ netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8,
+ 0);
+ netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc,
+ 0);
+ /* peg_clr 1 */
+ netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8,
+ 0);
+ netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc,
+ 0);
+ /* peg_clr 2 */
+ netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8,
+ 0);
+ netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc,
+ 0);
+ /* peg_clr 3 */
+ netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8,
+ 0);
+ netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc,
+ 0);
+ }
+ return 0;
+}
+
+int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
+{
+ uint64_t addr;
+ uint32_t hi;
+ uint32_t lo;
+
+ adapter->dummy_dma.addr =
+ pci_alloc_consistent(adapter->ahw.pdev,
+ NETXEN_HOST_DUMMY_DMA_SIZE,
+ &adapter->dummy_dma.phys_addr);
+ if (adapter->dummy_dma.addr == NULL) {
+ printk("%s: ERROR: Could not allocate dummy DMA memory\n",
+ __FUNCTION__);
+ return -ENOMEM;
+ }
+
+ addr = (uint64_t) adapter->dummy_dma.phys_addr;
+ hi = (addr >> 32) & 0xffffffff;
+ lo = addr & 0xffffffff;
+
+ writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI));
+ writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO));
+
+ return 0;
+}
+
+void netxen_free_adapter_offload(struct netxen_adapter *adapter)
+{
+ if (adapter->dummy_dma.addr) {
+ writel(0, NETXEN_CRB_NORMALIZE(adapter,
+ CRB_HOST_DUMMY_BUF_ADDR_HI));
+ writel(0, NETXEN_CRB_NORMALIZE(adapter,
+ CRB_HOST_DUMMY_BUF_ADDR_LO));
+ pci_free_consistent(adapter->ahw.pdev,
+ NETXEN_HOST_DUMMY_DMA_SIZE,
+ adapter->dummy_dma.addr,
+ adapter->dummy_dma.phys_addr);
+ adapter->dummy_dma.addr = NULL;
+ }
+}
+
+void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
+{
+ u32 val = 0;
+ int loops = 0;
+
+ if (!pegtune_val) {
+ val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
+ while (val != PHAN_INITIALIZE_COMPLETE &&
+ val != PHAN_INITIALIZE_ACK && loops < 200000) {
+ udelay(100);
+ schedule();
+ val =
+ readl(NETXEN_CRB_NORMALIZE
+ (adapter, CRB_CMDPEG_STATE));
+ loops++;
+ }
+ if (val != PHAN_INITIALIZE_COMPLETE)
+ printk("WARNING: Initial boot wait loop failed...\n");
+ }
+}
+
+int netxen_nic_rx_has_work(struct netxen_adapter *adapter)
+{
+ int ctx;
+
+ for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
+ struct netxen_recv_context *recv_ctx =
+ &(adapter->recv_ctx[ctx]);
+ u32 consumer;
+ struct status_desc *desc_head;
+ struct status_desc *desc;
+
+ consumer = recv_ctx->status_rx_consumer;
+ desc_head = recv_ctx->rcv_status_desc_head;
+ desc = &desc_head[consumer];
+
+ if ((netxen_get_sts_owner(le64_to_cpu(desc->status_desc_data)))
+ & STATUS_OWNER_HOST)
+ return 1;
+ }
+
+ return 0;
+}
+
+static inline int netxen_nic_check_temp(struct netxen_adapter *adapter)
+{
+ struct net_device *netdev = adapter->netdev;
+ uint32_t temp, temp_state, temp_val;
+ int rv = 0;
+
+ temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE));
+
+ temp_state = nx_get_temp_state(temp);
+ temp_val = nx_get_temp_val(temp);
+
+ if (temp_state == NX_TEMP_PANIC) {
+ printk(KERN_ALERT
+ "%s: Device temperature %d degrees C exceeds"
+ " maximum allowed. Hardware has been shut down.\n",
+ netxen_nic_driver_name, temp_val);
+
+ netif_carrier_off(netdev);
+ netif_stop_queue(netdev);
+ rv = 1;
+ } else if (temp_state == NX_TEMP_WARN) {
+ if (adapter->temp == NX_TEMP_NORMAL) {
+ printk(KERN_ALERT
+ "%s: Device temperature %d degrees C "
+ "exceeds operating range."
+ " Immediate action needed.\n",
+ netxen_nic_driver_name, temp_val);
+ }
+ } else {
+ if (adapter->temp == NX_TEMP_WARN) {
+ printk(KERN_INFO
+ "%s: Device temperature is now %d degrees C"
+ " in normal range.\n", netxen_nic_driver_name,
+ temp_val);
+ }
+ }
+ adapter->temp = temp_state;
+ return rv;
+}
+
+void netxen_watchdog_task(unsigned long adaptid)
+{
+ struct net_device *netdev;
+ struct netxen_adapter *adapter = (struct netxen_adapter *)adaptid;
+
+ if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter))
+ return;
+
+ netdev = adapter->netdev;
+ if ((netif_running(netdev)) && !netif_carrier_ok(netdev)) {
+ printk(KERN_INFO "%s port %d, %s carrier is now ok\n",
+ netxen_nic_driver_name, adapter->portnum, netdev->name);
+ netif_carrier_on(netdev);
+ }
+
+ if (netif_queue_stopped(netdev))
+ netif_wake_queue(netdev);
+
+ if (adapter->handle_phy_intr)
+ adapter->handle_phy_intr(adapter);
+ mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
+}
+
+/*
+ * netxen_process_rcv() send the received packet to the protocol stack.
+ * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
+ * invoke the routine to send more rx buffers to the Phantom...
+ */
+void
+netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
+ struct status_desc *desc)
+{
+ u64 status_desc = le64_to_cpu(desc->status_desc_data);
+ struct pci_dev *pdev = adapter->pdev;
+ struct net_device *netdev = adapter->netdev;
+ int index = netxen_get_sts_refhandle(status_desc);
+ struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
+ struct netxen_rx_buffer *buffer;
+ struct sk_buff *skb;
+ u32 length = netxen_get_sts_totallength(status_desc);
+ u32 desc_ctx;
+ struct netxen_rcv_desc_ctx *rcv_desc;
+ int ret;
+
+ desc_ctx = netxen_get_sts_type(status_desc);
+ if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
+ printk("%s: %s Bad Rcv descriptor ring\n",
+ netxen_nic_driver_name, netdev->name);
+ return;
+ }
+
+ rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
+ if (unlikely(index > rcv_desc->max_rx_desc_count)) {
+ DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
+ index, rcv_desc->max_rx_desc_count);
+ return;
+ }
+ buffer = &rcv_desc->rx_buf_arr[index];
+ if (desc_ctx == RCV_DESC_LRO_CTXID) {
+ buffer->lro_current_frags++;
+ if (netxen_get_sts_desc_lro_last_frag(desc)) {
+ buffer->lro_expected_frags =
+ netxen_get_sts_desc_lro_cnt(desc);
+ buffer->lro_length = length;
+ }
+ if (buffer->lro_current_frags != buffer->lro_expected_frags) {
+ if (buffer->lro_expected_frags != 0) {
+ printk("LRO: (refhandle:%x) recv frag."
+ "wait for last. flags: %x expected:%d"
+ "have:%d\n", index,
+ netxen_get_sts_desc_lro_last_frag(desc),
+ buffer->lro_expected_frags,
+ buffer->lro_current_frags);
+ }
+ return;
+ }
+ }
+
+ pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
+ PCI_DMA_FROMDEVICE);
+
+ skb = (struct sk_buff *)buffer->skb;
+
+ if (likely(netxen_get_sts_status(status_desc) == STATUS_CKSUM_OK)) {
+ adapter->stats.csummed++;
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ }
+ skb->dev = netdev;
+ if (desc_ctx == RCV_DESC_LRO_CTXID) {
+ /* True length was only available on the last pkt */
+ skb_put(skb, buffer->lro_length);
+ } else {
+ skb_put(skb, length);
+ }
+
+ skb->protocol = eth_type_trans(skb, netdev);
+
+ ret = netif_receive_skb(skb);
+
+ /*
+ * RH: Do we need these stats on a regular basis. Can we get it from
+ * Linux stats.
+ */
+ switch (ret) {
+ case NET_RX_SUCCESS:
+ adapter->stats.uphappy++;
+ break;
+
+ case NET_RX_CN_LOW:
+ adapter->stats.uplcong++;
+ break;
+
+ case NET_RX_CN_MOD:
+ adapter->stats.upmcong++;
+ break;
+
+ case NET_RX_CN_HIGH:
+ adapter->stats.uphcong++;
+ break;
+
+ case NET_RX_DROP:
+ adapter->stats.updropped++;
+ break;
+
+ default:
+ adapter->stats.updunno++;
+ break;
+ }
+
+ netdev->last_rx = jiffies;
+
+ rcv_desc->rcv_free++;
+ rcv_desc->rcv_pending--;
+
+ /*
+ * We just consumed one buffer so post a buffer.
+ */
+ buffer->skb = NULL;
+ buffer->state = NETXEN_BUFFER_FREE;
+ buffer->lro_current_frags = 0;
+ buffer->lro_expected_frags = 0;
+
+ adapter->stats.no_rcv++;
+ adapter->stats.rxbytes += length;
+}
+
+/* Process Receive status ring */
+u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
+{
+ struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
+ struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
+ struct status_desc *desc; /* used to read status desc here */
+ u32 consumer = recv_ctx->status_rx_consumer;
+ u32 producer = 0;
+ int count = 0, ring;
+
+ DPRINTK(INFO, "procesing receive\n");
+ /*
+ * we assume in this case that there is only one port and that is
+ * port #1...changes need to be done in firmware to indicate port
+ * number as part of the descriptor. This way we will be able to get
+ * the netdev which is associated with that device.
+ */
+ while (count < max) {
+ desc = &desc_head[consumer];
+ if (!
+ ((netxen_get_sts_owner(le64_to_cpu(desc->status_desc_data)))
+ & STATUS_OWNER_HOST)) {
+ DPRINTK(ERR, "desc %p ownedby %x\n", desc,
+ netxen_get_sts_owner(status_desc));
+ break;
+ }
+ netxen_process_rcv(adapter, ctxid, desc);
+ netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
+ consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
+ count++;
+ }
+ if (count) {
+ for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
+ netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
+ }
+ }
+
+ /* update the consumer index in phantom */
+ if (count) {
+ recv_ctx->status_rx_consumer = consumer;
+ recv_ctx->status_rx_producer = producer;
+
+ /* Window = 1 */
+ writel(consumer,
+ NETXEN_CRB_NORMALIZE(adapter,
+ recv_crb_registers[adapter->portnum].
+ crb_rcv_status_consumer));
+ }
+
+ return count;
+}
+
+/* Process Command status ring */
+int netxen_process_cmd_ring(unsigned long data)
+{
+ u32 last_consumer;
+ u32 consumer;
+ struct netxen_adapter *adapter = (struct netxen_adapter *)data;
+ int count1 = 0;
+ int count2 = 0;
+ struct netxen_cmd_buffer *buffer;
+ struct pci_dev *pdev;
+ struct netxen_skb_frag *frag;
+ u32 i;
+ struct sk_buff *skb = NULL;
+ int done;
+
+ spin_lock(&adapter->tx_lock);
+ last_consumer = adapter->last_cmd_consumer;
+ DPRINTK(INFO, "procesing xmit complete\n");
+ /* we assume in this case that there is only one port and that is
+ * port #1...changes need to be done in firmware to indicate port
+ * number as part of the descriptor. This way we will be able to get
+ * the netdev which is associated with that device.
+ */
+
+ consumer = le32_to_cpu(*(adapter->cmd_consumer));
+ if (last_consumer == consumer) { /* Ring is empty */
+ DPRINTK(INFO, "last_consumer %d == consumer %d\n",
+ last_consumer, consumer);
+ spin_unlock(&adapter->tx_lock);
+ return 1;
+ }
+
+ adapter->proc_cmd_buf_counter++;
+ /*
+ * Not needed - does not seem to be used anywhere.
+ * adapter->cmd_consumer = consumer;
+ */
+ spin_unlock(&adapter->tx_lock);
+
+ while ((last_consumer != consumer) && (count1 < MAX_STATUS_HANDLE)) {
+ buffer = &adapter->cmd_buf_arr[last_consumer];
+ pdev = adapter->pdev;
+ frag = &buffer->frag_array[0];
+ skb = buffer->skb;
+ if (skb && (cmpxchg(&buffer->skb, skb, 0) == skb)) {
+ pci_unmap_single(pdev, frag->dma, frag->length,
+ PCI_DMA_TODEVICE);
+ for (i = 1; i < buffer->frag_count; i++) {
+ DPRINTK(INFO, "getting fragment no %d\n", i);
+ frag++; /* Get the next frag */
+ pci_unmap_page(pdev, frag->dma, frag->length,
+ PCI_DMA_TODEVICE);
+ }
+
+ adapter->stats.skbfreed++;
+ dev_kfree_skb_any(skb);
+ skb = NULL;
+ } else if (adapter->proc_cmd_buf_counter == 1) {
+ adapter->stats.txnullskb++;
+ }
+ if (unlikely(netif_queue_stopped(adapter->netdev)
+ && netif_carrier_ok(adapter->netdev))
+ && ((jiffies - adapter->netdev->trans_start) >
+ adapter->netdev->watchdog_timeo)) {
+ SCHEDULE_WORK(&adapter->tx_timeout_task);
+ }
+
+ last_consumer = get_next_index(last_consumer,
+ adapter->max_tx_desc_count);
+ count1++;
+ }
+
+ count2 = 0;
+ spin_lock(&adapter->tx_lock);
+ if ((--adapter->proc_cmd_buf_counter) == 0) {
+ adapter->last_cmd_consumer = last_consumer;
+ while ((adapter->last_cmd_consumer != consumer)
+ && (count2 < MAX_STATUS_HANDLE)) {
+ buffer =
+ &adapter->cmd_buf_arr[adapter->last_cmd_consumer];
+ count2++;
+ if (buffer->skb)
+ break;
+ else
+ adapter->last_cmd_consumer =
+ get_next_index(adapter->last_cmd_consumer,
+ adapter->max_tx_desc_count);
+ }
+ }
+ if (count1 || count2) {
+ if (netif_queue_stopped(adapter->netdev)
+ && (adapter->flags & NETXEN_NETDEV_STATUS)) {
+ netif_wake_queue(adapter->netdev);
+ adapter->flags &= ~NETXEN_NETDEV_STATUS;
+ }
+ }
+ /*
+ * If everything is freed up to consumer then check if the ring is full
+ * If the ring is full then check if more needs to be freed and
+ * schedule the call back again.
+ *
+ * This happens when there are 2 CPUs. One could be freeing and the
+ * other filling it. If the ring is full when we get out of here and
+ * the card has already interrupted the host then the host can miss the
+ * interrupt.
+ *
+ * There is still a possible race condition and the host could miss an
+ * interrupt. The card has to take care of this.
+ */
+ if (adapter->last_cmd_consumer == consumer &&
+ (((adapter->cmd_producer + 1) %
+ adapter->max_tx_desc_count) == adapter->last_cmd_consumer)) {
+ consumer = le32_to_cpu(*(adapter->cmd_consumer));
+ }
+ done = (adapter->last_cmd_consumer == consumer);
+
+ spin_unlock(&adapter->tx_lock);
+ DPRINTK(INFO, "last consumer is %d in %s\n", last_consumer,
+ __FUNCTION__);
+ return (done);
+}
+
+/*
+ * netxen_post_rx_buffers puts buffer in the Phantom memory
+ */
+void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
+{
+ struct pci_dev *pdev = adapter->ahw.pdev;
+ struct sk_buff *skb;
+ struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
+ struct netxen_rcv_desc_ctx *rcv_desc = NULL;
+ uint producer;
+ struct rcv_desc *pdesc;
+ struct netxen_rx_buffer *buffer;
+ int count = 0;
+ int index = 0;
+ netxen_ctx_msg msg = 0;
+ dma_addr_t dma;
+
+ rcv_desc = &recv_ctx->rcv_desc[ringid];
+
+ producer = rcv_desc->producer;
+ index = rcv_desc->begin_alloc;
+ buffer = &rcv_desc->rx_buf_arr[index];
+ /* We can start writing rx descriptors into the phantom memory. */
+ while (buffer->state == NETXEN_BUFFER_FREE) {
+ skb = dev_alloc_skb(rcv_desc->skb_size);
+ if (unlikely(!skb)) {
+ /*
+ * TODO
+ * We need to schedule the posting of buffers to the pegs.
+ */
+ rcv_desc->begin_alloc = index;
+ DPRINTK(ERR, "netxen_post_rx_buffers: "
+ " allocated only %d buffers\n", count);
+ break;
+ }
+
+ count++; /* now there should be no failure */
+ pdesc = &rcv_desc->desc_head[producer];
+
+#if defined(XGB_DEBUG)
+ *(unsigned long *)(skb->head) = 0xc0debabe;
+ if (skb_is_nonlinear(skb)) {
+ printk("Allocated SKB @%p is nonlinear\n");
+ }
+#endif
+ skb_reserve(skb, 2);
+ /* This will be setup when we receive the
+ * buffer after it has been filled FSL TBD TBD
+ * skb->dev = netdev;
+ */
+ dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size,
+ PCI_DMA_FROMDEVICE);
+ pdesc->addr_buffer = cpu_to_le64(dma);
+ buffer->skb = skb;
+ buffer->state = NETXEN_BUFFER_BUSY;
+ buffer->dma = dma;
+ /* make a rcv descriptor */
+ pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
+ pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
+ DPRINTK(INFO, "done writing descripter\n");
+ producer =
+ get_next_index(producer, rcv_desc->max_rx_desc_count);
+ index = get_next_index(index, rcv_desc->max_rx_desc_count);
+ buffer = &rcv_desc->rx_buf_arr[index];
+ }
+ /* if we did allocate buffers, then write the count to Phantom */
+ if (count) {
+ rcv_desc->begin_alloc = index;
+ rcv_desc->rcv_pending += count;
+ rcv_desc->producer = producer;
+ if (rcv_desc->rcv_free >= 32) {
+ rcv_desc->rcv_free = 0;
+ /* Window = 1 */
+ writel((producer - 1) &
+ (rcv_desc->max_rx_desc_count - 1),
+ NETXEN_CRB_NORMALIZE(adapter,
+ recv_crb_registers[
+ adapter->portnum].
+ rcv_desc_crb[ringid].
+ crb_rcv_producer_offset));
+ /*
+ * Write a doorbell msg to tell phanmon of change in
+ * receive ring producer
+ */
+ netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
+ netxen_set_msg_privid(msg);
+ netxen_set_msg_count(msg,
+ ((producer -
+ 1) & (rcv_desc->
+ max_rx_desc_count - 1)));
+ netxen_set_msg_ctxid(msg, adapter->portnum);
+ netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
+ writel(msg,
+ DB_NORMALIZE(adapter,
+ NETXEN_RCV_PRODUCER_OFFSET));
+ }
+ }
+}
+
+void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, uint32_t ctx,
+ uint32_t ringid)
+{
+ struct pci_dev *pdev = adapter->ahw.pdev;
+ struct sk_buff *skb;
+ struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
+ struct netxen_rcv_desc_ctx *rcv_desc = NULL;
+ u32 producer;
+ struct rcv_desc *pdesc;
+ struct netxen_rx_buffer *buffer;
+ int count = 0;
+ int index = 0;
+
+ rcv_desc = &recv_ctx->rcv_desc[ringid];
+
+ producer = rcv_desc->producer;
+ index = rcv_desc->begin_alloc;
+ buffer = &rcv_desc->rx_buf_arr[index];
+ /* We can start writing rx descriptors into the phantom memory. */
+ while (buffer->state == NETXEN_BUFFER_FREE) {
+ skb = dev_alloc_skb(rcv_desc->skb_size);
+ if (unlikely(!skb)) {
+ /*
+ * We need to schedule the posting of buffers to the pegs.
+ */
+ rcv_desc->begin_alloc = index;
+ DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
+ " allocated only %d buffers\n", count);
+ break;
+ }
+ count++; /* now there should be no failure */
+ pdesc = &rcv_desc->desc_head[producer];
+ skb_reserve(skb, 2);
+ /*
+ * This will be setup when we receive the
+ * buffer after it has been filled
+ * skb->dev = netdev;
+ */
+ buffer->skb = skb;
+ buffer->state = NETXEN_BUFFER_BUSY;
+ buffer->dma = pci_map_single(pdev, skb->data,
+ rcv_desc->dma_size,
+ PCI_DMA_FROMDEVICE);
+
+ /* make a rcv descriptor */
+ pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
+ pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
+ pdesc->addr_buffer = cpu_to_le64(buffer->dma);
+ DPRINTK(INFO, "done writing descripter\n");
+ producer =
+ get_next_index(producer, rcv_desc->max_rx_desc_count);
+ index = get_next_index(index, rcv_desc->max_rx_desc_count);
+ buffer = &rcv_desc->rx_buf_arr[index];
+ }
+
+ /* if we did allocate buffers, then write the count to Phantom */
+ if (count) {
+ rcv_desc->begin_alloc = index;
+ rcv_desc->rcv_pending += count;
+ rcv_desc->producer = producer;
+ if (rcv_desc->rcv_free >= 32) {
+ rcv_desc->rcv_free = 0;
+ /* Window = 1 */
+ writel((producer - 1) &
+ (rcv_desc->max_rx_desc_count - 1),
+ NETXEN_CRB_NORMALIZE(adapter,
+ recv_crb_registers[
+ adapter->portnum].
+ rcv_desc_crb[ringid].
+ crb_rcv_producer_offset));
+ wmb();
+ }
+ }
+}
+
+int netxen_nic_tx_has_work(struct netxen_adapter *adapter)
+{
+ if (find_diff_among(adapter->last_cmd_consumer,
+ adapter->cmd_producer,
+ adapter->max_tx_desc_count) > 0)
+ return 1;
+
+ return 0;
+}
+
+
+void netxen_nic_clear_stats(struct netxen_adapter *adapter)
+{
+ memset(&adapter->stats, 0, sizeof(adapter->stats));
+ return;
+}
+
--- linux-2.6.18.x86_64/drivers/net/netxen/Makefile.rhel5
+++ linux-2.6.18.x86_64/drivers/net/netxen/Makefile
@@ -0,0 +1,36 @@
+# Copyright (C) 2003 - 2006 NetXen, Inc.
+# All rights reserved.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# as published by the Free Software Foundation; either version 2
+# of the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston,
+# MA 02111-1307, USA.
+#
+# The full GNU General Public License is included in this distribution
+# in the file called LICENSE.
+#
+# Contact Information:
+# info@netxen.com
+# NetXen,
+# 3965 Freedom Circle, Fourth floor,
+# Santa Clara, CA 95054
+#
+# Makefile for the NetXen NIC Driver
+#
+
+
+obj-$(CONFIG_NETXEN_NIC) := netxen_nic.o
+
+netxen_nic-objs := netxen_nic_hw.o netxen_nic_main.o netxen_nic_init.o \
+ netxen_nic_isr.o netxen_nic_ethtool.o netxen_nic_niu.o
+
--- linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic.h.rhel5
+++ linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic.h
@@ -0,0 +1,1158 @@
+/*
+ * Copyright (C) 2003 - 2006 NetXen, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
+ * MA 02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.
+ *
+ * Contact Information:
+ * info@netxen.com
+ * NetXen,
+ * 3965 Freedom Circle, Fourth floor,
+ * Santa Clara, CA 95054
+ */
+
+#ifndef _NETXEN_NIC_H_
+#define _NETXEN_NIC_H_
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/compiler.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ip.h>
+#include <linux/in.h>
+#include <linux/tcp.h>
+#include <linux/skbuff.h>
+#include <linux/version.h>
+
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/interrupt.h>
+#include <linux/timer.h>
+
+#include <linux/mm.h>
+#include <linux/mman.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+
+#include "netxen_nic_hw.h"
+
+#define _NETXEN_NIC_LINUX_MAJOR 3
+#define _NETXEN_NIC_LINUX_MINOR 4
+#define _NETXEN_NIC_LINUX_SUBVERSION 2
+#define NETXEN_NIC_LINUX_VERSIONID "3.4.2"
+
+#define NUM_FLASH_SECTORS (64)
+#define FLASH_SECTOR_SIZE (64 * 1024)
+#define FLASH_TOTAL_SIZE (NUM_FLASH_SECTORS * FLASH_SECTOR_SIZE)
+
+#define PHAN_VENDOR_ID 0x4040
+
+#define RCV_DESC_RINGSIZE \
+ (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
+#define STATUS_DESC_RINGSIZE \
+ (sizeof(struct status_desc)* adapter->max_rx_desc_count)
+#define LRO_DESC_RINGSIZE \
+ (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
+#define TX_RINGSIZE \
+ (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
+#define RCV_BUFFSIZE \
+ (sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count)
+#define find_diff_among(a,b,range) ((a)<=(b)?((b)-(a)):((b)+(range)-(a)))
+
+#define NETXEN_NETDEV_STATUS 0x1
+#define NETXEN_RCV_PRODUCER_OFFSET 0
+#define NETXEN_RCV_PEG_DB_ID 2
+#define NETXEN_HOST_DUMMY_DMA_SIZE 1024
+#define FLASH_SUCCESS 0
+
+#define ADDR_IN_WINDOW1(off) \
+ ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
+/*
+ * In netxen_nic_down(), we must wait for any pending callback requests into
+ * netxen_watchdog_task() to complete; eg otherwise the watchdog_timer could be
+ * reenabled right after it is deleted in netxen_nic_down(). FLUSH_SCHEDULED_WORK()
+ * does this synchronization.
+ *
+ * Normally, schedule_work()/flush_scheduled_work() could have worked, but
+ * netxen_nic_close() is invoked with kernel rtnl lock held. netif_carrier_off()
+ * call in netxen_nic_close() triggers a schedule_work(&linkwatch_work), and a
+ * subsequent call to flush_scheduled_work() in netxen_nic_down() would cause
+ * linkwatch_event() to be executed which also attempts to acquire the rtnl
+ * lock thus causing a deadlock.
+ */
+
+#define SCHEDULE_WORK(tp) queue_work(netxen_workq, tp)
+#define FLUSH_SCHEDULED_WORK() flush_workqueue(netxen_workq)
+extern struct workqueue_struct *netxen_workq;
+
+/*
+ * normalize a 64MB crb address to 32MB PCI window
+ * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
+ */
+#define NETXEN_CRB_NORMAL(reg) \
+ ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
+
+#define NETXEN_CRB_NORMALIZE(adapter, reg) \
+ pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
+
+#define DB_NORMALIZE(adapter, off) \
+ (adapter->ahw.db_base + (off))
+
+#define NX_P2_C0 0x24
+#define NX_P2_C1 0x25
+
+#define FIRST_PAGE_GROUP_START 0
+#define FIRST_PAGE_GROUP_END 0x100000
+
+#define SECOND_PAGE_GROUP_START 0x6000000
+#define SECOND_PAGE_GROUP_END 0x68BC000
+
+#define THIRD_PAGE_GROUP_START 0x70E4000
+#define THIRD_PAGE_GROUP_END 0x8000000
+
+#define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
+#define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
+#define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
+
+#define MAX_RX_BUFFER_LENGTH 1760
+#define MAX_RX_JUMBO_BUFFER_LENGTH 8062
+#define MAX_RX_LRO_BUFFER_LENGTH ((48*1024)-512)
+#define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
+#define RX_JUMBO_DMA_MAP_LEN \
+ (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
+#define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
+#define NETXEN_ROM_ROUNDUP 0x80000000ULL
+
+/*
+ * Maximum number of ring contexts
+ */
+#define MAX_RING_CTX 1
+
+/* Opcodes to be used with the commands */
+enum {
+ TX_ETHER_PKT = 0x01,
+/* The following opcodes are for IP checksum */
+ TX_TCP_PKT,
+ TX_UDP_PKT,
+ TX_IP_PKT,
+ TX_TCP_LSO,
+ TX_IPSEC,
+ TX_IPSEC_CMD
+};
+
+/* The following opcodes are for internal consumption. */
+#define NETXEN_CONTROL_OP 0x10
+#define PEGNET_REQUEST 0x11
+
+#define MAX_NUM_CARDS 4
+
+#define MAX_BUFFERS_PER_CMD 32
+
+/*
+ * Following are the states of the Phantom. Phantom will set them and
+ * Host will read to check if the fields are correct.
+ */
+#define PHAN_INITIALIZE_START 0xff00
+#define PHAN_INITIALIZE_FAILED 0xffff
+#define PHAN_INITIALIZE_COMPLETE 0xff01
+
+/* Host writes the following to notify that it has done the init-handshake */
+#define PHAN_INITIALIZE_ACK 0xf00f
+
+#define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */
+
+/* descriptor types */
+#define RCV_DESC_NORMAL 0x01
+#define RCV_DESC_JUMBO 0x02
+#define RCV_DESC_LRO 0x04
+#define RCV_DESC_NORMAL_CTXID 0
+#define RCV_DESC_JUMBO_CTXID 1
+#define RCV_DESC_LRO_CTXID 2
+
+#define RCV_DESC_TYPE(ID) \
+ ((ID == RCV_DESC_JUMBO_CTXID) \
+ ? RCV_DESC_JUMBO \
+ : ((ID == RCV_DESC_LRO_CTXID) \
+ ? RCV_DESC_LRO : \
+ (RCV_DESC_NORMAL)))
+
+#define MAX_CMD_DESCRIPTORS 1024
+#define MAX_RCV_DESCRIPTORS 16384
+#define MAX_CMD_DESCRIPTORS_HOST (MAX_CMD_DESCRIPTORS / 4)
+#define MAX_RCV_DESCRIPTORS_1G (MAX_RCV_DESCRIPTORS / 4)
+#define MAX_JUMBO_RCV_DESCRIPTORS 1024
+#define MAX_LRO_RCV_DESCRIPTORS 64
+#define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
+#define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
+#define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
+#define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
+#define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
+#define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
+ MAX_LRO_RCV_DESCRIPTORS)
+#define MIN_TX_COUNT 4096
+#define MIN_RX_COUNT 4096
+#define NETXEN_CTX_SIGNATURE 0xdee0
+#define NETXEN_RCV_PRODUCER(ringid) (ringid)
+#define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
+
+#define PHAN_PEG_RCV_INITIALIZED 0xff01
+#define PHAN_PEG_RCV_START_INITIALIZE 0xff00
+
+#define get_next_index(index, length) \
+ (((index) + 1) & ((length) - 1))
+
+#define get_index_range(index,length,count) \
+ (((index) + (count)) & ((length) - 1))
+
+#define MPORT_SINGLE_FUNCTION_MODE 0x1111
+#define MPORT_MULTI_FUNCTION_MODE 0x2222
+
+#include "netxen_nic_phan_reg.h"
+extern unsigned long long netxen_dma_mask;
+extern unsigned long last_schedule_time;
+
+/*
+ * NetXen host-peg signal message structure
+ *
+ * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
+ * Bit 2 : priv_id => must be 1
+ * Bit 3-17 : count => for doorbell
+ * Bit 18-27 : ctx_id => Context id
+ * Bit 28-31 : opcode
+ */
+
+typedef u32 netxen_ctx_msg;
+
+#define netxen_set_msg_peg_id(config_word, val) \
+ ((config_word) &= ~3, (config_word) |= val & 3)
+#define netxen_set_msg_privid(config_word) \
+ ((config_word) |= 1 << 2)
+#define netxen_set_msg_count(config_word, val) \
+ ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
+#define netxen_set_msg_ctxid(config_word, val) \
+ ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
+#define netxen_set_msg_opcode(config_word, val) \
+ ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
+
+struct netxen_rcv_context {
+ __le64 rcv_ring_addr;
+ __le32 rcv_ring_size;
+ __le32 rsrvd;
+};
+
+struct netxen_ring_ctx {
+
+ /* one command ring */
+ __le64 cmd_consumer_offset;
+ __le64 cmd_ring_addr;
+ __le32 cmd_ring_size;
+ __le32 rsrvd;
+
+ /* three receive rings */
+ struct netxen_rcv_context rcv_ctx[3];
+
+ /* one status ring */
+ __le64 sts_ring_addr;
+ __le32 sts_ring_size;
+
+ __le32 ctx_id;
+} __attribute__ ((aligned(64)));
+
+/*
+ * Following data structures describe the descriptors that will be used.
+ * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
+ * we are doing LSO (above the 1500 size packet) only.
+ */
+
+/*
+ * The size of reference handle been changed to 16 bits to pass the MSS fields
+ * for the LSO packet
+ */
+
+#define FLAGS_CHECKSUM_ENABLED 0x01
+#define FLAGS_LSO_ENABLED 0x02
+#define FLAGS_IPSEC_SA_ADD 0x04
+#define FLAGS_IPSEC_SA_DELETE 0x08
+#define FLAGS_VLAN_TAGGED 0x10
+
+#define netxen_set_cmd_desc_port(cmd_desc, val) \
+ ((cmd_desc)->port_ctxid &= ~(0xf<<0), \
+ (cmd_desc)->port_ctxid |= (val & 0xf) << 0)
+#define netxen_set_cmd_desc_ctxid(cmd_desc, val) \
+ ((cmd_desc)->port_ctxid &= ~(0xf<<4), \
+ (cmd_desc)->port_ctxid |= (val & 0xf) << 4)
+
+#define netxen_set_cmd_desc_opcode(cmd_desc, val) \
+ ((cmd_desc)->flags_opcode &= ~(0x3f<<7), \
+ (cmd_desc)->flags_opcode |= (val & 0x3f)<<7)
+
+#define netxen_set_cmd_desc_num_of_buff(cmd_desc, val) \
+ ((cmd_desc)->num_of_buffers_total_length &= ~(0xff<<0), \
+ (cmd_desc)->num_of_buffers_total_length |= (val & 0xff)<<0)
+#define netxen_set_cmd_desc_totallength(cmd_desc, val) \
+ ((cmd_desc)->num_of_buffers_total_length &= ~(0xffffff<<8), \
+ (cmd_desc)->num_of_buffers_total_length |= (val & 0xffffff) <<8)
+
+#define netxen_get_cmd_desc_opcode(cmd_desc) \
+ (((cmd_desc)->flags_opcode >> 7) & 0x003F)
+#define netxen_get_cmd_desc_totallength(cmd_desc) \
+ (((cmd_desc)->num_of_buffers_total_length >> 8) & 0x0FFFFFF)
+
+struct cmd_desc_type0 {
+ u8 tcp_hdr_offset; /* For LSO only */
+ u8 ip_hdr_offset; /* For LSO only */
+ /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
+ __le16 flags_opcode;
+ /* Bit pattern: 0-7 total number of segments,
+ 8-31 Total size of the packet */
+ __le32 num_of_buffers_total_length;
+ union {
+ struct {
+ __le32 addr_low_part2;
+ __le32 addr_high_part2;
+ };
+ __le64 addr_buffer2;
+ };
+
+ __le16 reference_handle; /* changed to u16 to add mss */
+ __le16 mss; /* passed by NDIS_PACKET for LSO */
+ /* Bit pattern 0-3 port, 4-7 ctx id */
+ u8 port_ctxid;
+ u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
+ __le16 conn_id; /* IPSec offoad only */
+
+ union {
+ struct {
+ __le32 addr_low_part3;
+ __le32 addr_high_part3;
+ };
+ __le64 addr_buffer3;
+ };
+ union {
+ struct {
+ __le32 addr_low_part1;
+ __le32 addr_high_part1;
+ };
+ __le64 addr_buffer1;
+ };
+
+ __le16 buffer1_length;
+ __le16 buffer2_length;
+ __le16 buffer3_length;
+ __le16 buffer4_length;
+
+ union {
+ struct {
+ __le32 addr_low_part4;
+ __le32 addr_high_part4;
+ };
+ __le64 addr_buffer4;
+ };
+
+ __le64 unused;
+
+} __attribute__ ((aligned(64)));
+
+/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
+struct rcv_desc {
+ __le16 reference_handle;
+ __le16 reserved;
+ __le32 buffer_length; /* allocated buffer length (usually 2K) */
+ __le64 addr_buffer;
+};
+
+/* opcode field in status_desc */
+#define RCV_NIC_PKT (0xA)
+#define STATUS_NIC_PKT ((RCV_NIC_PKT) << 12)
+
+/* for status field in status_desc */
+#define STATUS_NEED_CKSUM (1)
+#define STATUS_CKSUM_OK (2)
+
+/* owner bits of status_desc */
+#define STATUS_OWNER_HOST (0x1)
+#define STATUS_OWNER_PHANTOM (0x2)
+
+#define NETXEN_PROT_IP (1)
+#define NETXEN_PROT_UNKNOWN (0)
+
+/* Note: sizeof(status_desc) should always be a mutliple of 2 */
+
+#define netxen_get_sts_desc_lro_cnt(status_desc) \
+ (((status_desc)->lro) & 0x7F)
+#define netxen_get_sts_desc_lro_last_frag(status_desc) \
+ ((((status_desc)->lro) >> 7) & 0x1)
+
+#define netxen_get_sts_status(status_desc) \
+ (((status_desc) >> 4) & 0x0F)
+#define netxen_get_sts_type(status_desc) \
+ (((status_desc) >> 8) & 0x0F)
+#define netxen_get_sts_totallength(status_desc) \
+ (((status_desc) >> 12) & 0xFFFF)
+#define netxen_get_sts_refhandle(status_desc) \
+ (((status_desc) >> 28) & 0xFFFF)
+
+#define netxen_get_sts_prot(status_desc) \
+ (((status_desc) >> 44) & 0x0F)
+#define netxen_get_sts_owner(status_desc) \
+ (((status_desc) >> 56) & 0x03)
+
+#define netxen_set_sts_owner(status_desc, val) { \
+ u64 value = le64_to_cpu((status_desc)->status_desc_data); \
+ value &= ~(0x3ULL << 56); \
+ value |= (u64)(((u64)(val) << 56) & (0x3ULL << 56)); \
+ (status_desc)->status_desc_data = cpu_to_le64(value); \
+}
+
+struct status_desc {
+ /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
+ 28-43 reference_handle, 44-47 protocol, 48-52 unused
+ 53-55 desc_cnt, 56-57 owner, 58-63 opcode
+ */
+ __le64 status_desc_data;
+ __le32 hash_value;
+ u8 hash_type;
+ u8 msg_type;
+ u8 unused;
+ /* Bit pattern: 0-6 lro_count indicates frag sequence,
+ 7 last_frag indicates last frag */
+ u8 lro;
+} __attribute__ ((aligned(16)));
+
+enum {
+ NETXEN_RCV_PEG_0 = 0,
+ NETXEN_RCV_PEG_1
+};
+/* The version of the main data structure */
+#define NETXEN_BDINFO_VERSION 1
+
+/* Magic number to let user know flash is programmed */
+#define NETXEN_BDINFO_MAGIC 0x12345678
+
+/* Max number of Gig ports on a Phantom board */
+#define NETXEN_MAX_PORTS 4
+
+typedef enum {
+ NETXEN_BRDTYPE_P1_BD = 0x0000,
+ NETXEN_BRDTYPE_P1_SB = 0x0001,
+ NETXEN_BRDTYPE_P1_SMAX = 0x0002,
+ NETXEN_BRDTYPE_P1_SOCK = 0x0003,
+
+ NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
+ NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
+ NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
+ NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
+ NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
+
+ NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
+ NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
+ NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f
+} netxen_brdtype_t;
+
+typedef enum {
+ NETXEN_BRDMFG_INVENTEC = 1
+} netxen_brdmfg;
+
+typedef enum {
+ MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
+ MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
+ MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
+ MEM_ORG_256Mbx4 = 0x3,
+ MEM_ORG_256Mbx8 = 0x4,
+ MEM_ORG_256Mbx16 = 0x5,
+ MEM_ORG_512Mbx4 = 0x6,
+ MEM_ORG_512Mbx8 = 0x7,
+ MEM_ORG_512Mbx16 = 0x8,
+ MEM_ORG_1Gbx4 = 0x9,
+ MEM_ORG_1Gbx8 = 0xa,
+ MEM_ORG_1Gbx16 = 0xb,
+ MEM_ORG_2Gbx4 = 0xc,
+ MEM_ORG_2Gbx8 = 0xd,
+ MEM_ORG_2Gbx16 = 0xe,
+ MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
+ MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
+} netxen_mn_mem_org_t;
+
+typedef enum {
+ MEM_ORG_512Kx36 = 0x0,
+ MEM_ORG_1Mx36 = 0x1,
+ MEM_ORG_2Mx36 = 0x2
+} netxen_sn_mem_org_t;
+
+typedef enum {
+ MEM_DEPTH_4MB = 0x1,
+ MEM_DEPTH_8MB = 0x2,
+ MEM_DEPTH_16MB = 0x3,
+ MEM_DEPTH_32MB = 0x4,
+ MEM_DEPTH_64MB = 0x5,
+ MEM_DEPTH_128MB = 0x6,
+ MEM_DEPTH_256MB = 0x7,
+ MEM_DEPTH_512MB = 0x8,
+ MEM_DEPTH_1GB = 0x9,
+ MEM_DEPTH_2GB = 0xa,
+ MEM_DEPTH_4GB = 0xb,
+ MEM_DEPTH_8GB = 0xc,
+ MEM_DEPTH_16GB = 0xd,
+ MEM_DEPTH_32GB = 0xe
+} netxen_mem_depth_t;
+
+struct netxen_board_info {
+ u32 header_version;
+
+ u32 board_mfg;
+ u32 board_type;
+ u32 board_num;
+ u32 chip_id;
+ u32 chip_minor;
+ u32 chip_major;
+ u32 chip_pkg;
+ u32 chip_lot;
+
+ u32 port_mask; /* available niu ports */
+ u32 peg_mask; /* available pegs */
+ u32 icache_ok; /* can we run with icache? */
+ u32 dcache_ok; /* can we run with dcache? */
+ u32 casper_ok;
+
+ u32 mac_addr_lo_0;
+ u32 mac_addr_lo_1;
+ u32 mac_addr_lo_2;
+ u32 mac_addr_lo_3;
+
+ /* MN-related config */
+ u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
+ u32 mn_sync_shift_cclk;
+ u32 mn_sync_shift_mclk;
+ u32 mn_wb_en;
+ u32 mn_crystal_freq; /* in MHz */
+ u32 mn_speed; /* in MHz */
+ u32 mn_org;
+ u32 mn_depth;
+ u32 mn_ranks_0; /* ranks per slot */
+ u32 mn_ranks_1; /* ranks per slot */
+ u32 mn_rd_latency_0;
+ u32 mn_rd_latency_1;
+ u32 mn_rd_latency_2;
+ u32 mn_rd_latency_3;
+ u32 mn_rd_latency_4;
+ u32 mn_rd_latency_5;
+ u32 mn_rd_latency_6;
+ u32 mn_rd_latency_7;
+ u32 mn_rd_latency_8;
+ u32 mn_dll_val[18];
+ u32 mn_mode_reg; /* MIU DDR Mode Register */
+ u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
+ u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
+ u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
+ u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
+
+ /* SN-related config */
+ u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
+ u32 sn_pt_mode; /* pass through mode */
+ u32 sn_ecc_en;
+ u32 sn_wb_en;
+ u32 sn_crystal_freq;
+ u32 sn_speed;
+ u32 sn_org;
+ u32 sn_depth;
+ u32 sn_dll_tap;
+ u32 sn_rd_latency;
+
+ u32 mac_addr_hi_0;
+ u32 mac_addr_hi_1;
+ u32 mac_addr_hi_2;
+ u32 mac_addr_hi_3;
+
+ u32 magic; /* indicates flash has been initialized */
+
+ u32 mn_rdimm;
+ u32 mn_dll_override;
+
+};
+
+#define FLASH_NUM_PORTS (4)
+
+struct netxen_flash_mac_addr {
+ u32 flash_addr[32];
+};
+
+struct netxen_user_old_info {
+ u8 flash_md5[16];
+ u8 crbinit_md5[16];
+ u8 brdcfg_md5[16];
+ /* bootloader */
+ u32 bootld_version;
+ u32 bootld_size;
+ u8 bootld_md5[16];
+ /* image */
+ u32 image_version;
+ u32 image_size;
+ u8 image_md5[16];
+ /* primary image status */
+ u32 primary_status;
+ u32 secondary_present;
+
+ /* MAC address , 4 ports */
+ struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
+};
+#define FLASH_NUM_MAC_PER_PORT 32
+struct netxen_user_info {
+ u8 flash_md5[16 * 64];
+ /* bootloader */
+ u32 bootld_version;
+ u32 bootld_size;
+ /* image */
+ u32 image_version;
+ u32 image_size;
+ /* primary image status */
+ u32 primary_status;
+ u32 secondary_present;
+
+ /* MAC address , 4 ports, 32 address per port */
+ u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
+ u32 sub_sys_id;
+ u8 serial_num[32];
+
+ /* Any user defined data */
+};
+
+/*
+ * Flash Layout - new format.
+ */
+struct netxen_new_user_info {
+ u8 flash_md5[16 * 64];
+ /* bootloader */
+ u32 bootld_version;
+ u32 bootld_size;
+ /* image */
+ u32 image_version;
+ u32 image_size;
+ /* primary image status */
+ u32 primary_status;
+ u32 secondary_present;
+
+ /* MAC address , 4 ports, 32 address per port */
+ u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
+ u32 sub_sys_id;
+ u8 serial_num[32];
+
+ /* Any user defined data */
+};
+
+#define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
+#define SECONDARY_IMAGE_ABSENT 0xffffffff
+#define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
+#define PRIMARY_IMAGE_BAD 0xffffffff
+
+/* Flash memory map */
+typedef enum {
+ CRBINIT_START = 0, /* Crbinit section */
+ BRDCFG_START = 0x4000, /* board config */
+ INITCODE_START = 0x6000, /* pegtune code */
+ BOOTLD_START = 0x10000, /* bootld */
+ IMAGE_START = 0x43000, /* compressed image */
+ SECONDARY_START = 0x200000, /* backup images */
+ PXE_START = 0x3E0000, /* user defined region */
+ USER_START = 0x3E8000, /* User defined region for new boards */
+ FIXED_START = 0x3F0000 /* backup of crbinit */
+} netxen_flash_map_t;
+
+#define USER_START_OLD PXE_START /* for backward compatibility */
+
+#define FLASH_START (CRBINIT_START)
+#define INIT_SECTOR (0)
+#define PRIMARY_START (BOOTLD_START)
+#define FLASH_CRBINIT_SIZE (0x4000)
+#define FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
+#define FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
+#define FLASH_SECONDARY_SIZE (USER_START-SECONDARY_START)
+#define NUM_PRIMARY_SECTORS (0x20)
+#define NUM_CONFIG_SECTORS (1)
+#define PFX "NetXen: "
+extern char netxen_nic_driver_name[];
+
+/* Note: Make sure to not call this before adapter->port is valid */
+#if !defined(NETXEN_DEBUG)
+#define DPRINTK(klevel, fmt, args...) do { \
+ } while (0)
+#else
+#define DPRINTK(klevel, fmt, args...) do { \
+ printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\
+ (adapter != NULL && adapter->netdev != NULL) ? \
+ adapter->netdev->name : NULL, \
+ ## args); } while(0)
+#endif
+
+/* Number of status descriptors to handle per interrupt */
+#define MAX_STATUS_HANDLE (128)
+
+/*
+ * netxen_skb_frag{} is to contain mapping info for each SG list. This
+ * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
+ */
+struct netxen_skb_frag {
+ u64 dma;
+ u32 length;
+};
+
+/* Following defines are for the state of the buffers */
+#define NETXEN_BUFFER_FREE 0
+#define NETXEN_BUFFER_BUSY 1
+
+/*
+ * There will be one netxen_buffer per skb packet. These will be
+ * used to save the dma info for pci_unmap_page()
+ */
+struct netxen_cmd_buffer {
+ struct sk_buff *skb;
+ struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
+ u32 total_length;
+ u32 mss;
+ u16 port;
+ u8 cmd;
+ u8 frag_count;
+ unsigned long time_stamp;
+ u32 state;
+};
+
+/* In rx_buffer, we do not need multiple fragments as is a single buffer */
+struct netxen_rx_buffer {
+ struct sk_buff *skb;
+ u64 dma;
+ u16 ref_handle;
+ u16 state;
+ u32 lro_expected_frags;
+ u32 lro_current_frags;
+ u32 lro_length;
+};
+
+/* Board types */
+#define NETXEN_NIC_GBE 0x01
+#define NETXEN_NIC_XGBE 0x02
+
+/*
+ * One hardware_context{} per adapter
+ * contains interrupt info as well shared hardware info.
+ */
+struct netxen_hardware_context {
+ struct pci_dev *pdev;
+ void __iomem *pci_base0;
+ void __iomem *pci_base1;
+ void __iomem *pci_base2;
+ unsigned long first_page_group_end;
+ unsigned long first_page_group_start;
+ void __iomem *db_base;
+ unsigned long db_len;
+
+ u8 revision_id;
+ u16 board_type;
+ u16 max_ports;
+ struct netxen_board_info boardcfg;
+ u32 xg_linkup;
+ u32 qg_linksup;
+ /* Address of cmd ring in Phantom */
+ struct cmd_desc_type0 *cmd_desc_head;
+ struct pci_dev *cmd_desc_pdev;
+ dma_addr_t cmd_desc_phys_addr;
+ struct netxen_adapter *adapter;
+ int pci_func;
+};
+
+#define RCV_RING_LRO RCV_DESC_LRO
+
+#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
+#define ETHERNET_FCS_SIZE 4
+
+struct netxen_adapter_stats {
+ u64 rcvdbadskb;
+ u64 xmitcalled;
+ u64 xmitedframes;
+ u64 xmitfinished;
+ u64 badskblen;
+ u64 nocmddescriptor;
+ u64 polled;
+ u64 uphappy;
+ u64 updropped;
+ u64 uplcong;
+ u64 uphcong;
+ u64 upmcong;
+ u64 updunno;
+ u64 skbfreed;
+ u64 txdropped;
+ u64 txnullskb;
+ u64 csummed;
+ u64 no_rcv;
+ u64 rxbytes;
+ u64 txbytes;
+ u64 ints;
+};
+
+/*
+ * Rcv Descriptor Context. One such per Rcv Descriptor. There may
+ * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
+ */
+struct netxen_rcv_desc_ctx {
+ u32 flags;
+ u32 producer;
+ u32 rcv_pending; /* Num of bufs posted in phantom */
+ u32 rcv_free; /* Num of bufs in free list */
+ dma_addr_t phys_addr;
+ struct pci_dev *phys_pdev;
+ struct rcv_desc *desc_head; /* address of rx ring in Phantom */
+ u32 max_rx_desc_count;
+ u32 dma_size;
+ u32 skb_size;
+ struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
+ int begin_alloc;
+};
+
+/*
+ * Receive context. There is one such structure per instance of the
+ * receive processing. Any state information that is relevant to
+ * the receive, and is must be in this structure. The global data may be
+ * present elsewhere.
+ */
+struct netxen_recv_context {
+ struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS];
+ u32 status_rx_producer;
+ u32 status_rx_consumer;
+ dma_addr_t rcv_status_desc_phys_addr;
+ struct pci_dev *rcv_status_desc_pdev;
+ struct status_desc *rcv_status_desc_head;
+};
+
+#define NETXEN_NIC_MSI_ENABLED 0x02
+#define NETXEN_DMA_MASK 0xfffffffe
+#define NETXEN_DB_MAPSIZE_BYTES 0x1000
+
+struct netxen_dummy_dma {
+ void *addr;
+ dma_addr_t phys_addr;
+};
+
+struct netxen_adapter {
+ struct netxen_hardware_context ahw;
+
+ struct netxen_adapter *master;
+ struct net_device *netdev;
+ struct pci_dev *pdev;
+ struct net_device_stats net_stats;
+ unsigned char mac_addr[ETH_ALEN];
+ int mtu;
+ int portnum;
+
+ spinlock_t tx_lock;
+ spinlock_t lock;
+ struct work_struct watchdog_task;
+ struct timer_list watchdog_timer;
+ struct work_struct tx_timeout_task;
+
+ u32 curr_window;
+
+ u32 cmd_producer;
+ u32 *cmd_consumer;
+
+ u32 last_cmd_consumer;
+ u32 max_tx_desc_count;
+ u32 max_rx_desc_count;
+ u32 max_jumbo_rx_desc_count;
+ u32 max_lro_rx_desc_count;
+ /* Num of instances active on cmd buffer ring */
+ u32 proc_cmd_buf_counter;
+
+ u32 num_threads, total_threads; /*Use to keep track of xmit threads */
+
+ u32 flags;
+ u32 irq;
+ int driver_mismatch;
+ u32 temp;
+
+ struct netxen_adapter_stats stats;
+
+ u16 portno;
+ u16 link_speed;
+ u16 link_duplex;
+ u16 state;
+ u16 link_autoneg;
+ int rcsum;
+ int status;
+ spinlock_t stats_lock;
+
+ struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
+
+ /*
+ * Receive instances. These can be either one per port,
+ * or one per peg, etc.
+ */
+ struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
+
+ int is_up;
+ struct netxen_dummy_dma dummy_dma;
+
+ /* Context interface shared between card and host */
+ struct netxen_ring_ctx *ctx_desc;
+ struct pci_dev *ctx_desc_pdev;
+ dma_addr_t ctx_desc_phys_addr;
+ int (*enable_phy_interrupts) (struct netxen_adapter *);
+ int (*disable_phy_interrupts) (struct netxen_adapter *);
+ void (*handle_phy_intr) (struct netxen_adapter *);
+ int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
+ int (*set_mtu) (struct netxen_adapter *, int);
+ int (*set_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t);
+ int (*unset_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t);
+ int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
+ int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
+ int (*init_port) (struct netxen_adapter *, int);
+ void (*init_niu) (struct netxen_adapter *);
+ int (*stop_port) (struct netxen_adapter *);
+}; /* netxen_adapter structure */
+
+/* Max number of xmit producer threads that can run simultaneously */
+#define MAX_XMIT_PRODUCERS 16
+
+#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
+ ((adapter)->ahw.pci_base0 + (off))
+#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
+ ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
+#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
+ ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
+
+static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
+ unsigned long off)
+{
+ if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
+ return (adapter->ahw.pci_base0 + off);
+ } else if ((off < SECOND_PAGE_GROUP_END) &&
+ (off >= SECOND_PAGE_GROUP_START)) {
+ return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
+ } else if ((off < THIRD_PAGE_GROUP_END) &&
+ (off >= THIRD_PAGE_GROUP_START)) {
+ return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
+ }
+ return NULL;
+}
+
+static inline void __iomem *pci_base(struct netxen_adapter *adapter,
+ unsigned long off)
+{
+ if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
+ return adapter->ahw.pci_base0;
+ } else if ((off < SECOND_PAGE_GROUP_END) &&
+ (off >= SECOND_PAGE_GROUP_START)) {
+ return adapter->ahw.pci_base1;
+ } else if ((off < THIRD_PAGE_GROUP_END) &&
+ (off >= THIRD_PAGE_GROUP_START)) {
+ return adapter->ahw.pci_base2;
+ }
+ return NULL;
+}
+
+int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
+int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
+int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
+int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
+int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter);
+int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter);
+void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter);
+void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter);
+void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter, int port,
+ long enable);
+void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter, int port,
+ long enable);
+int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
+ __u32 * readval);
+int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
+ long reg, __u32 val);
+
+/* Functions available from netxen_nic_hw.c */
+int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
+int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
+void netxen_nic_init_niu_gb(struct netxen_adapter *adapter);
+void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw);
+void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
+int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
+void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
+void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value);
+
+int netxen_nic_get_board_info(struct netxen_adapter *adapter);
+int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
+ int len);
+int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
+ int len);
+void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
+ unsigned long off, int data);
+int netxen_nic_erase_pxe(struct netxen_adapter *adapter);
+
+/* Functions from netxen_nic_init.c */
+void netxen_free_adapter_offload(struct netxen_adapter *adapter);
+int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
+void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
+void netxen_load_firmware(struct netxen_adapter *adapter);
+int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
+int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
+int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
+ u8 *bytes, size_t size);
+int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
+ u8 *bytes, size_t size);
+int netxen_flash_unlock(struct netxen_adapter *adapter);
+int netxen_backup_crbinit(struct netxen_adapter *adapter);
+int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
+int netxen_flash_erase_primary(struct netxen_adapter *adapter);
+void netxen_halt_pegs(struct netxen_adapter *adapter);
+
+int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data);
+int netxen_rom_se(struct netxen_adapter *adapter, int addr);
+int netxen_do_rom_se(struct netxen_adapter *adapter, int addr);
+
+/* Functions from netxen_nic_isr.c */
+void netxen_nic_isr_other(struct netxen_adapter *adapter);
+void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 link);
+void netxen_handle_port_int(struct netxen_adapter *adapter, u32 enable);
+void netxen_initialize_adapter_sw(struct netxen_adapter *adapter);
+void netxen_initialize_adapter_hw(struct netxen_adapter *adapter);
+void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
+ struct pci_dev **used_dev);
+void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
+int netxen_init_firmware(struct netxen_adapter *adapter);
+void netxen_free_hw_resources(struct netxen_adapter *adapter);
+void netxen_tso_check(struct netxen_adapter *adapter,
+ struct cmd_desc_type0 *desc, struct sk_buff *skb);
+int netxen_nic_hw_resources(struct netxen_adapter *adapter);
+void netxen_nic_clear_stats(struct netxen_adapter *adapter);
+int netxen_nic_rx_has_work(struct netxen_adapter *adapter);
+int netxen_nic_tx_has_work(struct netxen_adapter *adapter);
+void netxen_watchdog_task(unsigned long adapid);
+void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
+ u32 ringid);
+void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, u32 ctx,
+ u32 ringid);
+int netxen_process_cmd_ring(unsigned long data);
+u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
+void netxen_nic_set_multi(struct net_device *netdev);
+int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
+int netxen_nic_set_mac(struct net_device *netdev, void *p);
+struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
+
+static inline void netxen_nic_disable_int(struct netxen_adapter *adapter)
+{
+ /*
+ * ISR_INT_MASK: Can be read from window 0 or 1.
+ */
+ writel(0x7ff, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
+
+}
+
+static inline void netxen_nic_enable_int(struct netxen_adapter *adapter)
+{
+ u32 mask;
+
+ switch (adapter->ahw.board_type) {
+ case NETXEN_NIC_GBE:
+ mask = 0x77b;
+ break;
+ case NETXEN_NIC_XGBE:
+ mask = 0x77f;
+ break;
+ default:
+ mask = 0x7ff;
+ break;
+ }
+
+ writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
+
+ if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
+ mask = 0xbff;
+ writel(0X0, NETXEN_CRB_NORMALIZE(adapter, CRB_INT_VECTOR));
+ writel(mask, PCI_OFFSET_SECOND_RANGE(adapter,
+ ISR_INT_TARGET_MASK));
+ }
+}
+
+/*
+ * NetXen Board information
+ */
+
+#define NETXEN_MAX_SHORT_NAME 16
+struct netxen_brdinfo {
+ netxen_brdtype_t brdtype; /* type of board */
+ long ports; /* max no of physical ports */
+ char short_name[NETXEN_MAX_SHORT_NAME];
+};
+
+static const struct netxen_brdinfo netxen_boards[] = {
+ {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
+ {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
+ {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
+ {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
+ {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
+ {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
+};
+
+#define NUM_SUPPORTED_BOARDS (sizeof(netxen_boards)/sizeof(struct netxen_brdinfo))
+
+static inline void get_brd_port_by_type(u32 type, int *ports)
+{
+ int i, found = 0;
+ for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
+ if (netxen_boards[i].brdtype == type) {
+ *ports = netxen_boards[i].ports;
+ found = 1;
+ break;
+ }
+ }
+ if (!found)
+ *ports = 0;
+}
+
+static inline void get_brd_name_by_type(u32 type, char *name)
+{
+ int i, found = 0;
+ for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
+ if (netxen_boards[i].brdtype == type) {
+ strcpy(name, netxen_boards[i].short_name);
+ found = 1;
+ break;
+ }
+
+ }
+ if (!found)
+ name = "Unknown";
+}
+
+int netxen_is_flash_supported(struct netxen_adapter *adapter);
+int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[]);
+extern void netxen_change_ringparam(struct netxen_adapter *adapter);
+extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
+ int *valp);
+
+extern struct ethtool_ops netxen_nic_ethtool_ops;
+
+extern int physical_port[]; /* physical port # from virtual port.*/
+#endif /* __NETXEN_NIC_H_ */
--- linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_phan_reg.h.rhel5
+++ linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_phan_reg.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2003 - 2006 NetXen, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
+ * MA 02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.
+ *
+ * Contact Information:
+ * info@netxen.com
+ * NetXen,
+ * 3965 Freedom Circle, Fourth floor,
+ * Santa Clara, CA 95054
+ */
+
+#ifndef __NIC_PHAN_REG_H_
+#define __NIC_PHAN_REG_H_
+
+/*
+ * CRB Registers or queue message done only at initialization time.
+ */
+#define NIC_CRB_BASE NETXEN_CAM_RAM(0x200)
+#define NETXEN_NIC_REG(X) (NIC_CRB_BASE+(X))
+
+#define CRB_PHAN_CNTRL_LO_OFFSET NETXEN_NIC_REG(0x00)
+#define CRB_PHAN_CNTRL_HI_OFFSET NETXEN_NIC_REG(0x04)
+#define CRB_CMD_PRODUCER_OFFSET NETXEN_NIC_REG(0x08)
+#define CRB_CMD_CONSUMER_OFFSET NETXEN_NIC_REG(0x0c)
+#define CRB_PAUSE_ADDR_LO NETXEN_NIC_REG(0x10) /* C0 EPG BUG */
+#define CRB_PAUSE_ADDR_HI NETXEN_NIC_REG(0x14)
+#define CRB_HOST_CMD_ADDR_HI NETXEN_NIC_REG(0x18) /* host add:cmd ring */
+#define CRB_HOST_CMD_ADDR_LO NETXEN_NIC_REG(0x1c)
+#define CRB_CMD_INTR_LOOP NETXEN_NIC_REG(0x20) /* 4 regs for perf */
+#define CRB_CMD_DMA_LOOP NETXEN_NIC_REG(0x24)
+#define CRB_RCV_INTR_LOOP NETXEN_NIC_REG(0x28)
+#define CRB_RCV_DMA_LOOP NETXEN_NIC_REG(0x2c)
+#define CRB_ENABLE_TX_INTR NETXEN_NIC_REG(0x30) /* phantom init status */
+#define CRB_MMAP_ADDR_3 NETXEN_NIC_REG(0x34)
+#define CRB_CMDPEG_CMDRING NETXEN_NIC_REG(0x38)
+#define CRB_HOST_DUMMY_BUF_ADDR_HI NETXEN_NIC_REG(0x3c)
+#define CRB_HOST_DUMMY_BUF_ADDR_LO NETXEN_NIC_REG(0x40)
+#define CRB_MMAP_ADDR_0 NETXEN_NIC_REG(0x44)
+#define CRB_MMAP_ADDR_1 NETXEN_NIC_REG(0x48)
+#define CRB_MMAP_ADDR_2 NETXEN_NIC_REG(0x4c)
+#define CRB_CMDPEG_STATE NETXEN_NIC_REG(0x50)
+#define CRB_MMAP_SIZE_0 NETXEN_NIC_REG(0x54)
+#define CRB_MMAP_SIZE_1 NETXEN_NIC_REG(0x58)
+#define CRB_MMAP_SIZE_2 NETXEN_NIC_REG(0x5c)
+#define CRB_MMAP_SIZE_3 NETXEN_NIC_REG(0x60)
+#define CRB_GLOBAL_INT_COAL NETXEN_NIC_REG(0x64) /* interrupt coalescing */
+#define CRB_INT_COAL_MODE NETXEN_NIC_REG(0x68)
+#define CRB_MAX_RCV_BUFS NETXEN_NIC_REG(0x6c)
+#define CRB_TX_INT_THRESHOLD NETXEN_NIC_REG(0x70)
+#define CRB_RX_PKT_TIMER NETXEN_NIC_REG(0x74)
+#define CRB_TX_PKT_TIMER NETXEN_NIC_REG(0x78)
+#define CRB_RX_PKT_CNT NETXEN_NIC_REG(0x7c)
+#define CRB_RX_TMR_CNT NETXEN_NIC_REG(0x80)
+#define CRB_RX_LRO_TIMER NETXEN_NIC_REG(0x84)
+#define CRB_RX_LRO_MID_TIMER NETXEN_NIC_REG(0x88)
+#define CRB_DMA_MAX_RCV_BUFS NETXEN_NIC_REG(0x8c)
+#define CRB_MAX_DMA_ENTRIES NETXEN_NIC_REG(0x90)
+#define CRB_XG_STATE NETXEN_NIC_REG(0x94) /* XG Link status */
+#define CRB_AGENT_GO NETXEN_NIC_REG(0x98) /* NIC pkt gen agent */
+#define CRB_AGENT_TX_SIZE NETXEN_NIC_REG(0x9c)
+#define CRB_AGENT_TX_TYPE NETXEN_NIC_REG(0xa0)
+#define CRB_AGENT_TX_ADDR NETXEN_NIC_REG(0xa4)
+#define CRB_AGENT_TX_MSS NETXEN_NIC_REG(0xa8)
+#define CRB_TX_STATE NETXEN_NIC_REG(0xac) /* Debug -performance */
+#define CRB_TX_COUNT NETXEN_NIC_REG(0xb0)
+#define CRB_RX_STATE NETXEN_NIC_REG(0xb4)
+#define CRB_RX_PERF_DEBUG_1 NETXEN_NIC_REG(0xb8)
+#define CRB_RX_LRO_CONTROL NETXEN_NIC_REG(0xbc) /* LRO On/OFF */
+#define CRB_RX_LRO_START_NUM NETXEN_NIC_REG(0xc0)
+#define CRB_MPORT_MODE NETXEN_NIC_REG(0xc4) /* Multiport Mode */
+#define CRB_CMD_RING_SIZE NETXEN_NIC_REG(0xc8)
+#define CRB_INT_VECTOR NETXEN_NIC_REG(0xd4)
+#define CRB_CTX_RESET NETXEN_NIC_REG(0xd8)
+#define CRB_HOST_STS_PROD NETXEN_NIC_REG(0xdc)
+#define CRB_HOST_STS_CONS NETXEN_NIC_REG(0xe0)
+#define CRB_PEG_CMD_PROD NETXEN_NIC_REG(0xe4)
+#define CRB_PEG_CMD_CONS NETXEN_NIC_REG(0xe8)
+#define CRB_HOST_BUFFER_PROD NETXEN_NIC_REG(0xec)
+#define CRB_HOST_BUFFER_CONS NETXEN_NIC_REG(0xf0)
+#define CRB_JUMBO_BUFFER_PROD NETXEN_NIC_REG(0xf4)
+#define CRB_JUMBO_BUFFER_CONS NETXEN_NIC_REG(0xf8)
+
+#define CRB_CMD_PRODUCER_OFFSET_1 NETXEN_NIC_REG(0x1ac)
+#define CRB_CMD_CONSUMER_OFFSET_1 NETXEN_NIC_REG(0x1b0)
+#define CRB_CMD_PRODUCER_OFFSET_2 NETXEN_NIC_REG(0x1b8)
+#define CRB_CMD_CONSUMER_OFFSET_2 NETXEN_NIC_REG(0x1bc)
+
+// 1c0 to 1cc used for signature reg
+#define CRB_CMD_PRODUCER_OFFSET_3 NETXEN_NIC_REG(0x1d0)
+#define CRB_CMD_CONSUMER_OFFSET_3 NETXEN_NIC_REG(0x1d4)
+#define CRB_TEMP_STATE NETXEN_NIC_REG(0x1b4)
+
+#define CRB_V2P_0 NETXEN_NIC_REG(0x290)
+#define CRB_V2P_1 NETXEN_NIC_REG(0x294)
+#define CRB_V2P_2 NETXEN_NIC_REG(0x298)
+#define CRB_V2P_3 NETXEN_NIC_REG(0x29c)
+#define CRB_V2P(port) (CRB_V2P_0+((port)*4))
+#define CRB_DRIVER_VERSION NETXEN_NIC_REG(0x2a0)
+
+/* used for ethtool tests */
+#define CRB_SCRATCHPAD_TEST NETXEN_NIC_REG(0x280)
+
+/*
+ * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address
+ * which can be read by the Phantom host to get producer/consumer indexes from
+ * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following
+ * registers will be used for the addresses of the ring's shared memory
+ * on the Phantom.
+ */
+
+#define nx_get_temp_val(x) ((x) >> 16)
+#define nx_get_temp_state(x) ((x) & 0xffff)
+#define nx_encode_temp(val, state) (((val) << 16) | (state))
+
+/* CRB registers per Rcv Descriptor ring */
+struct netxen_rcv_desc_crb {
+ u32 crb_rcv_producer_offset __attribute__ ((aligned(512)));
+ u32 crb_rcv_consumer_offset;
+ u32 crb_globalrcv_ring;
+ u32 crb_rcv_ring_size;
+};
+
+/*
+ * CRB registers used by the receive peg logic.
+ */
+
+struct netxen_recv_crb {
+ struct netxen_rcv_desc_crb rcv_desc_crb[NUM_RCV_DESC_RINGS];
+ u32 crb_rcvstatus_ring;
+ u32 crb_rcv_status_producer;
+ u32 crb_rcv_status_consumer;
+ u32 crb_rcvpeg_state;
+ u32 crb_status_ring_size;
+};
+
+#if defined(DEFINE_GLOBAL_RECV_CRB)
+#else
+extern struct netxen_recv_crb recv_crb_registers[];
+extern u64 ctx_addr_sig_regs[][3];
+#endif /* DEFINE_GLOBAL_RECEIVE_CRB */
+#define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
+#define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
+#define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
+
+/*
+ * Temperature control.
+ */
+enum {
+ NX_TEMP_NORMAL = 0x1, /* Normal operating range */
+ NX_TEMP_WARN, /* Sound alert, temperature getting high */
+ NX_TEMP_PANIC /* Fatal error, hardware has shut down. */
+};
+
+#endif /* __NIC_PHAN_REG_H_ */
--- linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_hdr.h.rhel5
+++ linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_hdr.h
@@ -0,0 +1,690 @@
+/*
+ * Copyright (C) 2003 - 2006 NetXen, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
+ * MA 02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.
+ *
+ * Contact Information:
+ * info@netxen.com
+ * NetXen,
+ * 3965 Freedom Circle, Fourth floor,
+ * Santa Clara, CA 95054
+ */
+
+#ifndef __NETXEN_NIC_HDR_H_
+#define __NETXEN_NIC_HDR_H_
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+
+#include <asm/semaphore.h>
+#include <linux/spinlock.h>
+#include <asm/irq.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <asm/uaccess.h>
+#include <asm/string.h> /* for memset */
+
+/*
+ * The basic unit of access when reading/writing control registers.
+ */
+
+typedef __le32 netxen_crbword_t; /* single word in CRB space */
+
+enum {
+ NETXEN_HW_H0_CH_HUB_ADR = 0x05,
+ NETXEN_HW_H1_CH_HUB_ADR = 0x0E,
+ NETXEN_HW_H2_CH_HUB_ADR = 0x03,
+ NETXEN_HW_H3_CH_HUB_ADR = 0x01,
+ NETXEN_HW_H4_CH_HUB_ADR = 0x06,
+ NETXEN_HW_H5_CH_HUB_ADR = 0x07,
+ NETXEN_HW_H6_CH_HUB_ADR = 0x08
+};
+
+/* Hub 0 */
+enum {
+ NETXEN_HW_MN_CRB_AGT_ADR = 0x15,
+ NETXEN_HW_MS_CRB_AGT_ADR = 0x25
+};
+
+/* Hub 1 */
+enum {
+ NETXEN_HW_PS_CRB_AGT_ADR = 0x73,
+ NETXEN_HW_SS_CRB_AGT_ADR = 0x20,
+ NETXEN_HW_RPMX3_CRB_AGT_ADR = 0x0b,
+ NETXEN_HW_QMS_CRB_AGT_ADR = 0x00,
+ NETXEN_HW_SQGS0_CRB_AGT_ADR = 0x01,
+ NETXEN_HW_SQGS1_CRB_AGT_ADR = 0x02,
+ NETXEN_HW_SQGS2_CRB_AGT_ADR = 0x03,
+ NETXEN_HW_SQGS3_CRB_AGT_ADR = 0x04,
+ NETXEN_HW_C2C0_CRB_AGT_ADR = 0x58,
+ NETXEN_HW_C2C1_CRB_AGT_ADR = 0x59,
+ NETXEN_HW_C2C2_CRB_AGT_ADR = 0x5a,
+ NETXEN_HW_RPMX2_CRB_AGT_ADR = 0x0a,
+ NETXEN_HW_RPMX4_CRB_AGT_ADR = 0x0c,
+ NETXEN_HW_RPMX7_CRB_AGT_ADR = 0x0f,
+ NETXEN_HW_RPMX9_CRB_AGT_ADR = 0x12,
+ NETXEN_HW_SMB_CRB_AGT_ADR = 0x18
+};
+
+/* Hub 2 */
+enum {
+ NETXEN_HW_NIU_CRB_AGT_ADR = 0x31,
+ NETXEN_HW_I2C0_CRB_AGT_ADR = 0x19,
+ NETXEN_HW_I2C1_CRB_AGT_ADR = 0x29,
+
+ NETXEN_HW_SN_CRB_AGT_ADR = 0x10,
+ NETXEN_HW_I2Q_CRB_AGT_ADR = 0x20,
+ NETXEN_HW_LPC_CRB_AGT_ADR = 0x22,
+ NETXEN_HW_ROMUSB_CRB_AGT_ADR = 0x21,
+ NETXEN_HW_QM_CRB_AGT_ADR = 0x66,
+ NETXEN_HW_SQG0_CRB_AGT_ADR = 0x60,
+ NETXEN_HW_SQG1_CRB_AGT_ADR = 0x61,
+ NETXEN_HW_SQG2_CRB_AGT_ADR = 0x62,
+ NETXEN_HW_SQG3_CRB_AGT_ADR = 0x63,
+ NETXEN_HW_RPMX1_CRB_AGT_ADR = 0x09,
+ NETXEN_HW_RPMX5_CRB_AGT_ADR = 0x0d,
+ NETXEN_HW_RPMX6_CRB_AGT_ADR = 0x0e,
+ NETXEN_HW_RPMX8_CRB_AGT_ADR = 0x11
+};
+
+/* Hub 3 */
+enum {
+ NETXEN_HW_PH_CRB_AGT_ADR = 0x1A,
+ NETXEN_HW_SRE_CRB_AGT_ADR = 0x50,
+ NETXEN_HW_EG_CRB_AGT_ADR = 0x51,
+ NETXEN_HW_RPMX0_CRB_AGT_ADR = 0x08
+};
+
+/* Hub 4 */
+enum {
+ NETXEN_HW_PEGN0_CRB_AGT_ADR = 0x40,
+ NETXEN_HW_PEGN1_CRB_AGT_ADR,
+ NETXEN_HW_PEGN2_CRB_AGT_ADR,
+ NETXEN_HW_PEGN3_CRB_AGT_ADR,
+ NETXEN_HW_PEGNI_CRB_AGT_ADR,
+ NETXEN_HW_PEGND_CRB_AGT_ADR,
+ NETXEN_HW_PEGNC_CRB_AGT_ADR,
+ NETXEN_HW_PEGR0_CRB_AGT_ADR,
+ NETXEN_HW_PEGR1_CRB_AGT_ADR,
+ NETXEN_HW_PEGR2_CRB_AGT_ADR,
+ NETXEN_HW_PEGR3_CRB_AGT_ADR
+};
+
+/* Hub 5 */
+enum {
+ NETXEN_HW_PEGS0_CRB_AGT_ADR = 0x40,
+ NETXEN_HW_PEGS1_CRB_AGT_ADR,
+ NETXEN_HW_PEGS2_CRB_AGT_ADR,
+ NETXEN_HW_PEGS3_CRB_AGT_ADR,
+ NETXEN_HW_PEGSI_CRB_AGT_ADR,
+ NETXEN_HW_PEGSD_CRB_AGT_ADR,
+ NETXEN_HW_PEGSC_CRB_AGT_ADR
+};
+
+/* Hub 6 */
+enum {
+ NETXEN_HW_CAS0_CRB_AGT_ADR = 0x46,
+ NETXEN_HW_CAS1_CRB_AGT_ADR = 0x47,
+ NETXEN_HW_CAS2_CRB_AGT_ADR = 0x48,
+ NETXEN_HW_CAS3_CRB_AGT_ADR = 0x49,
+ NETXEN_HW_NCM_CRB_AGT_ADR = 0x16,
+ NETXEN_HW_TMR_CRB_AGT_ADR = 0x17,
+ NETXEN_HW_XDMA_CRB_AGT_ADR = 0x05,
+ NETXEN_HW_OCM0_CRB_AGT_ADR = 0x06,
+ NETXEN_HW_OCM1_CRB_AGT_ADR = 0x07
+};
+
+/* Floaters - non existent modules */
+#define NETXEN_HW_EFC_RPMX0_CRB_AGT_ADR 0x67
+
+/* This field defines PCI/X adr [25:20] of agents on the CRB */
+enum {
+ NETXEN_HW_PX_MAP_CRB_PH = 0,
+ NETXEN_HW_PX_MAP_CRB_PS,
+ NETXEN_HW_PX_MAP_CRB_MN,
+ NETXEN_HW_PX_MAP_CRB_MS,
+ NETXEN_HW_PX_MAP_CRB_PGR1,
+ NETXEN_HW_PX_MAP_CRB_SRE,
+ NETXEN_HW_PX_MAP_CRB_NIU,
+ NETXEN_HW_PX_MAP_CRB_QMN,
+ NETXEN_HW_PX_MAP_CRB_SQN0,
+ NETXEN_HW_PX_MAP_CRB_SQN1,
+ NETXEN_HW_PX_MAP_CRB_SQN2,
+ NETXEN_HW_PX_MAP_CRB_SQN3,
+ NETXEN_HW_PX_MAP_CRB_QMS,
+ NETXEN_HW_PX_MAP_CRB_SQS0,
+ NETXEN_HW_PX_MAP_CRB_SQS1,
+ NETXEN_HW_PX_MAP_CRB_SQS2,
+ NETXEN_HW_PX_MAP_CRB_SQS3,
+ NETXEN_HW_PX_MAP_CRB_PGN0,
+ NETXEN_HW_PX_MAP_CRB_PGN1,
+ NETXEN_HW_PX_MAP_CRB_PGN2,
+ NETXEN_HW_PX_MAP_CRB_PGN3,
+ NETXEN_HW_PX_MAP_CRB_PGND,
+ NETXEN_HW_PX_MAP_CRB_PGNI,
+ NETXEN_HW_PX_MAP_CRB_PGS0,
+ NETXEN_HW_PX_MAP_CRB_PGS1,
+ NETXEN_HW_PX_MAP_CRB_PGS2,
+ NETXEN_HW_PX_MAP_CRB_PGS3,
+ NETXEN_HW_PX_MAP_CRB_PGSD,
+ NETXEN_HW_PX_MAP_CRB_PGSI,
+ NETXEN_HW_PX_MAP_CRB_SN,
+ NETXEN_HW_PX_MAP_CRB_PGR2,
+ NETXEN_HW_PX_MAP_CRB_EG,
+ NETXEN_HW_PX_MAP_CRB_PH2,
+ NETXEN_HW_PX_MAP_CRB_PS2,
+ NETXEN_HW_PX_MAP_CRB_CAM,
+ NETXEN_HW_PX_MAP_CRB_CAS0,
+ NETXEN_HW_PX_MAP_CRB_CAS1,
+ NETXEN_HW_PX_MAP_CRB_CAS2,
+ NETXEN_HW_PX_MAP_CRB_C2C0,
+ NETXEN_HW_PX_MAP_CRB_C2C1,
+ NETXEN_HW_PX_MAP_CRB_TIMR,
+ NETXEN_HW_PX_MAP_CRB_PGR3,
+ NETXEN_HW_PX_MAP_CRB_RPMX1,
+ NETXEN_HW_PX_MAP_CRB_RPMX2,
+ NETXEN_HW_PX_MAP_CRB_RPMX3,
+ NETXEN_HW_PX_MAP_CRB_RPMX4,
+ NETXEN_HW_PX_MAP_CRB_RPMX5,
+ NETXEN_HW_PX_MAP_CRB_RPMX6,
+ NETXEN_HW_PX_MAP_CRB_RPMX7,
+ NETXEN_HW_PX_MAP_CRB_XDMA,
+ NETXEN_HW_PX_MAP_CRB_I2Q,
+ NETXEN_HW_PX_MAP_CRB_ROMUSB,
+ NETXEN_HW_PX_MAP_CRB_CAS3,
+ NETXEN_HW_PX_MAP_CRB_RPMX0,
+ NETXEN_HW_PX_MAP_CRB_RPMX8,
+ NETXEN_HW_PX_MAP_CRB_RPMX9,
+ NETXEN_HW_PX_MAP_CRB_OCM0,
+ NETXEN_HW_PX_MAP_CRB_OCM1,
+ NETXEN_HW_PX_MAP_CRB_SMB,
+ NETXEN_HW_PX_MAP_CRB_I2C0,
+ NETXEN_HW_PX_MAP_CRB_I2C1,
+ NETXEN_HW_PX_MAP_CRB_LPC,
+ NETXEN_HW_PX_MAP_CRB_PGNC,
+ NETXEN_HW_PX_MAP_CRB_PGR0
+};
+
+/* This field defines CRB adr [31:20] of the agents */
+
+#define NETXEN_HW_CRB_HUB_AGT_ADR_MN \
+ ((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_MN_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PH \
+ ((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_PH_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_MS \
+ ((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_MS_CRB_AGT_ADR)
+
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PS \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_PS_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_SS \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SS_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3 \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX3_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_QMS \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_QMS_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS0 \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS0_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS1 \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS1_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS2 \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS2_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS3 \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS3_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_C2C0 \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_C2C0_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_C2C1 \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_C2C1_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2 \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX2_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4 \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX4_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7 \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX7_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9 \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX9_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_SMB \
+ ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SMB_CRB_AGT_ADR)
+
+#define NETXEN_HW_CRB_HUB_AGT_ADR_NIU \
+ ((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_NIU_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_I2C0 \
+ ((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_I2C0_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_I2C1 \
+ ((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_I2C1_CRB_AGT_ADR)
+
+#define NETXEN_HW_CRB_HUB_AGT_ADR_SRE \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SRE_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_EG \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_EG_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX0_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_QMN \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_QM_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN0 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG0_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN1 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG1_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN2 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG2_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN3 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG3_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX1_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX5_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX6_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX8_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS0 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS0_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS1 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS1_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS2 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS2_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS3 \
+ ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS3_CRB_AGT_ADR)
+
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGNI \
+ ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGNI_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGND \
+ ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGND_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN0 \
+ ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN0_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN1 \
+ ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN1_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN2 \
+ ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN2_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN3 \
+ ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN3_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGNC \
+ ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGNC_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR0 \
+ ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR0_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR1 \
+ ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR1_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR2 \
+ ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR2_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR3 \
+ ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR3_CRB_AGT_ADR)
+
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGSI \
+ ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSI_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGSD \
+ ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSD_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS0 \
+ ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS0_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS1 \
+ ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS1_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS2 \
+ ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS2_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS3 \
+ ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS3_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_PGSC \
+ ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSC_CRB_AGT_ADR)
+
+#define NETXEN_HW_CRB_HUB_AGT_ADR_CAM \
+ ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_NCM_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_TIMR \
+ ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_TMR_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_XDMA \
+ ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_XDMA_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_SN \
+ ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_SN_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_I2Q \
+ ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_I2Q_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB \
+ ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_ROMUSB_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_OCM0 \
+ ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_OCM0_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_OCM1 \
+ ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_OCM1_CRB_AGT_ADR)
+#define NETXEN_HW_CRB_HUB_AGT_ADR_LPC \
+ ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_LPC_CRB_AGT_ADR)
+
+/*
+ * MAX_RCV_CTX : The number of receive contexts that are available on
+ * the phantom.
+ */
+#define MAX_RCV_CTX 1
+
+#define NETXEN_SRE_INT_STATUS (NETXEN_CRB_SRE + 0x00034)
+#define NETXEN_SRE_PBI_ACTIVE_STATUS (NETXEN_CRB_SRE + 0x01014)
+#define NETXEN_SRE_L1RE_CTL (NETXEN_CRB_SRE + 0x03000)
+#define NETXEN_SRE_L2RE_CTL (NETXEN_CRB_SRE + 0x05000)
+#define NETXEN_SRE_BUF_CTL (NETXEN_CRB_SRE + 0x01000)
+
+#define NETXEN_DMA_BASE(U) (NETXEN_CRB_PCIX_MD + 0x20000 + ((U)<<16))
+#define NETXEN_DMA_COMMAND(U) (NETXEN_DMA_BASE(U) + 0x00008)
+
+#define NETXEN_I2Q_CLR_PCI_HI (NETXEN_CRB_I2Q + 0x00034)
+
+#define PEG_NETWORK_BASE(N) (NETXEN_CRB_PEG_NET_0 + (((N)&3) << 20))
+#define CRB_REG_EX_PC 0x3c
+
+#define ROMUSB_GLB (NETXEN_CRB_ROMUSB + 0x00000)
+#define ROMUSB_ROM (NETXEN_CRB_ROMUSB + 0x10000)
+
+#define NETXEN_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
+#define NETXEN_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
+#define NETXEN_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c)
+#define NETXEN_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
+#define NETXEN_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044)
+#define NETXEN_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
+#define NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8)
+
+#define NETXEN_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n)))
+
+#define NETXEN_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
+#define NETXEN_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
+#define NETXEN_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
+#define NETXEN_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
+#define NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
+#define NETXEN_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
+
+/* Lock IDs for ROM lock */
+#define ROM_LOCK_DRIVER 0x0d417340
+
+/******************************************************************************
+*
+* Definitions specific to M25P flash
+*
+*******************************************************************************
+* Instructions
+*/
+#define M25P_INSTR_WREN 0x06
+#define M25P_INSTR_WRDI 0x04
+#define M25P_INSTR_RDID 0x9f
+#define M25P_INSTR_RDSR 0x05
+#define M25P_INSTR_WRSR 0x01
+#define M25P_INSTR_READ 0x03
+#define M25P_INSTR_FAST_READ 0x0b
+#define M25P_INSTR_PP 0x02
+#define M25P_INSTR_SE 0xd8
+#define M25P_INSTR_BE 0xc7
+#define M25P_INSTR_DP 0xb9
+#define M25P_INSTR_RES 0xab
+
+/* all are 1MB windows */
+
+#define NETXEN_PCI_CRB_WINDOWSIZE 0x00100000
+#define NETXEN_PCI_CRB_WINDOW(A) \
+ (NETXEN_PCI_CRBSPACE + (A)*NETXEN_PCI_CRB_WINDOWSIZE)
+
+#define NETXEN_CRB_NIU NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_NIU)
+#define NETXEN_CRB_SRE NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SRE)
+#define NETXEN_CRB_ROMUSB \
+ NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_ROMUSB)
+#define NETXEN_CRB_I2Q NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_I2Q)
+#define NETXEN_CRB_MAX NETXEN_PCI_CRB_WINDOW(64)
+
+#define NETXEN_CRB_PCIX_HOST NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PH)
+#define NETXEN_CRB_PCIX_HOST2 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PH2)
+#define NETXEN_CRB_PEG_NET_0 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN0)
+#define NETXEN_CRB_PEG_NET_1 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN1)
+#define NETXEN_CRB_PEG_NET_2 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN2)
+#define NETXEN_CRB_PEG_NET_3 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN3)
+#define NETXEN_CRB_PEG_NET_D NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGND)
+#define NETXEN_CRB_PEG_NET_I NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGNI)
+#define NETXEN_CRB_DDR_NET NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_MN)
+
+#define NETXEN_CRB_PCIX_MD NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PS)
+#define NETXEN_CRB_PCIE NETXEN_CRB_PCIX_MD
+
+#define ISR_INT_VECTOR (NETXEN_PCIX_PS_REG(PCIX_INT_VECTOR))
+#define ISR_INT_MASK (NETXEN_PCIX_PS_REG(PCIX_INT_MASK))
+#define ISR_INT_MASK_SLOW (NETXEN_PCIX_PS_REG(PCIX_INT_MASK))
+#define ISR_INT_TARGET_STATUS (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS))
+#define ISR_INT_TARGET_MASK (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK))
+
+#define NETXEN_PCI_MAPSIZE 128
+#define NETXEN_PCI_DDR_NET (0x00000000UL)
+#define NETXEN_PCI_QDR_NET (0x04000000UL)
+#define NETXEN_PCI_DIRECT_CRB (0x04400000UL)
+#define NETXEN_PCI_CAMQM_MAX (0x04ffffffUL)
+#define NETXEN_PCI_OCM0 (0x05000000UL)
+#define NETXEN_PCI_OCM0_MAX (0x050fffffUL)
+#define NETXEN_PCI_OCM1 (0x05100000UL)
+#define NETXEN_PCI_OCM1_MAX (0x051fffffUL)
+#define NETXEN_PCI_CRBSPACE (0x06000000UL)
+#define NETXEN_PCI_128MB_SIZE (0x08000000UL)
+#define NETXEN_PCI_32MB_SIZE (0x02000000UL)
+
+#define NETXEN_CRB_CAM NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_CAM)
+
+#define NETXEN_ADDR_DDR_NET (0x0000000000000000ULL)
+#define NETXEN_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
+#define NETXEN_ADDR_OCM0 (0x0000000200000000ULL)
+#define NETXEN_ADDR_OCM0_MAX (0x00000002000fffffULL)
+#define NETXEN_ADDR_OCM1 (0x0000000200400000ULL)
+#define NETXEN_ADDR_OCM1_MAX (0x00000002004fffffULL)
+#define NETXEN_ADDR_QDR_NET (0x0000000300000000ULL)
+#define NETXEN_ADDR_QDR_NET_MAX (0x00000003003fffffULL)
+
+ /* 200ms delay in each loop */
+#define NETXEN_NIU_PHY_WAITLEN 200000
+ /* 10 seconds before we give up */
+#define NETXEN_NIU_PHY_WAITMAX 50
+#define NETXEN_NIU_MAX_GBE_PORTS 4
+#define NETXEN_NIU_MAX_XG_PORTS 2
+
+#define NETXEN_NIU_MODE (NETXEN_CRB_NIU + 0x00000)
+
+#define NETXEN_NIU_XG_SINGLE_TERM (NETXEN_CRB_NIU + 0x00004)
+#define NETXEN_NIU_XG_DRIVE_HI (NETXEN_CRB_NIU + 0x00008)
+#define NETXEN_NIU_XG_DRIVE_LO (NETXEN_CRB_NIU + 0x0000c)
+#define NETXEN_NIU_XG_DTX (NETXEN_CRB_NIU + 0x00010)
+#define NETXEN_NIU_XG_DEQ (NETXEN_CRB_NIU + 0x00014)
+#define NETXEN_NIU_XG_WORD_ALIGN (NETXEN_CRB_NIU + 0x00018)
+#define NETXEN_NIU_XG_RESET (NETXEN_CRB_NIU + 0x0001c)
+#define NETXEN_NIU_XG_POWER_DOWN (NETXEN_CRB_NIU + 0x00020)
+#define NETXEN_NIU_XG_RESET_PLL (NETXEN_CRB_NIU + 0x00024)
+#define NETXEN_NIU_XG_SERDES_LOOPBACK (NETXEN_CRB_NIU + 0x00028)
+#define NETXEN_NIU_XG_DO_BYTE_ALIGN (NETXEN_CRB_NIU + 0x0002c)
+#define NETXEN_NIU_XG_TX_ENABLE (NETXEN_CRB_NIU + 0x00030)
+#define NETXEN_NIU_XG_RX_ENABLE (NETXEN_CRB_NIU + 0x00034)
+#define NETXEN_NIU_XG_STATUS (NETXEN_CRB_NIU + 0x00038)
+#define NETXEN_NIU_XG_PAUSE_THRESHOLD (NETXEN_CRB_NIU + 0x0003c)
+#define NETXEN_NIU_INT_MASK (NETXEN_CRB_NIU + 0x00040)
+#define NETXEN_NIU_ACTIVE_INT (NETXEN_CRB_NIU + 0x00044)
+#define NETXEN_NIU_MASKABLE_INT (NETXEN_CRB_NIU + 0x00048)
+
+#define NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER (NETXEN_CRB_NIU + 0x0004c)
+
+#define NETXEN_NIU_GB_SERDES_RESET (NETXEN_CRB_NIU + 0x00050)
+#define NETXEN_NIU_GB0_GMII_MODE (NETXEN_CRB_NIU + 0x00054)
+#define NETXEN_NIU_GB0_MII_MODE (NETXEN_CRB_NIU + 0x00058)
+#define NETXEN_NIU_GB1_GMII_MODE (NETXEN_CRB_NIU + 0x0005c)
+#define NETXEN_NIU_GB1_MII_MODE (NETXEN_CRB_NIU + 0x00060)
+#define NETXEN_NIU_GB2_GMII_MODE (NETXEN_CRB_NIU + 0x00064)
+#define NETXEN_NIU_GB2_MII_MODE (NETXEN_CRB_NIU + 0x00068)
+#define NETXEN_NIU_GB3_GMII_MODE (NETXEN_CRB_NIU + 0x0006c)
+#define NETXEN_NIU_GB3_MII_MODE (NETXEN_CRB_NIU + 0x00070)
+#define NETXEN_NIU_REMOTE_LOOPBACK (NETXEN_CRB_NIU + 0x00074)
+#define NETXEN_NIU_GB0_HALF_DUPLEX (NETXEN_CRB_NIU + 0x00078)
+#define NETXEN_NIU_GB1_HALF_DUPLEX (NETXEN_CRB_NIU + 0x0007c)
+#define NETXEN_NIU_RESET_SYS_FIFOS (NETXEN_CRB_NIU + 0x00088)
+#define NETXEN_NIU_GB_CRC_DROP (NETXEN_CRB_NIU + 0x0008c)
+#define NETXEN_NIU_GB_DROP_WRONGADDR (NETXEN_CRB_NIU + 0x00090)
+#define NETXEN_NIU_TEST_MUX_CTL (NETXEN_CRB_NIU + 0x00094)
+#define NETXEN_NIU_XG_PAUSE_CTL (NETXEN_CRB_NIU + 0x00098)
+#define NETXEN_NIU_XG_PAUSE_LEVEL (NETXEN_CRB_NIU + 0x000dc)
+#define NETXEN_NIU_XG_SEL (NETXEN_CRB_NIU + 0x00128)
+#define NETXEN_NIU_GB_PAUSE_CTL (NETXEN_CRB_NIU + 0x0030c)
+
+#define NETXEN_NIU_FULL_LEVEL_XG (NETXEN_CRB_NIU + 0x00450)
+
+#define NETXEN_NIU_XG1_RESET (NETXEN_CRB_NIU + 0x0011c)
+#define NETXEN_NIU_XG1_POWER_DOWN (NETXEN_CRB_NIU + 0x00120)
+#define NETXEN_NIU_XG1_RESET_PLL (NETXEN_CRB_NIU + 0x00124)
+
+#define NETXEN_MAC_ADDR_CNTL_REG (NETXEN_CRB_NIU + 0x1000)
+
+#define NETXEN_MULTICAST_ADDR_HI_0 (NETXEN_CRB_NIU + 0x1010)
+#define NETXEN_MULTICAST_ADDR_HI_1 (NETXEN_CRB_NIU + 0x1014)
+#define NETXEN_MULTICAST_ADDR_HI_2 (NETXEN_CRB_NIU + 0x1018)
+#define NETXEN_MULTICAST_ADDR_HI_3 (NETXEN_CRB_NIU + 0x101c)
+
+#define NETXEN_NIU_GB_MAC_CONFIG_0(I) \
+ (NETXEN_CRB_NIU + 0x30000 + (I)*0x10000)
+#define NETXEN_NIU_GB_MAC_CONFIG_1(I) \
+ (NETXEN_CRB_NIU + 0x30004 + (I)*0x10000)
+#define NETXEN_NIU_GB_MAC_IPG_IFG(I) \
+ (NETXEN_CRB_NIU + 0x30008 + (I)*0x10000)
+#define NETXEN_NIU_GB_HALF_DUPLEX_CTRL(I) \
+ (NETXEN_CRB_NIU + 0x3000c + (I)*0x10000)
+#define NETXEN_NIU_GB_MAX_FRAME_SIZE(I) \
+ (NETXEN_CRB_NIU + 0x30010 + (I)*0x10000)
+#define NETXEN_NIU_GB_TEST_REG(I) \
+ (NETXEN_CRB_NIU + 0x3001c + (I)*0x10000)
+#define NETXEN_NIU_GB_MII_MGMT_CONFIG(I) \
+ (NETXEN_CRB_NIU + 0x30020 + (I)*0x10000)
+#define NETXEN_NIU_GB_MII_MGMT_COMMAND(I) \
+ (NETXEN_CRB_NIU + 0x30024 + (I)*0x10000)
+#define NETXEN_NIU_GB_MII_MGMT_ADDR(I) \
+ (NETXEN_CRB_NIU + 0x30028 + (I)*0x10000)
+#define NETXEN_NIU_GB_MII_MGMT_CTRL(I) \
+ (NETXEN_CRB_NIU + 0x3002c + (I)*0x10000)
+#define NETXEN_NIU_GB_MII_MGMT_STATUS(I) \
+ (NETXEN_CRB_NIU + 0x30030 + (I)*0x10000)
+#define NETXEN_NIU_GB_MII_MGMT_INDICATE(I) \
+ (NETXEN_CRB_NIU + 0x30034 + (I)*0x10000)
+#define NETXEN_NIU_GB_INTERFACE_CTRL(I) \
+ (NETXEN_CRB_NIU + 0x30038 + (I)*0x10000)
+#define NETXEN_NIU_GB_INTERFACE_STATUS(I) \
+ (NETXEN_CRB_NIU + 0x3003c + (I)*0x10000)
+#define NETXEN_NIU_GB_STATION_ADDR_0(I) \
+ (NETXEN_CRB_NIU + 0x30040 + (I)*0x10000)
+#define NETXEN_NIU_GB_STATION_ADDR_1(I) \
+ (NETXEN_CRB_NIU + 0x30044 + (I)*0x10000)
+
+#define NETXEN_NIU_XGE_CONFIG_0 (NETXEN_CRB_NIU + 0x70000)
+#define NETXEN_NIU_XGE_CONFIG_1 (NETXEN_CRB_NIU + 0x70004)
+#define NETXEN_NIU_XGE_IPG (NETXEN_CRB_NIU + 0x70008)
+#define NETXEN_NIU_XGE_STATION_ADDR_0_HI (NETXEN_CRB_NIU + 0x7000c)
+#define NETXEN_NIU_XGE_STATION_ADDR_0_1 (NETXEN_CRB_NIU + 0x70010)
+#define NETXEN_NIU_XGE_STATION_ADDR_1_LO (NETXEN_CRB_NIU + 0x70014)
+#define NETXEN_NIU_XGE_STATUS (NETXEN_CRB_NIU + 0x70018)
+#define NETXEN_NIU_XGE_MAX_FRAME_SIZE (NETXEN_CRB_NIU + 0x7001c)
+#define NETXEN_NIU_XGE_PAUSE_FRAME_VALUE (NETXEN_CRB_NIU + 0x70020)
+#define NETXEN_NIU_XGE_TX_BYTE_CNT (NETXEN_CRB_NIU + 0x70024)
+#define NETXEN_NIU_XGE_TX_FRAME_CNT (NETXEN_CRB_NIU + 0x70028)
+#define NETXEN_NIU_XGE_RX_BYTE_CNT (NETXEN_CRB_NIU + 0x7002c)
+#define NETXEN_NIU_XGE_RX_FRAME_CNT (NETXEN_CRB_NIU + 0x70030)
+#define NETXEN_NIU_XGE_AGGR_ERROR_CNT (NETXEN_CRB_NIU + 0x70034)
+#define NETXEN_NIU_XGE_MULTICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x70038)
+#define NETXEN_NIU_XGE_UNICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x7003c)
+#define NETXEN_NIU_XGE_CRC_ERROR_CNT (NETXEN_CRB_NIU + 0x70040)
+#define NETXEN_NIU_XGE_OVERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x70044)
+#define NETXEN_NIU_XGE_UNDERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x70048)
+#define NETXEN_NIU_XGE_LOCAL_ERROR_CNT (NETXEN_CRB_NIU + 0x7004c)
+#define NETXEN_NIU_XGE_REMOTE_ERROR_CNT (NETXEN_CRB_NIU + 0x70050)
+#define NETXEN_NIU_XGE_CONTROL_CHAR_CNT (NETXEN_CRB_NIU + 0x70054)
+#define NETXEN_NIU_XGE_PAUSE_FRAME_CNT (NETXEN_CRB_NIU + 0x70058)
+#define NETXEN_NIU_XG1_CONFIG_0 (NETXEN_CRB_NIU + 0x80000)
+#define NETXEN_NIU_XG1_CONFIG_1 (NETXEN_CRB_NIU + 0x80004)
+#define NETXEN_NIU_XG1_IPG (NETXEN_CRB_NIU + 0x80008)
+#define NETXEN_NIU_XG1_STATION_ADDR_0_HI (NETXEN_CRB_NIU + 0x8000c)
+#define NETXEN_NIU_XG1_STATION_ADDR_0_1 (NETXEN_CRB_NIU + 0x80010)
+#define NETXEN_NIU_XG1_STATION_ADDR_1_LO (NETXEN_CRB_NIU + 0x80014)
+#define NETXEN_NIU_XG1_STATUS (NETXEN_CRB_NIU + 0x80018)
+#define NETXEN_NIU_XG1_MAX_FRAME_SIZE (NETXEN_CRB_NIU + 0x8001c)
+#define NETXEN_NIU_XG1_PAUSE_FRAME_VALUE (NETXEN_CRB_NIU + 0x80020)
+#define NETXEN_NIU_XG1_TX_BYTE_CNT (NETXEN_CRB_NIU + 0x80024)
+#define NETXEN_NIU_XG1_TX_FRAME_CNT (NETXEN_CRB_NIU + 0x80028)
+#define NETXEN_NIU_XG1_RX_BYTE_CNT (NETXEN_CRB_NIU + 0x8002c)
+#define NETXEN_NIU_XG1_RX_FRAME_CNT (NETXEN_CRB_NIU + 0x80030)
+#define NETXEN_NIU_XG1_AGGR_ERROR_CNT (NETXEN_CRB_NIU + 0x80034)
+#define NETXEN_NIU_XG1_MULTICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x80038)
+#define NETXEN_NIU_XG1_UNICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x8003c)
+#define NETXEN_NIU_XG1_CRC_ERROR_CNT (NETXEN_CRB_NIU + 0x80040)
+#define NETXEN_NIU_XG1_OVERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x80044)
+#define NETXEN_NIU_XG1_UNDERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x80048)
+#define NETXEN_NIU_XG1_LOCAL_ERROR_CNT (NETXEN_CRB_NIU + 0x8004c)
+#define NETXEN_NIU_XG1_REMOTE_ERROR_CNT (NETXEN_CRB_NIU + 0x80050)
+#define NETXEN_NIU_XG1_CONTROL_CHAR_CNT (NETXEN_CRB_NIU + 0x80054)
+#define NETXEN_NIU_XG1_PAUSE_FRAME_CNT (NETXEN_CRB_NIU + 0x80058)
+
+/* XG Link status */
+#define XG_LINK_UP 0x10
+#define XG_LINK_DOWN 0x20
+
+#define NETXEN_CAM_RAM_BASE (NETXEN_CRB_CAM + 0x02000)
+#define NETXEN_CAM_RAM(reg) (NETXEN_CAM_RAM_BASE + (reg))
+#define NETXEN_FW_VERSION_MAJOR (NETXEN_CAM_RAM(0x150))
+#define NETXEN_FW_VERSION_MINOR (NETXEN_CAM_RAM(0x154))
+#define NETXEN_FW_VERSION_SUB (NETXEN_CAM_RAM(0x158))
+#define NETXEN_ROM_LOCK_ID (NETXEN_CAM_RAM(0x100))
+
+#define NETXEN_PHY_LOCK_ID (NETXEN_CAM_RAM(0x120))
+
+/* Lock IDs for PHY lock */
+#define PHY_LOCK_DRIVER 0x44524956
+
+/* Used for PS PCI Memory access */
+#define PCIX_PS_OP_ADDR_LO (0x10000)
+/* via CRB (PS side only) */
+#define PCIX_PS_OP_ADDR_HI (0x10004)
+
+#define PCIX_INT_VECTOR (0x10100)
+#define PCIX_INT_MASK (0x10104)
+
+#define PCIX_MN_WINDOW (0x10200)
+#define PCIX_MS_WINDOW (0x10204)
+#define PCIX_SN_WINDOW (0x10208)
+#define PCIX_CRB_WINDOW (0x10210)
+#define PCIX_CRB_WINDOW_F0 (0x10210)
+#define PCIX_CRB_WINDOW_F1 (0x10230)
+#define PCIX_CRB_WINDOW_F2 (0x10250)
+#define PCIX_CRB_WINDOW_F3 (0x10270)
+
+#define PCIX_TARGET_STATUS (0x10118)
+#define PCIX_TARGET_MASK (0x10128)
+
+#define PCIX_MSI_F0 (0x13000)
+#define PCIX_MSI_F1 (0x13004)
+#define PCIX_MSI_F2 (0x13008)
+#define PCIX_MSI_F3 (0x1300c)
+#define PCIX_MSI_F(i) (0x13000+((i)*4))
+
+#define PCIX_PS_MEM_SPACE (0x90000)
+
+#define NETXEN_PCIX_PH_REG(reg) (NETXEN_CRB_PCIE + (reg))
+#define NETXEN_PCIX_PS_REG(reg) (NETXEN_CRB_PCIX_MD + (reg))
+
+#define NETXEN_PCIE_REG(reg) (NETXEN_CRB_PCIE + (reg))
+
+#define PCIE_MAX_DMA_XFER_SIZE (0x1404c)
+
+#define PCIE_DCR 0x00d8
+
+#define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
+#define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
+#define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */
+#define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */
+
+#define PCIE_TGT_SPLIT_CHICKEN (0x12080)
+
+#define PCIE_MAX_MASTER_SPLIT (0x14048)
+
+#endif /* __NETXEN_NIC_HDR_H_ */
--- linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_ethtool.c.rhel5
+++ linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_ethtool.c
@@ -0,0 +1,758 @@
+/*
+ * Copyright (C) 2003 - 2006 NetXen, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
+ * MA 02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.
+ *
+ * Contact Information:
+ * info@netxen.com
+ * NetXen,
+ * 3965 Freedom Circle, Fourth floor,
+ * Santa Clara, CA 95054
+ *
+ *
+ * ethtool support for netxen nic
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <asm/uaccess.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+#include <linux/netdevice.h>
+#include <linux/ethtool.h>
+#include <linux/version.h>
+
+#include "netxen_nic.h"
+#include "netxen_nic_hw.h"
+#include "netxen_nic_phan_reg.h"
+
+struct netxen_nic_stats {
+ char stat_string[ETH_GSTRING_LEN];
+ int sizeof_stat;
+ int stat_offset;
+};
+
+#define NETXEN_NIC_STAT(m) sizeof(((struct netxen_adapter *)0)->m), \
+ offsetof(struct netxen_adapter, m)
+
+#define NETXEN_NIC_PORT_WINDOW 0x10000
+#define NETXEN_NIC_INVALID_DATA 0xDEADBEEF
+
+static const struct netxen_nic_stats netxen_nic_gstrings_stats[] = {
+ {"rcvd_bad_skb", NETXEN_NIC_STAT(stats.rcvdbadskb)},
+ {"xmit_called", NETXEN_NIC_STAT(stats.xmitcalled)},
+ {"xmited_frames", NETXEN_NIC_STAT(stats.xmitedframes)},
+ {"xmit_finished", NETXEN_NIC_STAT(stats.xmitfinished)},
+ {"bad_skb_len", NETXEN_NIC_STAT(stats.badskblen)},
+ {"no_cmd_desc", NETXEN_NIC_STAT(stats.nocmddescriptor)},
+ {"polled", NETXEN_NIC_STAT(stats.polled)},
+ {"uphappy", NETXEN_NIC_STAT(stats.uphappy)},
+ {"updropped", NETXEN_NIC_STAT(stats.updropped)},
+ {"uplcong", NETXEN_NIC_STAT(stats.uplcong)},
+ {"uphcong", NETXEN_NIC_STAT(stats.uphcong)},
+ {"upmcong", NETXEN_NIC_STAT(stats.upmcong)},
+ {"updunno", NETXEN_NIC_STAT(stats.updunno)},
+ {"skb_freed", NETXEN_NIC_STAT(stats.skbfreed)},
+ {"tx_dropped", NETXEN_NIC_STAT(stats.txdropped)},
+ {"tx_null_skb", NETXEN_NIC_STAT(stats.txnullskb)},
+ {"csummed", NETXEN_NIC_STAT(stats.csummed)},
+ {"no_rcv", NETXEN_NIC_STAT(stats.no_rcv)},
+ {"rx_bytes", NETXEN_NIC_STAT(stats.rxbytes)},
+ {"tx_bytes", NETXEN_NIC_STAT(stats.txbytes)},
+};
+
+#define NETXEN_NIC_STATS_LEN ARRAY_SIZE(netxen_nic_gstrings_stats)
+
+static const char netxen_nic_gstrings_test[][ETH_GSTRING_LEN] = {
+ "Register_Test_on_offline",
+ "Link_Test_on_offline"
+};
+
+#define NETXEN_NIC_TEST_LEN sizeof(netxen_nic_gstrings_test) / ETH_GSTRING_LEN
+
+#define NETXEN_NIC_REGS_COUNT 42
+#define NETXEN_NIC_REGS_LEN (NETXEN_NIC_REGS_COUNT * sizeof(__le32))
+#define NETXEN_MAX_EEPROM_LEN 1024
+
+static int netxen_nic_get_eeprom_len(struct net_device *dev)
+{
+ return FLASH_TOTAL_SIZE;
+}
+
+static void
+netxen_nic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
+{
+ struct netxen_adapter *adapter = netdev_priv(dev);
+ u32 fw_major = 0;
+ u32 fw_minor = 0;
+ u32 fw_build = 0;
+
+ strncpy(drvinfo->driver, netxen_nic_driver_name, 32);
+ strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32);
+ fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
+ NETXEN_FW_VERSION_MAJOR));
+ fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
+ NETXEN_FW_VERSION_MINOR));
+ fw_build = readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
+ sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build);
+
+ strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
+ drvinfo->n_stats = NETXEN_NIC_STATS_LEN;
+ drvinfo->testinfo_len = NETXEN_NIC_TEST_LEN;
+ drvinfo->regdump_len = NETXEN_NIC_REGS_LEN;
+ drvinfo->eedump_len = netxen_nic_get_eeprom_len(dev);
+}
+
+static int
+netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
+{
+ struct netxen_adapter *adapter = netdev_priv(dev);
+ struct netxen_board_info *boardinfo = &adapter->ahw.boardcfg;
+
+ /* read which mode */
+ if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
+ ecmd->supported = (SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full |
+ SUPPORTED_1000baseT_Half |
+ SUPPORTED_1000baseT_Full);
+
+ ecmd->advertising = (ADVERTISED_100baseT_Half |
+ ADVERTISED_100baseT_Full |
+ ADVERTISED_1000baseT_Half |
+ ADVERTISED_1000baseT_Full);
+
+ ecmd->port = PORT_TP;
+
+ if (netif_running(dev)) {
+ ecmd->speed = adapter->link_speed;
+ ecmd->duplex = adapter->link_duplex;
+ } else
+ return -EIO; /* link absent */
+ } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
+ ecmd->supported = (SUPPORTED_TP |
+ SUPPORTED_1000baseT_Full |
+ SUPPORTED_10000baseT_Full);
+ ecmd->advertising = (ADVERTISED_TP |
+ ADVERTISED_1000baseT_Full |
+ ADVERTISED_10000baseT_Full);
+ ecmd->port = PORT_TP;
+
+ ecmd->speed = SPEED_10000;
+ ecmd->duplex = DUPLEX_FULL;
+ ecmd->autoneg = AUTONEG_DISABLE;
+ } else
+ return -EIO;
+
+ ecmd->phy_address = adapter->portnum;
+ ecmd->transceiver = XCVR_EXTERNAL;
+
+ switch ((netxen_brdtype_t) boardinfo->board_type) {
+ case NETXEN_BRDTYPE_P2_SB35_4G:
+ case NETXEN_BRDTYPE_P2_SB31_2G:
+ ecmd->supported |= SUPPORTED_Autoneg;
+ ecmd->advertising |= ADVERTISED_Autoneg;
+ case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
+ ecmd->supported |= SUPPORTED_TP;
+ ecmd->advertising |= ADVERTISED_TP;
+ ecmd->port = PORT_TP;
+ ecmd->autoneg = (boardinfo->board_type ==
+ NETXEN_BRDTYPE_P2_SB31_10G_CX4) ?
+ (AUTONEG_DISABLE) : (adapter->link_autoneg);
+ break;
+ case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
+ case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
+ ecmd->supported |= SUPPORTED_MII;
+ ecmd->advertising |= ADVERTISED_MII;
+ ecmd->port = PORT_FIBRE;
+ ecmd->autoneg = AUTONEG_DISABLE;
+ break;
+ case NETXEN_BRDTYPE_P2_SB31_10G:
+ ecmd->supported |= SUPPORTED_FIBRE;
+ ecmd->advertising |= ADVERTISED_FIBRE;
+ ecmd->port = PORT_FIBRE;
+ ecmd->autoneg = AUTONEG_DISABLE;
+ break;
+ default:
+ printk(KERN_ERR "netxen-nic: Unsupported board model %d\n",
+ (netxen_brdtype_t) boardinfo->board_type);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int
+netxen_nic_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
+{
+ struct netxen_adapter *adapter = netdev_priv(dev);
+ __u32 status;
+
+ /* read which mode */
+ if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
+ /* autonegotiation */
+ if (adapter->phy_write
+ && adapter->phy_write(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
+ ecmd->autoneg) != 0)
+ return -EIO;
+ else
+ adapter->link_autoneg = ecmd->autoneg;
+
+ if (adapter->phy_read
+ && adapter->phy_read(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
+ &status) != 0)
+ return -EIO;
+
+ /* speed */
+ switch (ecmd->speed) {
+ case SPEED_10:
+ netxen_set_phy_speed(status, 0);
+ break;
+ case SPEED_100:
+ netxen_set_phy_speed(status, 1);
+ break;
+ case SPEED_1000:
+ netxen_set_phy_speed(status, 2);
+ break;
+ }
+ /* set duplex mode */
+ if (ecmd->duplex == DUPLEX_HALF)
+ netxen_clear_phy_duplex(status);
+ if (ecmd->duplex == DUPLEX_FULL)
+ netxen_set_phy_duplex(status);
+ if (adapter->phy_write
+ && adapter->phy_write(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
+ *((int *)&status)) != 0)
+ return -EIO;
+ else {
+ adapter->link_speed = ecmd->speed;
+ adapter->link_duplex = ecmd->duplex;
+ }
+ } else
+ return -EOPNOTSUPP;
+
+ if (netif_running(dev)) {
+ dev->stop(dev);
+ dev->open(dev);
+ }
+ return 0;
+}
+
+static int netxen_nic_get_regs_len(struct net_device *dev)
+{
+ return NETXEN_NIC_REGS_LEN;
+}
+
+struct netxen_niu_regs {
+ __u32 reg[NETXEN_NIC_REGS_COUNT];
+};
+
+static struct netxen_niu_regs niu_registers[] = {
+ {
+ /* GB Mode */
+ {
+ NETXEN_NIU_GB_SERDES_RESET,
+ NETXEN_NIU_GB0_MII_MODE,
+ NETXEN_NIU_GB1_MII_MODE,
+ NETXEN_NIU_GB2_MII_MODE,
+ NETXEN_NIU_GB3_MII_MODE,
+ NETXEN_NIU_GB0_GMII_MODE,
+ NETXEN_NIU_GB1_GMII_MODE,
+ NETXEN_NIU_GB2_GMII_MODE,
+ NETXEN_NIU_GB3_GMII_MODE,
+ NETXEN_NIU_REMOTE_LOOPBACK,
+ NETXEN_NIU_GB0_HALF_DUPLEX,
+ NETXEN_NIU_GB1_HALF_DUPLEX,
+ NETXEN_NIU_RESET_SYS_FIFOS,
+ NETXEN_NIU_GB_CRC_DROP,
+ NETXEN_NIU_GB_DROP_WRONGADDR,
+ NETXEN_NIU_TEST_MUX_CTL,
+
+ NETXEN_NIU_GB_MAC_CONFIG_0(0),
+ NETXEN_NIU_GB_MAC_CONFIG_1(0),
+ NETXEN_NIU_GB_HALF_DUPLEX_CTRL(0),
+ NETXEN_NIU_GB_MAX_FRAME_SIZE(0),
+ NETXEN_NIU_GB_TEST_REG(0),
+ NETXEN_NIU_GB_MII_MGMT_CONFIG(0),
+ NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
+ NETXEN_NIU_GB_MII_MGMT_ADDR(0),
+ NETXEN_NIU_GB_MII_MGMT_CTRL(0),
+ NETXEN_NIU_GB_MII_MGMT_STATUS(0),
+ NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
+ NETXEN_NIU_GB_INTERFACE_CTRL(0),
+ NETXEN_NIU_GB_INTERFACE_STATUS(0),
+ NETXEN_NIU_GB_STATION_ADDR_0(0),
+ NETXEN_NIU_GB_STATION_ADDR_1(0),
+ -1,
+ }
+ },
+ {
+ /* XG Mode */
+ {
+ NETXEN_NIU_XG_SINGLE_TERM,
+ NETXEN_NIU_XG_DRIVE_HI,
+ NETXEN_NIU_XG_DRIVE_LO,
+ NETXEN_NIU_XG_DTX,
+ NETXEN_NIU_XG_DEQ,
+ NETXEN_NIU_XG_WORD_ALIGN,
+ NETXEN_NIU_XG_RESET,
+ NETXEN_NIU_XG_POWER_DOWN,
+ NETXEN_NIU_XG_RESET_PLL,
+ NETXEN_NIU_XG_SERDES_LOOPBACK,
+ NETXEN_NIU_XG_DO_BYTE_ALIGN,
+ NETXEN_NIU_XG_TX_ENABLE,
+ NETXEN_NIU_XG_RX_ENABLE,
+ NETXEN_NIU_XG_STATUS,
+ NETXEN_NIU_XG_PAUSE_THRESHOLD,
+ NETXEN_NIU_XGE_CONFIG_0,
+ NETXEN_NIU_XGE_CONFIG_1,
+ NETXEN_NIU_XGE_IPG,
+ NETXEN_NIU_XGE_STATION_ADDR_0_HI,
+ NETXEN_NIU_XGE_STATION_ADDR_0_1,
+ NETXEN_NIU_XGE_STATION_ADDR_1_LO,
+ NETXEN_NIU_XGE_STATUS,
+ NETXEN_NIU_XGE_MAX_FRAME_SIZE,
+ NETXEN_NIU_XGE_PAUSE_FRAME_VALUE,
+ NETXEN_NIU_XGE_TX_BYTE_CNT,
+ NETXEN_NIU_XGE_TX_FRAME_CNT,
+ NETXEN_NIU_XGE_RX_BYTE_CNT,
+ NETXEN_NIU_XGE_RX_FRAME_CNT,
+ NETXEN_NIU_XGE_AGGR_ERROR_CNT,
+ NETXEN_NIU_XGE_MULTICAST_FRAME_CNT,
+ NETXEN_NIU_XGE_UNICAST_FRAME_CNT,
+ NETXEN_NIU_XGE_CRC_ERROR_CNT,
+ NETXEN_NIU_XGE_OVERSIZE_FRAME_ERR,
+ NETXEN_NIU_XGE_UNDERSIZE_FRAME_ERR,
+ NETXEN_NIU_XGE_LOCAL_ERROR_CNT,
+ NETXEN_NIU_XGE_REMOTE_ERROR_CNT,
+ NETXEN_NIU_XGE_CONTROL_CHAR_CNT,
+ NETXEN_NIU_XGE_PAUSE_FRAME_CNT,
+ -1,
+ }
+ }
+};
+
+static void
+netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
+{
+ struct netxen_adapter *adapter = netdev_priv(dev);
+ __u32 mode, *regs_buff = p;
+ void __iomem *addr;
+ int i, window;
+
+ memset(p, 0, NETXEN_NIC_REGS_LEN);
+ regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |
+ (adapter->pdev)->device;
+ /* which mode */
+ NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_MODE, ®s_buff[0]);
+ mode = regs_buff[0];
+
+ /* Common registers to all the modes */
+ NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER,
+ ®s_buff[2]);
+ /* GB/XGB Mode */
+ mode = (mode / 2) - 1;
+ window = 0;
+ if (mode <= 1) {
+ for (i = 3; niu_registers[mode].reg[i - 3] != -1; i++) {
+ /* GB: port specific registers */
+ if (mode == 0 && i >= 19)
+ window = physical_port[adapter->portnum] *
+ NETXEN_NIC_PORT_WINDOW;
+
+ NETXEN_NIC_LOCKED_READ_REG(niu_registers[mode].
+ reg[i - 3] + window,
+ ®s_buff[i]);
+ }
+
+ }
+}
+
+static u32 netxen_nic_test_link(struct net_device *dev)
+{
+ struct netxen_adapter *adapter = netdev_priv(dev);
+ __u32 status;
+ int val;
+
+ /* read which mode */
+ if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
+ if (adapter->phy_read
+ && adapter->phy_read(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
+ &status) != 0)
+ return -EIO;
+ else {
+ val = netxen_get_phy_link(status);
+ return !val;
+ }
+ } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
+ val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE));
+ return (val == XG_LINK_UP) ? 0 : 1;
+ }
+ return -EIO;
+}
+
+static int
+netxen_nic_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
+ u8 * bytes)
+{
+ struct netxen_adapter *adapter = netdev_priv(dev);
+ int offset;
+ int ret;
+
+ if (eeprom->len == 0)
+ return -EINVAL;
+
+ eeprom->magic = (adapter->pdev)->vendor |
+ ((adapter->pdev)->device << 16);
+ offset = eeprom->offset;
+
+ ret = netxen_rom_fast_read_words(adapter, offset, bytes,
+ eeprom->len);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int
+netxen_nic_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
+ u8 * bytes)
+{
+ struct netxen_adapter *adapter = netdev_priv(dev);
+ int offset = eeprom->offset;
+ static int flash_start;
+ static int ready_to_flash;
+ int ret;
+
+ if (flash_start == 0) {
+ netxen_halt_pegs(adapter);
+ ret = netxen_flash_unlock(adapter);
+ if (ret < 0) {
+ printk(KERN_ERR "%s: Flash unlock failed.\n",
+ netxen_nic_driver_name);
+ return ret;
+ }
+ printk(KERN_INFO "%s: flash unlocked. \n",
+ netxen_nic_driver_name);
+ last_schedule_time = jiffies;
+ ret = netxen_flash_erase_secondary(adapter);
+ if (ret != FLASH_SUCCESS) {
+ printk(KERN_ERR "%s: Flash erase failed.\n",
+ netxen_nic_driver_name);
+ return ret;
+ }
+ printk(KERN_INFO "%s: secondary flash erased successfully.\n",
+ netxen_nic_driver_name);
+ flash_start = 1;
+ return 0;
+ }
+
+ if (offset == BOOTLD_START) {
+ ret = netxen_flash_erase_primary(adapter);
+ if (ret != FLASH_SUCCESS) {
+ printk(KERN_ERR "%s: Flash erase failed.\n",
+ netxen_nic_driver_name);
+ return ret;
+ }
+
+ ret = netxen_rom_se(adapter, USER_START);
+ if (ret != FLASH_SUCCESS)
+ return ret;
+ ret = netxen_rom_se(adapter, FIXED_START);
+ if (ret != FLASH_SUCCESS)
+ return ret;
+
+ printk(KERN_INFO "%s: primary flash erased successfully\n",
+ netxen_nic_driver_name);
+
+ ret = netxen_backup_crbinit(adapter);
+ if (ret != FLASH_SUCCESS) {
+ printk(KERN_ERR "%s: CRBinit backup failed.\n",
+ netxen_nic_driver_name);
+ return ret;
+ }
+ printk(KERN_INFO "%s: CRBinit backup done.\n",
+ netxen_nic_driver_name);
+ ready_to_flash = 1;
+ }
+
+ if (!ready_to_flash) {
+ printk(KERN_ERR "%s: Invalid write sequence, returning...\n",
+ netxen_nic_driver_name);
+ return -EINVAL;
+ }
+
+ return netxen_rom_fast_write_words(adapter, offset, bytes, eeprom->len);
+}
+
+static void
+netxen_nic_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ring)
+{
+ struct netxen_adapter *adapter = netdev_priv(dev);
+ int i;
+
+ ring->rx_pending = 0;
+ ring->rx_jumbo_pending = 0;
+ for (i = 0; i < MAX_RCV_CTX; ++i) {
+ ring->rx_pending += adapter->recv_ctx[i].
+ rcv_desc[RCV_DESC_NORMAL_CTXID].rcv_pending;
+ ring->rx_jumbo_pending += adapter->recv_ctx[i].
+ rcv_desc[RCV_DESC_JUMBO_CTXID].rcv_pending;
+ }
+
+ ring->rx_max_pending = adapter->max_rx_desc_count;
+ ring->tx_max_pending = adapter->max_tx_desc_count;
+ ring->rx_jumbo_max_pending = adapter->max_jumbo_rx_desc_count;
+ ring->rx_mini_max_pending = 0;
+ ring->rx_mini_pending = 0;
+ ring->rx_jumbo_pending = 0;
+}
+
+static void
+netxen_nic_get_pauseparam(struct net_device *dev,
+ struct ethtool_pauseparam *pause)
+{
+ struct netxen_adapter *adapter = netdev_priv(dev);
+ __u32 val;
+ int port = physical_port[adapter->portnum];
+
+ if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
+ if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
+ return;
+ /* get flow control settings */
+ netxen_nic_read_w0(adapter,NETXEN_NIU_GB_MAC_CONFIG_0(port),
+ &val);
+ pause->rx_pause = netxen_gb_get_rx_flowctl(val);
+ netxen_nic_read_w0(adapter, NETXEN_NIU_GB_PAUSE_CTL, &val);
+ switch (port) {
+ case 0:
+ pause->tx_pause = !(netxen_gb_get_gb0_mask(val));
+ break;
+ case 1:
+ pause->tx_pause = !(netxen_gb_get_gb1_mask(val));
+ break;
+ case 2:
+ pause->tx_pause = !(netxen_gb_get_gb2_mask(val));
+ break;
+ case 3:
+ default:
+ pause->tx_pause = !(netxen_gb_get_gb3_mask(val));
+ break;
+ }
+ } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
+ if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS))
+ return;
+ pause->rx_pause = 1;
+ netxen_nic_read_w0(adapter, NETXEN_NIU_XG_PAUSE_CTL, &val);
+ if (port == 0)
+ pause->tx_pause = !(netxen_xg_get_xg0_mask(val));
+ else
+ pause->tx_pause = !(netxen_xg_get_xg1_mask(val));
+ } else {
+ printk(KERN_ERR"%s: Unknown board type: %x\n",
+ netxen_nic_driver_name, adapter->ahw.board_type);
+ }
+}
+
+static int
+netxen_nic_set_pauseparam(struct net_device *dev,
+ struct ethtool_pauseparam *pause)
+{
+ struct netxen_adapter *adapter = netdev_priv(dev);
+ __u32 val;
+ int port = physical_port[adapter->portnum];
+ /* read mode */
+ if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
+ if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
+ return -EIO;
+ /* set flow control */
+ netxen_nic_read_w0(adapter,
+ NETXEN_NIU_GB_MAC_CONFIG_0(port), &val);
+
+ if (pause->rx_pause)
+ netxen_gb_rx_flowctl(val);
+ else
+ netxen_gb_unset_rx_flowctl(val);
+
+ netxen_nic_write_w0(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
+ val);
+ /* set autoneg */
+ netxen_nic_read_w0(adapter, NETXEN_NIU_GB_PAUSE_CTL, &val);
+ switch (port) {
+ case 0:
+ if (pause->tx_pause)
+ netxen_gb_unset_gb0_mask(val);
+ else
+ netxen_gb_set_gb0_mask(val);
+ break;
+ case 1:
+ if (pause->tx_pause)
+ netxen_gb_unset_gb1_mask(val);
+ else
+ netxen_gb_set_gb1_mask(val);
+ break;
+ case 2:
+ if (pause->tx_pause)
+ netxen_gb_unset_gb2_mask(val);
+ else
+ netxen_gb_set_gb2_mask(val);
+ break;
+ case 3:
+ default:
+ if (pause->tx_pause)
+ netxen_gb_unset_gb3_mask(val);
+ else
+ netxen_gb_set_gb3_mask(val);
+ break;
+ }
+ netxen_nic_write_w0(adapter, NETXEN_NIU_GB_PAUSE_CTL, val);
+ } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
+ if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS))
+ return -EIO;
+ netxen_nic_read_w0(adapter, NETXEN_NIU_XG_PAUSE_CTL, &val);
+ if (port == 0) {
+ if (pause->tx_pause)
+ netxen_xg_unset_xg0_mask(val);
+ else
+ netxen_xg_set_xg0_mask(val);
+ } else {
+ if (pause->tx_pause)
+ netxen_xg_unset_xg1_mask(val);
+ else
+ netxen_xg_set_xg1_mask(val);
+ }
+ netxen_nic_write_w0(adapter, NETXEN_NIU_XG_PAUSE_CTL, val);
+ } else {
+ printk(KERN_ERR "%s: Unknown board type: %x\n",
+ netxen_nic_driver_name,
+ adapter->ahw.board_type);
+ }
+ return 0;
+}
+
+static int netxen_nic_reg_test(struct net_device *dev)
+{
+ struct netxen_adapter *adapter = netdev_priv(dev);
+ u32 data_read, data_written;
+
+ netxen_nic_read_w0(adapter, NETXEN_PCIX_PH_REG(0), &data_read);
+ if ((data_read & 0xffff) != PHAN_VENDOR_ID)
+ return 1;
+
+ data_written = (u32)0xa5a5a5a5;
+
+ netxen_nic_reg_write(adapter, CRB_SCRATCHPAD_TEST, data_written);
+ data_read = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_SCRATCHPAD_TEST));
+ if (data_written != data_read)
+ return 1;
+
+ return 0;
+}
+
+static int netxen_nic_diag_test_count(struct net_device *dev)
+{
+ return NETXEN_NIC_TEST_LEN;
+}
+
+static void
+netxen_nic_diag_test(struct net_device *dev, struct ethtool_test *eth_test,
+ u64 * data)
+{
+ memset(data, 0, sizeof(uint64_t) * NETXEN_NIC_TEST_LEN);
+ if ((data[0] = netxen_nic_reg_test(dev)))
+ eth_test->flags |= ETH_TEST_FL_FAILED;
+ /* link test */
+ if ((data[1] = (u64) netxen_nic_test_link(dev)))
+ eth_test->flags |= ETH_TEST_FL_FAILED;
+}
+
+static void
+netxen_nic_get_strings(struct net_device *dev, u32 stringset, u8 * data)
+{
+ int index;
+
+ switch (stringset) {
+ case ETH_SS_TEST:
+ memcpy(data, *netxen_nic_gstrings_test,
+ NETXEN_NIC_TEST_LEN * ETH_GSTRING_LEN);
+ break;
+ case ETH_SS_STATS:
+ for (index = 0; index < NETXEN_NIC_STATS_LEN; index++) {
+ memcpy(data + index * ETH_GSTRING_LEN,
+ netxen_nic_gstrings_stats[index].stat_string,
+ ETH_GSTRING_LEN);
+ }
+ break;
+ }
+}
+
+static int netxen_nic_get_stats_count(struct net_device *dev)
+{
+ return NETXEN_NIC_STATS_LEN;
+}
+
+static void
+netxen_nic_get_ethtool_stats(struct net_device *dev,
+ struct ethtool_stats *stats, u64 * data)
+{
+ struct netxen_adapter *adapter = netdev_priv(dev);
+ int index;
+
+ for (index = 0; index < NETXEN_NIC_STATS_LEN; index++) {
+ char *p =
+ (char *)adapter +
+ netxen_nic_gstrings_stats[index].stat_offset;
+ data[index] =
+ (netxen_nic_gstrings_stats[index].sizeof_stat ==
+ sizeof(u64)) ? *(u64 *) p : *(u32 *) p;
+ }
+}
+
+struct ethtool_ops netxen_nic_ethtool_ops = {
+ .get_settings = netxen_nic_get_settings,
+ .set_settings = netxen_nic_set_settings,
+ .get_drvinfo = netxen_nic_get_drvinfo,
+ .get_regs_len = netxen_nic_get_regs_len,
+ .get_regs = netxen_nic_get_regs,
+ .get_link = ethtool_op_get_link,
+ .get_eeprom_len = netxen_nic_get_eeprom_len,
+ .get_eeprom = netxen_nic_get_eeprom,
+ .set_eeprom = netxen_nic_set_eeprom,
+ .get_ringparam = netxen_nic_get_ringparam,
+ .get_pauseparam = netxen_nic_get_pauseparam,
+ .set_pauseparam = netxen_nic_set_pauseparam,
+ .get_tx_csum = ethtool_op_get_tx_csum,
+ .set_tx_csum = ethtool_op_set_tx_csum,
+ .get_sg = ethtool_op_get_sg,
+ .set_sg = ethtool_op_set_sg,
+ .get_tso = ethtool_op_get_tso,
+ .set_tso = ethtool_op_set_tso,
+ .self_test_count = netxen_nic_diag_test_count,
+ .self_test = netxen_nic_diag_test,
+ .get_strings = netxen_nic_get_strings,
+ .get_stats_count = netxen_nic_get_stats_count,
+ .get_ethtool_stats = netxen_nic_get_ethtool_stats,
+};
--- linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_hw.c.rhel5
+++ linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_hw.c
@@ -0,0 +1,1186 @@
+/*
+ * Copyright (C) 2003 - 2006 NetXen, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
+ * MA 02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.
+ *
+ * Contact Information:
+ * info@netxen.com
+ * NetXen,
+ * 3965 Freedom Circle, Fourth floor,
+ * Santa Clara, CA 95054
+ *
+ *
+ * Source file for NIC routines to access the Phantom hardware
+ *
+ */
+
+#include "netxen_nic.h"
+#include "netxen_nic_hw.h"
+#define DEFINE_GLOBAL_RECV_CRB
+#include "netxen_nic_phan_reg.h"
+
+struct netxen_recv_crb recv_crb_registers[] = {
+ /*
+ * Instance 0.
+ */
+ {
+ /* rcv_desc_crb: */
+ {
+ {
+ /* crb_rcv_producer_offset: */
+ NETXEN_NIC_REG(0x100),
+ /* crb_rcv_consumer_offset: */
+ NETXEN_NIC_REG(0x104),
+ /* crb_gloablrcv_ring: */
+ NETXEN_NIC_REG(0x108),
+ /* crb_rcv_ring_size */
+ NETXEN_NIC_REG(0x10c),
+
+ },
+ /* Jumbo frames */
+ {
+ /* crb_rcv_producer_offset: */
+ NETXEN_NIC_REG(0x110),
+ /* crb_rcv_consumer_offset: */
+ NETXEN_NIC_REG(0x114),
+ /* crb_gloablrcv_ring: */
+ NETXEN_NIC_REG(0x118),
+ /* crb_rcv_ring_size */
+ NETXEN_NIC_REG(0x11c),
+ },
+ /* LRO */
+ {
+ /* crb_rcv_producer_offset: */
+ NETXEN_NIC_REG(0x120),
+ /* crb_rcv_consumer_offset: */
+ NETXEN_NIC_REG(0x124),
+ /* crb_gloablrcv_ring: */
+ NETXEN_NIC_REG(0x128),
+ /* crb_rcv_ring_size */
+ NETXEN_NIC_REG(0x12c),
+ }
+ },
+ /* crb_rcvstatus_ring: */
+ NETXEN_NIC_REG(0x130),
+ /* crb_rcv_status_producer: */
+ NETXEN_NIC_REG(0x134),
+ /* crb_rcv_status_consumer: */
+ NETXEN_NIC_REG(0x138),
+ /* crb_rcvpeg_state: */
+ NETXEN_NIC_REG(0x13c),
+ /* crb_status_ring_size */
+ NETXEN_NIC_REG(0x140),
+
+ },
+ /*
+ * Instance 1,
+ */
+ {
+ /* rcv_desc_crb: */
+ {
+ {
+ /* crb_rcv_producer_offset: */
+ NETXEN_NIC_REG(0x144),
+ /* crb_rcv_consumer_offset: */
+ NETXEN_NIC_REG(0x148),
+ /* crb_globalrcv_ring: */
+ NETXEN_NIC_REG(0x14c),
+ /* crb_rcv_ring_size */
+ NETXEN_NIC_REG(0x150),
+
+ },
+ /* Jumbo frames */
+ {
+ /* crb_rcv_producer_offset: */
+ NETXEN_NIC_REG(0x154),
+ /* crb_rcv_consumer_offset: */
+ NETXEN_NIC_REG(0x158),
+ /* crb_globalrcv_ring: */
+ NETXEN_NIC_REG(0x15c),
+ /* crb_rcv_ring_size */
+ NETXEN_NIC_REG(0x160),
+ },
+ /* LRO */
+ {
+ /* crb_rcv_producer_offset: */
+ NETXEN_NIC_REG(0x164),
+ /* crb_rcv_consumer_offset: */
+ NETXEN_NIC_REG(0x168),
+ /* crb_globalrcv_ring: */
+ NETXEN_NIC_REG(0x16c),
+ /* crb_rcv_ring_size */
+ NETXEN_NIC_REG(0x170),
+ }
+
+ },
+ /* crb_rcvstatus_ring: */
+ NETXEN_NIC_REG(0x174),
+ /* crb_rcv_status_producer: */
+ NETXEN_NIC_REG(0x178),
+ /* crb_rcv_status_consumer: */
+ NETXEN_NIC_REG(0x17c),
+ /* crb_rcvpeg_state: */
+ NETXEN_NIC_REG(0x180),
+ /* crb_status_ring_size */
+ NETXEN_NIC_REG(0x184),
+ },
+ /*
+ * Instance 2,
+ */
+ {
+ {
+ {
+ /* crb_rcv_producer_offset: */
+ NETXEN_NIC_REG(0x1d8),
+ /* crb_rcv_consumer_offset: */
+ NETXEN_NIC_REG(0x1dc),
+ /* crb_gloablrcv_ring: */
+ NETXEN_NIC_REG(0x1f0),
+ /* crb_rcv_ring_size */
+ NETXEN_NIC_REG(0x1f4),
+ },
+ /* Jumbo frames */
+ {
+ /* crb_rcv_producer_offset: */
+ NETXEN_NIC_REG(0x1f8),
+ /* crb_rcv_consumer_offset: */
+ NETXEN_NIC_REG(0x1fc),
+ /* crb_gloablrcv_ring: */
+ NETXEN_NIC_REG(0x200),
+ /* crb_rcv_ring_size */
+ NETXEN_NIC_REG(0x204),
+ },
+ /* LRO */
+ {
+ /* crb_rcv_producer_offset: */
+ NETXEN_NIC_REG(0x208),
+ /* crb_rcv_consumer_offset: */
+ NETXEN_NIC_REG(0x20c),
+ /* crb_gloablrcv_ring: */
+ NETXEN_NIC_REG(0x210),
+ /* crb_rcv_ring_size */
+ NETXEN_NIC_REG(0x214),
+ }
+ },
+ /* crb_rcvstatus_ring: */
+ NETXEN_NIC_REG(0x218),
+ /* crb_rcv_status_producer: */
+ NETXEN_NIC_REG(0x21c),
+ /* crb_rcv_status_consumer: */
+ NETXEN_NIC_REG(0x220),
+ /* crb_rcvpeg_state: */
+ NETXEN_NIC_REG(0x224),
+ /* crb_status_ring_size */
+ NETXEN_NIC_REG(0x228),
+ },
+ /*
+ * Instance 3,
+ */
+ {
+ {
+ {
+ /* crb_rcv_producer_offset: */
+ NETXEN_NIC_REG(0x22c),
+ /* crb_rcv_consumer_offset: */
+ NETXEN_NIC_REG(0x230),
+ /* crb_gloablrcv_ring: */
+ NETXEN_NIC_REG(0x234),
+ /* crb_rcv_ring_size */
+ NETXEN_NIC_REG(0x238),
+ },
+ /* Jumbo frames */
+ {
+ /* crb_rcv_producer_offset: */
+ NETXEN_NIC_REG(0x23c),
+ /* crb_rcv_consumer_offset: */
+ NETXEN_NIC_REG(0x240),
+ /* crb_gloablrcv_ring: */
+ NETXEN_NIC_REG(0x244),
+ /* crb_rcv_ring_size */
+ NETXEN_NIC_REG(0x248),
+ },
+ /* LRO */
+ {
+ /* crb_rcv_producer_offset: */
+ NETXEN_NIC_REG(0x24c),
+ /* crb_rcv_consumer_offset: */
+ NETXEN_NIC_REG(0x250),
+ /* crb_gloablrcv_ring: */
+ NETXEN_NIC_REG(0x254),
+ /* crb_rcv_ring_size */
+ NETXEN_NIC_REG(0x258),
+ }
+ },
+ /* crb_rcvstatus_ring: */
+ NETXEN_NIC_REG(0x25c),
+ /* crb_rcv_status_producer: */
+ NETXEN_NIC_REG(0x260),
+ /* crb_rcv_status_consumer: */
+ NETXEN_NIC_REG(0x264),
+ /* crb_rcvpeg_state: */
+ NETXEN_NIC_REG(0x268),
+ /* crb_status_ring_size */
+ NETXEN_NIC_REG(0x26c),
+ },
+};
+
+u64 ctx_addr_sig_regs[][3] = {
+ {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
+ {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
+ {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
+ {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
+};
+
+
+
+/* PCI Windowing for DDR regions. */
+
+#define ADDR_IN_RANGE(addr, low, high) \
+ (((addr) <= (high)) && ((addr) >= (low)))
+
+#define NETXEN_FLASH_BASE (BOOTLD_START)
+#define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
+#define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
+#define NETXEN_MIN_MTU 64
+#define NETXEN_ETH_FCS_SIZE 4
+#define NETXEN_ENET_HEADER_SIZE 14
+#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
+#define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
+#define NETXEN_NIU_HDRSIZE (0x1 << 6)
+#define NETXEN_NIU_TLRSIZE (0x1 << 5)
+
+#define lower32(x) ((u32)((x) & 0xffffffff))
+#define upper32(x) \
+ ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
+
+#define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
+#define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
+#define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
+#define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
+
+#define NETXEN_NIC_WINDOW_MARGIN 0x100000
+
+unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
+ unsigned long long addr);
+void netxen_free_hw_resources(struct netxen_adapter *adapter);
+
+int netxen_nic_set_mac(struct net_device *netdev, void *p)
+{
+ struct netxen_adapter *adapter = netdev_priv(netdev);
+ struct sockaddr *addr = p;
+
+ if (netif_running(netdev))
+ return -EBUSY;
+
+ if (!is_valid_ether_addr(addr->sa_data))
+ return -EADDRNOTAVAIL;
+
+ DPRINTK(INFO, "valid ether addr\n");
+ memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
+
+ if (adapter->macaddr_set)
+ adapter->macaddr_set(adapter, addr->sa_data);
+
+ return 0;
+}
+
+/*
+ * netxen_nic_set_multi - Multicast
+ */
+void netxen_nic_set_multi(struct net_device *netdev)
+{
+ struct netxen_adapter *adapter = netdev_priv(netdev);
+ struct dev_mc_list *mc_ptr;
+
+ mc_ptr = netdev->mc_list;
+ if (netdev->flags & IFF_PROMISC) {
+ if (adapter->set_promisc)
+ adapter->set_promisc(adapter,
+ NETXEN_NIU_PROMISC_MODE);
+ } else {
+ if (adapter->unset_promisc)
+ adapter->unset_promisc(adapter,
+ NETXEN_NIU_NON_PROMISC_MODE);
+ }
+}
+
+/*
+ * netxen_nic_change_mtu - Change the Maximum Transfer Unit
+ * @returns 0 on success, negative on failure
+ */
+int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
+{
+ struct netxen_adapter *adapter = netdev_priv(netdev);
+ int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
+
+ if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
+ printk(KERN_ERR "%s: %s %d is not supported.\n",
+ netxen_nic_driver_name, netdev->name, mtu);
+ return -EINVAL;
+ }
+
+ if (adapter->set_mtu)
+ adapter->set_mtu(adapter, mtu);
+ netdev->mtu = mtu;
+
+ return 0;
+}
+
+/*
+ * check if the firmware has been downloaded and ready to run and
+ * setup the address for the descriptors in the adapter
+ */
+int netxen_nic_hw_resources(struct netxen_adapter *adapter)
+{
+ struct netxen_hardware_context *hw = &adapter->ahw;
+ u32 state = 0;
+ void *addr;
+ int loops = 0, err = 0;
+ int ctx, ring;
+ struct netxen_recv_context *recv_ctx;
+ struct netxen_rcv_desc_ctx *rcv_desc;
+ int func_id = adapter->portnum;
+
+ DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
+ PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
+ DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
+ pci_base_offset(adapter, NETXEN_CRB_CAM));
+ DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
+ pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
+
+
+ for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
+ DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
+ loops = 0;
+ state = 0;
+ /* Window 1 call */
+ state = readl(NETXEN_CRB_NORMALIZE(adapter,
+ recv_crb_registers[ctx].
+ crb_rcvpeg_state));
+ while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
+ udelay(100);
+ /* Window 1 call */
+ state = readl(NETXEN_CRB_NORMALIZE(adapter,
+ recv_crb_registers
+ [ctx].
+ crb_rcvpeg_state));
+ loops++;
+ }
+ if (loops >= 20) {
+ printk(KERN_ERR "Rcv Peg initialization not complete:"
+ "%x.\n", state);
+ err = -EIO;
+ return err;
+ }
+ }
+ DPRINTK(INFO, "Recieve Peg ready too. starting stuff\n");
+
+ addr = netxen_alloc(adapter->ahw.pdev,
+ sizeof(struct netxen_ring_ctx) +
+ sizeof(uint32_t),
+ (dma_addr_t *) & adapter->ctx_desc_phys_addr,
+ &adapter->ctx_desc_pdev);
+
+ printk(KERN_INFO "ctx_desc_phys_addr: 0x%llx\n",
+ (unsigned long long) adapter->ctx_desc_phys_addr);
+ if (addr == NULL) {
+ DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
+ err = -ENOMEM;
+ return err;
+ }
+ memset(addr, 0, sizeof(struct netxen_ring_ctx));
+ adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
+ adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum);
+ adapter->ctx_desc->cmd_consumer_offset =
+ cpu_to_le64(adapter->ctx_desc_phys_addr +
+ sizeof(struct netxen_ring_ctx));
+ adapter->cmd_consumer = (uint32_t *) (((char *)addr) +
+ sizeof(struct netxen_ring_ctx));
+
+ addr = netxen_alloc(adapter->ahw.pdev,
+ sizeof(struct cmd_desc_type0) *
+ adapter->max_tx_desc_count,
+ (dma_addr_t *) & hw->cmd_desc_phys_addr,
+ &adapter->ahw.cmd_desc_pdev);
+ printk(KERN_INFO "cmd_desc_phys_addr: 0x%llx\n",
+ (unsigned long long) hw->cmd_desc_phys_addr);
+
+ if (addr == NULL) {
+ DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
+ netxen_free_hw_resources(adapter);
+ return -ENOMEM;
+ }
+
+ adapter->ctx_desc->cmd_ring_addr =
+ cpu_to_le64(hw->cmd_desc_phys_addr);
+ adapter->ctx_desc->cmd_ring_size =
+ cpu_to_le32(adapter->max_tx_desc_count);
+
+ hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
+
+ for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
+ recv_ctx = &adapter->recv_ctx[ctx];
+
+ for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
+ rcv_desc = &recv_ctx->rcv_desc[ring];
+ addr = netxen_alloc(adapter->ahw.pdev,
+ RCV_DESC_RINGSIZE,
+ &rcv_desc->phys_addr,
+ &rcv_desc->phys_pdev);
+ if (addr == NULL) {
+ DPRINTK(ERR, "bad return from "
+ "pci_alloc_consistent\n");
+ netxen_free_hw_resources(adapter);
+ err = -ENOMEM;
+ return err;
+ }
+ rcv_desc->desc_head = (struct rcv_desc *)addr;
+ adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
+ cpu_to_le64(rcv_desc->phys_addr);
+ adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
+ cpu_to_le32(rcv_desc->max_rx_desc_count);
+ }
+
+ addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
+ &recv_ctx->rcv_status_desc_phys_addr,
+ &recv_ctx->rcv_status_desc_pdev);
+ if (addr == NULL) {
+ DPRINTK(ERR, "bad return from"
+ " pci_alloc_consistent\n");
+ netxen_free_hw_resources(adapter);
+ err = -ENOMEM;
+ return err;
+ }
+ recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
+ adapter->ctx_desc->sts_ring_addr =
+ cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
+ adapter->ctx_desc->sts_ring_size =
+ cpu_to_le32(adapter->max_rx_desc_count);
+
+ }
+ /* Window = 1 */
+
+ writel(lower32(adapter->ctx_desc_phys_addr),
+ NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id)));
+ writel(upper32(adapter->ctx_desc_phys_addr),
+ NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id)));
+ writel(NETXEN_CTX_SIGNATURE | func_id,
+ NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id)));
+ return err;
+}
+
+void netxen_free_hw_resources(struct netxen_adapter *adapter)
+{
+ struct netxen_recv_context *recv_ctx;
+ struct netxen_rcv_desc_ctx *rcv_desc;
+ int ctx, ring;
+
+ if (adapter->ctx_desc != NULL) {
+ pci_free_consistent(adapter->ctx_desc_pdev,
+ sizeof(struct netxen_ring_ctx) +
+ sizeof(uint32_t),
+ adapter->ctx_desc,
+ adapter->ctx_desc_phys_addr);
+ adapter->ctx_desc = NULL;
+ }
+
+ if (adapter->ahw.cmd_desc_head != NULL) {
+ pci_free_consistent(adapter->ahw.cmd_desc_pdev,
+ sizeof(struct cmd_desc_type0) *
+ adapter->max_tx_desc_count,
+ adapter->ahw.cmd_desc_head,
+ adapter->ahw.cmd_desc_phys_addr);
+ adapter->ahw.cmd_desc_head = NULL;
+ }
+
+ for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
+ recv_ctx = &adapter->recv_ctx[ctx];
+ for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
+ rcv_desc = &recv_ctx->rcv_desc[ring];
+
+ if (rcv_desc->desc_head != NULL) {
+ pci_free_consistent(rcv_desc->phys_pdev,
+ RCV_DESC_RINGSIZE,
+ rcv_desc->desc_head,
+ rcv_desc->phys_addr);
+ rcv_desc->desc_head = NULL;
+ }
+ }
+
+ if (recv_ctx->rcv_status_desc_head != NULL) {
+ pci_free_consistent(recv_ctx->rcv_status_desc_pdev,
+ STATUS_DESC_RINGSIZE,
+ recv_ctx->rcv_status_desc_head,
+ recv_ctx->
+ rcv_status_desc_phys_addr);
+ recv_ctx->rcv_status_desc_head = NULL;
+ }
+ }
+}
+
+void netxen_tso_check(struct netxen_adapter *adapter,
+ struct cmd_desc_type0 *desc, struct sk_buff *skb)
+{
+ if (desc->mss) {
+ desc->total_hdr_length = sizeof(struct ethhdr) +
+ ((skb->nh.iph)->ihl * sizeof(u32)) +
+ ((skb->h.th)->doff * sizeof(u32));
+ netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
+ } else if (skb->ip_summed == CHECKSUM_HW) {
+ if (skb->nh.iph->protocol == IPPROTO_TCP) {
+ netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
+ } else if (skb->nh.iph->protocol == IPPROTO_UDP) {
+ netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
+ } else {
+ return;
+ }
+ }
+ desc->tcp_hdr_offset = skb->h.raw - skb->data;
+ desc->ip_hdr_offset = skb->nh.raw - skb->data;
+}
+
+int netxen_is_flash_supported(struct netxen_adapter *adapter)
+{
+ const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
+ int addr, val01, val02, i, j;
+
+ /* if the flash size less than 4Mb, make huge war cry and die */
+ for (j = 1; j < 4; j++) {
+ addr = j * NETXEN_NIC_WINDOW_MARGIN;
+ for (i = 0; i < (sizeof(locs) / sizeof(locs[0])); i++) {
+ if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
+ && netxen_rom_fast_read(adapter, (addr + locs[i]),
+ &val02) == 0) {
+ if (val01 == val02)
+ return -1;
+ } else
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
+ int size, u32 * buf)
+{
+ int i, addr;
+ u32 *ptr32;
+
+ addr = base;
+ ptr32 = buf;
+ for (i = 0; i < size / sizeof(u32); i++) {
+ if (netxen_rom_fast_read(adapter, addr, ptr32) == -1)
+ return -1;
+ *ptr32 = cpu_to_le32(*ptr32);
+ ptr32++;
+ addr += sizeof(u32);
+ }
+ if ((char *)buf + size > (char *)ptr32) {
+ u32 local;
+
+ if (netxen_rom_fast_read(adapter, addr, &local) == -1)
+ return -1;
+ local = cpu_to_le32(local);
+ memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
+ }
+
+ return 0;
+}
+
+int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[])
+{
+ u32 *pmac = (u32 *) & mac[0];
+
+ if (netxen_get_flash_block(adapter,
+ USER_START +
+ offsetof(struct netxen_new_user_info,
+ mac_addr),
+ FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
+ return -1;
+ }
+ if (*mac == ~0ULL) {
+ if (netxen_get_flash_block(adapter,
+ USER_START_OLD +
+ offsetof(struct netxen_user_old_info,
+ mac_addr),
+ FLASH_NUM_PORTS * sizeof(u64),
+ pmac) == -1)
+ return -1;
+ if (*mac == ~0ULL)
+ return -1;
+ }
+ return 0;
+}
+
+/*
+ * Changes the CRB window to the specified window.
+ */
+void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
+{
+ void __iomem *offset;
+ u32 tmp;
+ int count = 0;
+
+ if (adapter->curr_window == wndw)
+ return;
+ switch(adapter->ahw.pci_func) {
+ case 0:
+ offset = PCI_OFFSET_SECOND_RANGE(adapter,
+ NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
+ break;
+ case 1:
+ offset = PCI_OFFSET_SECOND_RANGE(adapter,
+ NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1));
+ break;
+ case 2:
+ offset = PCI_OFFSET_SECOND_RANGE(adapter,
+ NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2));
+ break;
+ case 3:
+ offset = PCI_OFFSET_SECOND_RANGE(adapter,
+ NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3));
+ break;
+ default:
+ printk(KERN_INFO "Changing the window for PCI function"
+ "%d\n", adapter->ahw.pci_func);
+ offset = PCI_OFFSET_SECOND_RANGE(adapter,
+ NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
+ break;
+ }
+ /*
+ * Move the CRB window.
+ * We need to write to the "direct access" region of PCI
+ * to avoid a race condition where the window register has
+ * not been successfully written across CRB before the target
+ * register address is received by PCI. The direct region bypasses
+ * the CRB bus.
+ */
+
+ if (wndw & 0x1)
+ wndw = NETXEN_WINDOW_ONE;
+
+ writel(wndw, offset);
+
+ /* MUST make sure window is set before we forge on... */
+ while ((tmp = readl(offset)) != wndw) {
+ printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
+ "registered properly: 0x%08x.\n",
+ netxen_nic_driver_name, __FUNCTION__, tmp);
+ mdelay(1);
+ if (count >= 10)
+ break;
+ count++;
+ }
+
+ if (wndw == NETXEN_WINDOW_ONE)
+ adapter->curr_window = 1;
+ else
+ adapter->curr_window = 0;
+}
+
+void netxen_load_firmware(struct netxen_adapter *adapter)
+{
+ int i;
+ u32 data, size = 0;
+ u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
+ u64 off;
+ void __iomem *addr;
+
+ size = NETXEN_FIRMWARE_LEN;
+ writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
+
+ for (i = 0; i < size; i++) {
+ if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) {
+ DPRINTK(ERR,
+ "Error in netxen_rom_fast_read(). Will skip"
+ "loading flash image\n");
+ return;
+ }
+ off = netxen_nic_pci_set_window(adapter, memaddr);
+ addr = pci_base_offset(adapter, off);
+ writel(data, addr);
+ flashaddr += 4;
+ memaddr += 4;
+ }
+ udelay(100);
+ /* make sure Casper is powered on */
+ writel(0x3fff,
+ NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
+ writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
+
+ udelay(100);
+}
+
+int
+netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
+ int len)
+{
+ void __iomem *addr;
+
+ if (ADDR_IN_WINDOW1(off)) {
+ addr = NETXEN_CRB_NORMALIZE(adapter, off);
+ } else { /* Window 0 */
+ addr = pci_base_offset(adapter, off);
+ netxen_nic_pci_change_crbwindow(adapter, 0);
+ }
+
+ DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
+ " data %llx len %d\n",
+ pci_base(adapter, off), off, addr,
+ *(unsigned long long *)data, len);
+ if (!addr) {
+ netxen_nic_pci_change_crbwindow(adapter, 1);
+ return 1;
+ }
+
+ switch (len) {
+ case 1:
+ writeb(*(u8 *) data, addr);
+ break;
+ case 2:
+ writew(*(u16 *) data, addr);
+ break;
+ case 4:
+ writel(*(u32 *) data, addr);
+ break;
+ case 8:
+ writeq(*(u64 *) data, addr);
+ break;
+ default:
+ DPRINTK(INFO,
+ "writing data %lx to offset %llx, num words=%d\n",
+ *(unsigned long *)data, off, (len >> 3));
+
+ netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
+ (len >> 3));
+ break;
+ }
+ if (!ADDR_IN_WINDOW1(off))
+ netxen_nic_pci_change_crbwindow(adapter, 1);
+
+ return 0;
+}
+
+int
+netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
+ int len)
+{
+ void __iomem *addr;
+
+ if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
+ addr = NETXEN_CRB_NORMALIZE(adapter, off);
+ } else { /* Window 0 */
+ addr = pci_base_offset(adapter, off);
+ netxen_nic_pci_change_crbwindow(adapter, 0);
+ }
+
+ DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
+ pci_base(adapter, off), off, addr);
+ if (!addr) {
+ netxen_nic_pci_change_crbwindow(adapter, 1);
+ return 1;
+ }
+ switch (len) {
+ case 1:
+ *(u8 *) data = readb(addr);
+ break;
+ case 2:
+ *(u16 *) data = readw(addr);
+ break;
+ case 4:
+ *(u32 *) data = readl(addr);
+ break;
+ case 8:
+ *(u64 *) data = readq(addr);
+ break;
+ default:
+ netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
+ (len >> 3));
+ break;
+ }
+ DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
+
+ if (!ADDR_IN_WINDOW1(off))
+ netxen_nic_pci_change_crbwindow(adapter, 1);
+
+ return 0;
+}
+
+void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
+{ /* Only for window 1 */
+ void __iomem *addr;
+
+ addr = NETXEN_CRB_NORMALIZE(adapter, off);
+ DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
+ pci_base(adapter, off), off, addr, val);
+ writel(val, addr);
+
+}
+
+int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
+{ /* Only for window 1 */
+ void __iomem *addr;
+ int val;
+
+ addr = NETXEN_CRB_NORMALIZE(adapter, off);
+ DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
+ pci_base(adapter, off), off, addr);
+ val = readl(addr);
+ writel(val, addr);
+
+ return val;
+}
+
+/* Change the window to 0, write and change back to window 1. */
+void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
+{
+ void __iomem *addr;
+
+ netxen_nic_pci_change_crbwindow(adapter, 0);
+ addr = pci_base_offset(adapter, index);
+ writel(value, addr);
+ netxen_nic_pci_change_crbwindow(adapter, 1);
+}
+
+/* Change the window to 0, read and change back to window 1. */
+void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
+{
+ void __iomem *addr;
+
+ addr = pci_base_offset(adapter, index);
+
+ netxen_nic_pci_change_crbwindow(adapter, 0);
+ *value = readl(addr);
+ netxen_nic_pci_change_crbwindow(adapter, 1);
+}
+
+int netxen_pci_set_window_warning_count = 0;
+
+unsigned long
+netxen_nic_pci_set_window(struct netxen_adapter *adapter,
+ unsigned long long addr)
+{
+ static int ddr_mn_window = -1;
+ static int qdr_sn_window = -1;
+ int window;
+
+ if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
+ /* DDR network side */
+ addr -= NETXEN_ADDR_DDR_NET;
+ window = (addr >> 25) & 0x3ff;
+ if (ddr_mn_window != window) {
+ ddr_mn_window = window;
+ writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
+ NETXEN_PCIX_PH_REG
+ (PCIX_MN_WINDOW)));
+ /* MUST make sure window is set before we forge on... */
+ readl(PCI_OFFSET_SECOND_RANGE(adapter,
+ NETXEN_PCIX_PH_REG
+ (PCIX_MN_WINDOW)));
+ }
+ addr -= (window * NETXEN_WINDOW_ONE);
+ addr += NETXEN_PCI_DDR_NET;
+ } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
+ addr -= NETXEN_ADDR_OCM0;
+ addr += NETXEN_PCI_OCM0;
+ } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
+ addr -= NETXEN_ADDR_OCM1;
+ addr += NETXEN_PCI_OCM1;
+ } else
+ if (ADDR_IN_RANGE
+ (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
+ /* QDR network side */
+ addr -= NETXEN_ADDR_QDR_NET;
+ window = (addr >> 22) & 0x3f;
+ if (qdr_sn_window != window) {
+ qdr_sn_window = window;
+ writel((window << 22),
+ PCI_OFFSET_SECOND_RANGE(adapter,
+ NETXEN_PCIX_PH_REG
+ (PCIX_SN_WINDOW)));
+ /* MUST make sure window is set before we forge on... */
+ readl(PCI_OFFSET_SECOND_RANGE(adapter,
+ NETXEN_PCIX_PH_REG
+ (PCIX_SN_WINDOW)));
+ }
+ addr -= (window * 0x400000);
+ addr += NETXEN_PCI_QDR_NET;
+ } else {
+ /*
+ * peg gdb frequently accesses memory that doesn't exist,
+ * this limits the chit chat so debugging isn't slowed down.
+ */
+ if ((netxen_pci_set_window_warning_count++ < 8)
+ || (netxen_pci_set_window_warning_count % 64 == 0))
+ printk("%s: Warning:netxen_nic_pci_set_window()"
+ " Unknown address range!\n",
+ netxen_nic_driver_name);
+
+ }
+ return addr;
+}
+
+int
+netxen_nic_erase_pxe(struct netxen_adapter *adapter)
+{
+ if (netxen_rom_fast_write(adapter, PXE_START, 0) == -1) {
+ printk(KERN_ERR "%s: erase pxe failed\n",
+ netxen_nic_driver_name);
+ return -1;
+ }
+ return 0;
+}
+
+int netxen_nic_get_board_info(struct netxen_adapter *adapter)
+{
+ int rv = 0;
+ int addr = BRDCFG_START;
+ struct netxen_board_info *boardinfo;
+ int index;
+ u32 *ptr32;
+
+ boardinfo = &adapter->ahw.boardcfg;
+ ptr32 = (u32 *) boardinfo;
+
+ for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
+ index++) {
+ if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
+ return -EIO;
+ }
+ ptr32++;
+ addr += sizeof(u32);
+ }
+ if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
+ printk("%s: ERROR reading %s board config."
+ " Read %x, expected %x\n", netxen_nic_driver_name,
+ netxen_nic_driver_name,
+ boardinfo->magic, NETXEN_BDINFO_MAGIC);
+ rv = -1;
+ }
+ if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
+ printk("%s: Unknown board config version."
+ " Read %x, expected %x\n", netxen_nic_driver_name,
+ boardinfo->header_version, NETXEN_BDINFO_VERSION);
+ rv = -1;
+ }
+
+ DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
+ switch ((netxen_brdtype_t) boardinfo->board_type) {
+ case NETXEN_BRDTYPE_P2_SB35_4G:
+ adapter->ahw.board_type = NETXEN_NIC_GBE;
+ break;
+ case NETXEN_BRDTYPE_P2_SB31_10G:
+ case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
+ case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
+ case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
+ adapter->ahw.board_type = NETXEN_NIC_XGBE;
+ break;
+ case NETXEN_BRDTYPE_P1_BD:
+ case NETXEN_BRDTYPE_P1_SB:
+ case NETXEN_BRDTYPE_P1_SMAX:
+ case NETXEN_BRDTYPE_P1_SOCK:
+ adapter->ahw.board_type = NETXEN_NIC_GBE;
+ break;
+ default:
+ printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
+ boardinfo->board_type);
+ break;
+ }
+
+ return rv;
+}
+
+/* NIU access sections */
+
+int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
+{
+ netxen_nic_write_w0(adapter,
+ NETXEN_NIU_GB_MAX_FRAME_SIZE(
+ physical_port[adapter->portnum]), new_mtu);
+ return 0;
+}
+
+int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
+{
+ new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
+ if (physical_port[adapter->portnum] == 0)
+ netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
+ new_mtu);
+ else
+ netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
+ new_mtu);
+ return 0;
+}
+
+void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
+{
+ netxen_niu_gbe_init_port(adapter, physical_port[adapter->portnum]);
+}
+
+void
+netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
+ int data)
+{
+ void __iomem *addr;
+
+ if (ADDR_IN_WINDOW1(off)) {
+ writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
+ } else {
+ netxen_nic_pci_change_crbwindow(adapter, 0);
+ addr = pci_base_offset(adapter, off);
+ writel(data, addr);
+ netxen_nic_pci_change_crbwindow(adapter, 1);
+ }
+}
+
+void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
+{
+ __u32 status;
+ __u32 autoneg;
+ __u32 mode;
+
+ netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
+ if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
+ if (adapter->phy_read
+ && adapter->
+ phy_read(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
+ &status) == 0) {
+ if (netxen_get_phy_link(status)) {
+ switch (netxen_get_phy_speed(status)) {
+ case 0:
+ adapter->link_speed = SPEED_10;
+ break;
+ case 1:
+ adapter->link_speed = SPEED_100;
+ break;
+ case 2:
+ adapter->link_speed = SPEED_1000;
+ break;
+ default:
+ adapter->link_speed = -1;
+ break;
+ }
+ switch (netxen_get_phy_duplex(status)) {
+ case 0:
+ adapter->link_duplex = DUPLEX_HALF;
+ break;
+ case 1:
+ adapter->link_duplex = DUPLEX_FULL;
+ break;
+ default:
+ adapter->link_duplex = -1;
+ break;
+ }
+ if (adapter->phy_read
+ && adapter->
+ phy_read(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
+ &autoneg) != 0)
+ adapter->link_autoneg = autoneg;
+ } else
+ goto link_down;
+ } else {
+ link_down:
+ adapter->link_speed = -1;
+ adapter->link_duplex = -1;
+ }
+ }
+}
+
+void netxen_nic_flash_print(struct netxen_adapter *adapter)
+{
+ int valid = 1;
+ u32 fw_major = 0;
+ u32 fw_minor = 0;
+ u32 fw_build = 0;
+ char brd_name[NETXEN_MAX_SHORT_NAME];
+ struct netxen_new_user_info user_info;
+ int i, addr = USER_START;
+ __le32 *ptr32;
+
+ struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
+ if (board_info->magic != NETXEN_BDINFO_MAGIC) {
+ printk
+ ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
+ board_info->magic, NETXEN_BDINFO_MAGIC);
+ valid = 0;
+ }
+ if (board_info->header_version != NETXEN_BDINFO_VERSION) {
+ printk("NetXen Unknown board config version."
+ " Read %x, expected %x\n",
+ board_info->header_version, NETXEN_BDINFO_VERSION);
+ valid = 0;
+ }
+ if (valid) {
+ ptr32 = (u32 *) & user_info;
+ for (i = 0;
+ i < sizeof(struct netxen_new_user_info) / sizeof(u32);
+ i++) {
+ if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
+ printk("%s: ERROR reading %s board userarea.\n",
+ netxen_nic_driver_name,
+ netxen_nic_driver_name);
+ return;
+ }
+ ptr32++;
+ addr += sizeof(u32);
+ }
+ get_brd_name_by_type(board_info->board_type, brd_name);
+
+ printk("NetXen %s Board S/N %s Chip id 0x%x\n",
+ brd_name, user_info.serial_num, board_info->chip_id);
+
+ printk("NetXen %s Board #%d, Chip id 0x%x\n",
+ board_info->board_type == 0x0b ? "XGB" : "GBE",
+ board_info->board_num, board_info->chip_id);
+ fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
+ NETXEN_FW_VERSION_MAJOR));
+ fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
+ NETXEN_FW_VERSION_MINOR));
+ fw_build =
+ readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
+
+ printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
+ fw_build);
+ }
+ if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
+ printk(KERN_ERR "The mismatch in driver version and firmware "
+ "version major number\n"
+ "Driver version major number = %d \t"
+ "Firmware version major number = %d \n",
+ _NETXEN_NIC_LINUX_MAJOR, fw_major);
+ adapter->driver_mismatch = 1;
+ }
+ if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
+ fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
+ printk(KERN_ERR "The mismatch in driver version and firmware "
+ "version minor number\n"
+ "Driver version minor number = %d \t"
+ "Firmware version minor number = %d \n",
+ _NETXEN_NIC_LINUX_MINOR, fw_minor);
+ adapter->driver_mismatch = 1;
+ }
+ if (adapter->driver_mismatch)
+ printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
+ fw_major, fw_minor);
+}
+
--- linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_isr.c.rhel5
+++ linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_isr.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2003 - 2006 NetXen, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
+ * MA 02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.
+ *
+ * Contact Information:
+ * info@netxen.com
+ * NetXen,
+ * 3965 Freedom Circle, Fourth floor,
+ * Santa Clara, CA 95054
+ */
+
+#include <linux/netdevice.h>
+#include <linux/delay.h>
+
+#include "netxen_nic.h"
+#include "netxen_nic_hw.h"
+#include "netxen_nic_phan_reg.h"
+
+/*
+ * netxen_nic_get_stats - Get System Network Statistics
+ * @netdev: network interface device structure
+ */
+struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev)
+{
+ struct netxen_adapter *adapter = netdev_priv(netdev);
+ struct net_device_stats *stats = &adapter->net_stats;
+
+ memset(stats, 0, sizeof(*stats));
+
+ /* total packets received */
+ stats->rx_packets = adapter->stats.no_rcv;
+ /* total packets transmitted */
+ stats->tx_packets = adapter->stats.xmitedframes +
+ adapter->stats.xmitfinished;
+ /* total bytes received */
+ stats->rx_bytes = adapter->stats.rxbytes;
+ /* total bytes transmitted */
+ stats->tx_bytes = adapter->stats.txbytes;
+ /* bad packets received */
+ stats->rx_errors = adapter->stats.rcvdbadskb;
+ /* packet transmit problems */
+ stats->tx_errors = adapter->stats.nocmddescriptor;
+ /* no space in linux buffers */
+ stats->rx_dropped = adapter->stats.updropped;
+ /* no space available in linux */
+ stats->tx_dropped = adapter->stats.txdropped;
+
+ return stats;
+}
+
+void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 link)
+{
+ struct net_device *netdev = adapter->netdev;
+
+ if (link)
+ netif_carrier_on(netdev);
+ else
+ netif_carrier_off(netdev);
+}
+
+void netxen_handle_port_int(struct netxen_adapter *adapter, u32 enable)
+{
+ __u32 int_src;
+
+ /* This should clear the interrupt source */
+ if (adapter->phy_read)
+ adapter->phy_read(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
+ &int_src);
+ if (int_src == 0) {
+ DPRINTK(INFO, "No phy interrupts for port #%d\n", portno);
+ return;
+ }
+ if (adapter->disable_phy_interrupts)
+ adapter->disable_phy_interrupts(adapter);
+
+ if (netxen_get_phy_int_jabber(int_src))
+ DPRINTK(INFO, "Jabber interrupt \n");
+
+ if (netxen_get_phy_int_polarity_changed(int_src))
+ DPRINTK(INFO, "POLARITY CHANGED int \n");
+
+ if (netxen_get_phy_int_energy_detect(int_src))
+ DPRINTK(INFO, "ENERGY DETECT INT \n");
+
+ if (netxen_get_phy_int_downshift(int_src))
+ DPRINTK(INFO, "DOWNSHIFT INT \n");
+ /* write it down later.. */
+ if ((netxen_get_phy_int_speed_changed(int_src))
+ || (netxen_get_phy_int_link_status_changed(int_src))) {
+ __u32 status;
+
+ DPRINTK(INFO, "SPEED CHANGED OR LINK STATUS CHANGED \n");
+
+ if (adapter->phy_read
+ && adapter->phy_read(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
+ &status) == 0) {
+ if (netxen_get_phy_int_link_status_changed(int_src)) {
+ if (netxen_get_phy_link(status)) {
+ printk(KERN_INFO "%s: %s Link UP\n",
+ netxen_nic_driver_name,
+ adapter->netdev->name);
+
+ } else {
+ printk(KERN_INFO "%s: %s Link DOWN\n",
+ netxen_nic_driver_name,
+ adapter->netdev->name);
+ }
+ netxen_indicate_link_status(adapter,
+ netxen_get_phy_link
+ (status));
+ }
+ }
+ }
+ if (adapter->enable_phy_interrupts)
+ adapter->enable_phy_interrupts(adapter);
+}
+
+void netxen_nic_isr_other(struct netxen_adapter *adapter)
+{
+ int portno = adapter->portnum;
+ u32 val, linkup, qg_linksup;
+
+ /* verify the offset */
+ val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE));
+ val = val >> physical_port[adapter->portnum];
+ if (val == adapter->ahw.qg_linksup)
+ return;
+
+ qg_linksup = adapter->ahw.qg_linksup;
+ adapter->ahw.qg_linksup = val;
+ DPRINTK(INFO, "link update 0x%08x\n", val);
+
+ linkup = val & 1;
+
+ if (linkup != (qg_linksup & 1)) {
+ printk(KERN_INFO "%s: %s PORT %d link %s\n",
+ adapter->netdev->name,
+ netxen_nic_driver_name, portno,
+ ((linkup == 0) ? "down" : "up"));
+ netxen_indicate_link_status(adapter, linkup);
+ if (linkup)
+ netxen_nic_set_link_parameters(adapter);
+
+ }
+}
+
+void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter)
+{
+ netxen_nic_isr_other(adapter);
+}
+
+void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter)
+{
+ struct net_device *netdev = adapter->netdev;
+ u32 val, val1;
+
+ /* WINDOW = 1 */
+ val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE));
+ val >>= (physical_port[adapter->portnum] * 8);
+ val1 = val & 0xff;
+
+ if (adapter->ahw.xg_linkup == 1 && val1 != XG_LINK_UP) {
+ printk(KERN_INFO "%s: %s NIC Link is down\n",
+ netxen_nic_driver_name, netdev->name);
+ adapter->ahw.xg_linkup = 0;
+ /* read twice to clear sticky bits */
+ /* WINDOW = 0 */
+ netxen_nic_read_w0(adapter, NETXEN_NIU_XG_STATUS, &val1);
+ netxen_nic_read_w0(adapter, NETXEN_NIU_XG_STATUS, &val1);
+
+ if ((val & 0xffb) != 0xffb) {
+ printk(KERN_INFO "%s ISR: Sync/Align BAD: 0x%08x\n",
+ netxen_nic_driver_name, val1);
+ }
+ } else if (adapter->ahw.xg_linkup == 0 && val1 == XG_LINK_UP) {
+ printk(KERN_INFO "%s: %s NIC Link is up\n",
+ netxen_nic_driver_name, netdev->name);
+ adapter->ahw.xg_linkup = 1;
+ }
+}
--- linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_niu.c.rhel5
+++ linux-2.6.18.x86_64/drivers/net/netxen/netxen_nic_niu.c
@@ -0,0 +1,916 @@
+/*
+ * Copyright (C) 2003 - 2006 NetXen, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
+ * MA 02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.
+ *
+ * Contact Information:
+ * info@netxen.com
+ * NetXen,
+ * 3965 Freedom Circle, Fourth floor,
+ * Santa Clara, CA 95054
+ *
+ *
+ * Provides access to the Network Interface Unit h/w block.
+ *
+ */
+
+#include "netxen_nic.h"
+
+#define NETXEN_GB_MAC_SOFT_RESET 0x80000000
+#define NETXEN_GB_MAC_RESET_PROT_BLK 0x000F0000
+#define NETXEN_GB_MAC_ENABLE_TX_RX 0x00000005
+#define NETXEN_GB_MAC_PAUSED_FRMS 0x00000020
+
+static long phy_lock_timeout = 100000000;
+
+static inline int phy_lock(struct netxen_adapter *adapter)
+{
+ int i;
+ int done = 0, timeout = 0;
+
+ while (!done) {
+ done =
+ readl(pci_base_offset
+ (adapter, NETXEN_PCIE_REG(PCIE_SEM3_LOCK)));
+ if (done == 1)
+ break;
+ if (timeout >= phy_lock_timeout) {
+ return -1;
+ }
+ timeout++;
+ if (!in_atomic())
+ schedule();
+ else {
+ for (i = 0; i < 20; i++)
+ cpu_relax();
+ }
+ }
+
+ writel(PHY_LOCK_DRIVER,
+ NETXEN_CRB_NORMALIZE(adapter, NETXEN_PHY_LOCK_ID));
+ return 0;
+}
+
+static inline int phy_unlock(struct netxen_adapter *adapter)
+{
+ readl(pci_base_offset(adapter, NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK)));
+
+ return 0;
+}
+
+/*
+ * netxen_niu_gbe_phy_read - read a register from the GbE PHY via
+ * mii management interface.
+ *
+ * Note: The MII management interface goes through port 0.
+ * Individual phys are addressed as follows:
+ * @param phy [15:8] phy id
+ * @param reg [7:0] register number
+ *
+ * @returns 0 on success
+ * -1 on error
+ *
+ */
+int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
+ __u32 * readval)
+{
+ long timeout = 0;
+ long result = 0;
+ long restore = 0;
+ long phy = physical_port[adapter->portnum];
+ __u32 address;
+ __u32 command;
+ __u32 status;
+ __u32 mac_cfg0;
+
+ if (phy_lock(adapter) != 0) {
+ return -1;
+ }
+
+ /*
+ * MII mgmt all goes through port 0 MAC interface,
+ * so it cannot be in reset
+ */
+
+ if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
+ &mac_cfg0, 4))
+ return -EIO;
+ if (netxen_gb_get_soft_reset(mac_cfg0)) {
+ __u32 temp;
+ temp = 0;
+ netxen_gb_tx_reset_pb(temp);
+ netxen_gb_rx_reset_pb(temp);
+ netxen_gb_tx_reset_mac(temp);
+ netxen_gb_rx_reset_mac(temp);
+ if (netxen_nic_hw_write_wx(adapter,
+ NETXEN_NIU_GB_MAC_CONFIG_0(0),
+ &temp, 4))
+ return -EIO;
+ restore = 1;
+ }
+
+ address = 0;
+ netxen_gb_mii_mgmt_reg_addr(address, reg);
+ netxen_gb_mii_mgmt_phy_addr(address, phy);
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
+ &address, 4))
+ return -EIO;
+ command = 0; /* turn off any prior activity */
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
+ &command, 4))
+ return -EIO;
+ /* send read command */
+ netxen_gb_mii_mgmt_set_read_cycle(command);
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
+ &command, 4))
+ return -EIO;
+
+ status = 0;
+ do {
+ if (netxen_nic_hw_read_wx(adapter,
+ NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
+ &status, 4))
+ return -EIO;
+ timeout++;
+ } while ((netxen_get_gb_mii_mgmt_busy(status)
+ || netxen_get_gb_mii_mgmt_notvalid(status))
+ && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
+
+ if (timeout < NETXEN_NIU_PHY_WAITMAX) {
+ if (netxen_nic_hw_read_wx(adapter,
+ NETXEN_NIU_GB_MII_MGMT_STATUS(0),
+ readval, 4))
+ return -EIO;
+ result = 0;
+ } else
+ result = -1;
+
+ if (restore)
+ if (netxen_nic_hw_write_wx(adapter,
+ NETXEN_NIU_GB_MAC_CONFIG_0(0),
+ &mac_cfg0, 4))
+ return -EIO;
+ phy_unlock(adapter);
+ return result;
+}
+
+/*
+ * netxen_niu_gbe_phy_write - write a register to the GbE PHY via
+ * mii management interface.
+ *
+ * Note: The MII management interface goes through port 0.
+ * Individual phys are addressed as follows:
+ * @param phy [15:8] phy id
+ * @param reg [7:0] register number
+ *
+ * @returns 0 on success
+ * -1 on error
+ *
+ */
+int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
+ __u32 val)
+{
+ long timeout = 0;
+ long result = 0;
+ long restore = 0;
+ long phy = physical_port[adapter->portnum];
+ __u32 address;
+ __u32 command;
+ __u32 status;
+ __u32 mac_cfg0;
+
+ /*
+ * MII mgmt all goes through port 0 MAC interface, so it
+ * cannot be in reset
+ */
+
+ if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
+ &mac_cfg0, 4))
+ return -EIO;
+ if (netxen_gb_get_soft_reset(mac_cfg0)) {
+ __u32 temp;
+ temp = 0;
+ netxen_gb_tx_reset_pb(temp);
+ netxen_gb_rx_reset_pb(temp);
+ netxen_gb_tx_reset_mac(temp);
+ netxen_gb_rx_reset_mac(temp);
+
+ if (netxen_nic_hw_write_wx(adapter,
+ NETXEN_NIU_GB_MAC_CONFIG_0(0),
+ &temp, 4))
+ return -EIO;
+ restore = 1;
+ }
+
+ command = 0; /* turn off any prior activity */
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
+ &command, 4))
+ return -EIO;
+
+ address = 0;
+ netxen_gb_mii_mgmt_reg_addr(address, reg);
+ netxen_gb_mii_mgmt_phy_addr(address, phy);
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
+ &address, 4))
+ return -EIO;
+
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0),
+ &val, 4))
+ return -EIO;
+
+ status = 0;
+ do {
+ if (netxen_nic_hw_read_wx(adapter,
+ NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
+ &status, 4))
+ return -EIO;
+ timeout++;
+ } while ((netxen_get_gb_mii_mgmt_busy(status))
+ && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
+
+ if (timeout < NETXEN_NIU_PHY_WAITMAX)
+ result = 0;
+ else
+ result = -EIO;
+
+ /* restore the state of port 0 MAC in case we tampered with it */
+ if (restore)
+ if (netxen_nic_hw_write_wx(adapter,
+ NETXEN_NIU_GB_MAC_CONFIG_0(0),
+ &mac_cfg0, 4))
+ return -EIO;
+
+ return result;
+}
+
+int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter)
+{
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x3f);
+ return 0;
+}
+
+int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter)
+{
+ int result = 0;
+ __u32 enable = 0;
+ netxen_set_phy_int_link_status_changed(enable);
+ netxen_set_phy_int_autoneg_completed(enable);
+ netxen_set_phy_int_speed_changed(enable);
+
+ if (0 !=
+ netxen_niu_gbe_phy_write(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE,
+ enable))
+ result = -EIO;
+
+ return result;
+}
+
+int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter)
+{
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x7f);
+ return 0;
+}
+
+int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter)
+{
+ int result = 0;
+ if (0 !=
+ netxen_niu_gbe_phy_write(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE, 0))
+ result = -EIO;
+
+ return result;
+}
+
+int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter)
+{
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_ACTIVE_INT, -1);
+ return 0;
+}
+
+int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter)
+{
+ int result = 0;
+ if (0 !=
+ netxen_niu_gbe_phy_write(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
+ -EIO))
+ result = -EIO;
+
+ return result;
+}
+
+/*
+ * netxen_niu_gbe_set_mii_mode- Set 10/100 Mbit Mode for GbE MAC
+ *
+ */
+void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
+ int port, long enable)
+{
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2);
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
+ 0x80000000);
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
+ 0x0000f0025);
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port),
+ 0xf1ff);
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
+ netxen_crb_writelit_adapter(adapter,
+ (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
+
+ if (enable) {
+ /*
+ * Do NOT enable flow control until a suitable solution for
+ * shutting down pause frames is found.
+ */
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_GB_MAC_CONFIG_0(port),
+ 0x5);
+ }
+
+ if (netxen_niu_gbe_enable_phy_interrupts(adapter))
+ printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n");
+ if (netxen_niu_gbe_clear_phy_interrupts(adapter))
+ printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n");
+}
+
+/*
+ * netxen_niu_gbe_set_gmii_mode- Set GbE Mode for GbE MAC
+ */
+void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter,
+ int port, long enable)
+{
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2);
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
+ 0x80000000);
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
+ 0x0000f0025);
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port),
+ 0xf2ff);
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
+ netxen_crb_writelit_adapter(adapter,
+ (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
+
+ if (enable) {
+ /*
+ * Do NOT enable flow control until a suitable solution for
+ * shutting down pause frames is found.
+ */
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_GB_MAC_CONFIG_0(port),
+ 0x5);
+ }
+
+ if (netxen_niu_gbe_enable_phy_interrupts(adapter))
+ printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n");
+ if (netxen_niu_gbe_clear_phy_interrupts(adapter))
+ printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n");
+}
+
+int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
+{
+ int result = 0;
+ __u32 status;
+ if (adapter->disable_phy_interrupts)
+ adapter->disable_phy_interrupts(adapter);
+ mdelay(2);
+
+ if (0 ==
+ netxen_niu_gbe_phy_read(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
+ &status)) {
+ if (netxen_get_phy_link(status)) {
+ if (netxen_get_phy_speed(status) == 2) {
+ netxen_niu_gbe_set_gmii_mode(adapter, port, 1);
+ } else if ((netxen_get_phy_speed(status) == 1)
+ || (netxen_get_phy_speed(status) == 0)) {
+ netxen_niu_gbe_set_mii_mode(adapter, port, 1);
+ } else {
+ result = -1;
+ }
+
+ } else {
+ /*
+ * We don't have link. Cable must be unconnected.
+ * Enable phy interrupts so we take action when
+ * plugged in.
+ */
+
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_GB_MAC_CONFIG_0
+ (port),
+ NETXEN_GB_MAC_SOFT_RESET);
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_GB_MAC_CONFIG_0
+ (port),
+ NETXEN_GB_MAC_RESET_PROT_BLK
+ | NETXEN_GB_MAC_ENABLE_TX_RX
+ |
+ NETXEN_GB_MAC_PAUSED_FRMS);
+ if (netxen_niu_gbe_clear_phy_interrupts(adapter))
+ printk(KERN_ERR PFX
+ "ERROR clearing PHY interrupts\n");
+ if (netxen_niu_gbe_enable_phy_interrupts(adapter))
+ printk(KERN_ERR PFX
+ "ERROR enabling PHY interrupts\n");
+ if (netxen_niu_gbe_clear_phy_interrupts(adapter))
+ printk(KERN_ERR PFX
+ "ERROR clearing PHY interrupts\n");
+ result = -1;
+ }
+ } else {
+ result = -EIO;
+ }
+ return result;
+}
+
+int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
+{
+ u32 reg;
+ u32 portnum = physical_port[adapter->portnum];
+
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_XGE_CONFIG_0+(0x10000*portnum), 0x5);
+ netxen_nic_hw_read_wx(adapter,
+ NETXEN_NIU_XGE_CONFIG_1+(0x10000*portnum), ®, 4);
+ reg = (reg & ~0x2000UL);
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_XGE_CONFIG_1+(0x10000*portnum), reg);
+
+ return 0;
+}
+
+/*
+ * netxen_niu_gbe_handle_phy_interrupt - Handles GbE PHY interrupts
+ * @param enable 0 means don't enable the port
+ * 1 means enable (or re-enable) the port
+ */
+int netxen_niu_gbe_handle_phy_interrupt(struct netxen_adapter *adapter,
+ int port, long enable)
+{
+ int result = 0;
+ __u32 int_src;
+
+ printk(KERN_INFO PFX "NETXEN: Handling PHY interrupt on port %d"
+ " (device enable = %d)\n", (int)port, (int)enable);
+
+ /*
+ * The read of the PHY INT status will clear the pending
+ * interrupt status
+ */
+ if (netxen_niu_gbe_phy_read(adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
+ &int_src) != 0)
+ result = -EINVAL;
+ else {
+ printk(KERN_INFO PFX "PHY Interrupt source = 0x%x \n", int_src);
+ if (netxen_get_phy_int_jabber(int_src))
+ printk(KERN_INFO PFX "jabber Interrupt ");
+ if (netxen_get_phy_int_polarity_changed(int_src))
+ printk(KERN_INFO PFX "polarity changed ");
+ if (netxen_get_phy_int_energy_detect(int_src))
+ printk(KERN_INFO PFX "energy detect \n");
+ if (netxen_get_phy_int_downshift(int_src))
+ printk(KERN_INFO PFX "downshift \n");
+ if (netxen_get_phy_int_mdi_xover_changed(int_src))
+ printk(KERN_INFO PFX "mdi_xover_changed ");
+ if (netxen_get_phy_int_fifo_over_underflow(int_src))
+ printk(KERN_INFO PFX "fifo_over_underflow ");
+ if (netxen_get_phy_int_false_carrier(int_src))
+ printk(KERN_INFO PFX "false_carrier ");
+ if (netxen_get_phy_int_symbol_error(int_src))
+ printk(KERN_INFO PFX "symbol_error ");
+ if (netxen_get_phy_int_autoneg_completed(int_src))
+ printk(KERN_INFO PFX "autoneg_completed ");
+ if (netxen_get_phy_int_page_received(int_src))
+ printk(KERN_INFO PFX "page_received ");
+ if (netxen_get_phy_int_duplex_changed(int_src))
+ printk(KERN_INFO PFX "duplex_changed ");
+ if (netxen_get_phy_int_autoneg_error(int_src))
+ printk(KERN_INFO PFX "autoneg_error ");
+ if ((netxen_get_phy_int_speed_changed(int_src))
+ || (netxen_get_phy_int_link_status_changed(int_src))) {
+ __u32 status;
+
+ printk(KERN_INFO PFX
+ "speed_changed or link status changed");
+ if (netxen_niu_gbe_phy_read
+ (adapter,
+ NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
+ &status) == 0) {
+ if (netxen_get_phy_speed(status) == 2) {
+ printk
+ (KERN_INFO PFX "Link speed changed"
+ " to 1000 Mbps\n");
+ netxen_niu_gbe_set_gmii_mode(adapter,
+ port,
+ enable);
+ } else if (netxen_get_phy_speed(status) == 1) {
+ printk
+ (KERN_INFO PFX "Link speed changed"
+ " to 100 Mbps\n");
+ netxen_niu_gbe_set_mii_mode(adapter,
+ port,
+ enable);
+ } else if (netxen_get_phy_speed(status) == 0) {
+ printk
+ (KERN_INFO PFX "Link speed changed"
+ " to 10 Mbps\n");
+ netxen_niu_gbe_set_mii_mode(adapter,
+ port,
+ enable);
+ } else {
+ printk(KERN_ERR PFX "ERROR reading"
+ "PHY status. Illegal speed.\n");
+ result = -1;
+ }
+ } else {
+ printk(KERN_ERR PFX
+ "ERROR reading PHY status.\n");
+ result = -1;
+ }
+
+ }
+ printk(KERN_INFO "\n");
+ }
+ return result;
+}
+
+/*
+ * Return the current station MAC address.
+ * Note that the passed-in value must already be in network byte order.
+ */
+int netxen_niu_macaddr_get(struct netxen_adapter *adapter,
+ netxen_ethernet_macaddr_t * addr)
+{
+ u32 stationhigh;
+ u32 stationlow;
+ int phy = physical_port[adapter->portnum];
+ u8 val[8];
+
+ if (addr == NULL)
+ return -EINVAL;
+ if ((phy < 0) || (phy > 3))
+ return -EINVAL;
+
+ if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy),
+ &stationhigh, 4))
+ return -EIO;
+ if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy),
+ &stationlow, 4))
+ return -EIO;
+ ((__le32 *)val)[1] = cpu_to_le32(stationhigh);
+ ((__le32 *)val)[0] = cpu_to_le32(stationlow);
+
+ memcpy(addr, val + 2, 6);
+
+ return 0;
+}
+
+/*
+ * Set the station MAC address.
+ * Note that the passed-in value must already be in network byte order.
+ */
+int netxen_niu_macaddr_set(struct netxen_adapter *adapter,
+ netxen_ethernet_macaddr_t addr)
+{
+ u8 temp[4];
+ u32 val;
+ int phy = physical_port[adapter->portnum];
+ unsigned char mac_addr[6];
+ int i;
+
+ for (i = 0; i < 10; i++) {
+ temp[0] = temp[1] = 0;
+ memcpy(temp + 2, addr, 2);
+ val = le32_to_cpu(*(__le32 *)temp);
+ if (netxen_nic_hw_write_wx
+ (adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy), &val, 4))
+ return -EIO;
+
+ memcpy(temp, ((u8 *) addr) + 2, sizeof(__le32));
+ val = le32_to_cpu(*(__le32 *)temp);
+ if (netxen_nic_hw_write_wx
+ (adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy), &val, 4))
+ return -2;
+
+ netxen_niu_macaddr_get(adapter,
+ (netxen_ethernet_macaddr_t *) mac_addr);
+ if (memcmp(mac_addr, addr, 6) == 0)
+ break;
+ }
+
+ if (i == 10) {
+ printk(KERN_ERR "%s: cannot set Mac addr for %s\n",
+ netxen_nic_driver_name, adapter->netdev->name);
+ printk(KERN_ERR "MAC address set: "
+ "%02x:%02x:%02x:%02x:%02x:%02x.\n",
+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+
+ printk(KERN_ERR "MAC address get: "
+ "%02x:%02x:%02x:%02x:%02x:%02x.\n",
+ mac_addr[0],
+ mac_addr[1],
+ mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
+ }
+ return 0;
+}
+
+/* Enable a GbE interface */
+int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
+ int port, netxen_niu_gbe_ifmode_t mode)
+{
+ __u32 mac_cfg0;
+ __u32 mac_cfg1;
+ __u32 mii_cfg;
+
+ if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
+ return -EINVAL;
+
+ mac_cfg0 = 0;
+ netxen_gb_soft_reset(mac_cfg0);
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
+ &mac_cfg0, 4))
+ return -EIO;
+ mac_cfg0 = 0;
+ netxen_gb_enable_tx(mac_cfg0);
+ netxen_gb_enable_rx(mac_cfg0);
+ netxen_gb_unset_rx_flowctl(mac_cfg0);
+ netxen_gb_tx_reset_pb(mac_cfg0);
+ netxen_gb_rx_reset_pb(mac_cfg0);
+ netxen_gb_tx_reset_mac(mac_cfg0);
+ netxen_gb_rx_reset_mac(mac_cfg0);
+
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
+ &mac_cfg0, 4))
+ return -EIO;
+ mac_cfg1 = 0;
+ netxen_gb_set_preamblelen(mac_cfg1, 0xf);
+ netxen_gb_set_duplex(mac_cfg1);
+ netxen_gb_set_crc_enable(mac_cfg1);
+ netxen_gb_set_padshort(mac_cfg1);
+ netxen_gb_set_checklength(mac_cfg1);
+ netxen_gb_set_hugeframes(mac_cfg1);
+
+ if (mode == NETXEN_NIU_10_100_MB) {
+ netxen_gb_set_intfmode(mac_cfg1, 1);
+ if (netxen_nic_hw_write_wx(adapter,
+ NETXEN_NIU_GB_MAC_CONFIG_1(port),
+ &mac_cfg1, 4))
+ return -EIO;
+
+ /* set mii mode */
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE +
+ (port << 3), 0);
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE +
+ (port << 3), 1);
+
+ } else if (mode == NETXEN_NIU_1000_MB) {
+ netxen_gb_set_intfmode(mac_cfg1, 2);
+ if (netxen_nic_hw_write_wx(adapter,
+ NETXEN_NIU_GB_MAC_CONFIG_1(port),
+ &mac_cfg1, 4))
+ return -EIO;
+ /* set gmii mode */
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE +
+ (port << 3), 0);
+ netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE +
+ (port << 3), 1);
+ }
+ mii_cfg = 0;
+ netxen_gb_set_mii_mgmt_clockselect(mii_cfg, 7);
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port),
+ &mii_cfg, 4))
+ return -EIO;
+ mac_cfg0 = 0;
+ netxen_gb_enable_tx(mac_cfg0);
+ netxen_gb_enable_rx(mac_cfg0);
+ netxen_gb_unset_rx_flowctl(mac_cfg0);
+ netxen_gb_unset_tx_flowctl(mac_cfg0);
+
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
+ &mac_cfg0, 4))
+ return -EIO;
+ return 0;
+}
+
+/* Disable a GbE interface */
+int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter)
+{
+ __u32 mac_cfg0;
+ u32 port = physical_port[adapter->portnum];
+
+ if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
+ return -EINVAL;
+ mac_cfg0 = 0;
+ netxen_gb_soft_reset(mac_cfg0);
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
+ &mac_cfg0, 4))
+ return -EIO;
+ return 0;
+}
+
+/* Disable an XG interface */
+int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
+{
+ __u32 mac_cfg;
+ u32 port = physical_port[adapter->portnum];
+
+ if (port != 0)
+ return -EINVAL;
+ mac_cfg = 0;
+ netxen_xg_soft_reset(mac_cfg);
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_CONFIG_0,
+ &mac_cfg, 4))
+ return -EIO;
+ return 0;
+}
+
+/* Set promiscuous mode for a GbE interface */
+int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
+ netxen_niu_prom_mode_t mode)
+{
+ __u32 reg;
+ u32 port = physical_port[adapter->portnum];
+
+ if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
+ return -EINVAL;
+
+ /* save previous contents */
+ if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
+ ®, 4))
+ return -EIO;
+ if (mode == NETXEN_NIU_PROMISC_MODE) {
+ switch (port) {
+ case 0:
+ netxen_clear_gb_drop_gb0(reg);
+ break;
+ case 1:
+ netxen_clear_gb_drop_gb1(reg);
+ break;
+ case 2:
+ netxen_clear_gb_drop_gb2(reg);
+ break;
+ case 3:
+ netxen_clear_gb_drop_gb3(reg);
+ break;
+ default:
+ return -EIO;
+ }
+ } else {
+ switch (port) {
+ case 0:
+ netxen_set_gb_drop_gb0(reg);
+ break;
+ case 1:
+ netxen_set_gb_drop_gb1(reg);
+ break;
+ case 2:
+ netxen_set_gb_drop_gb2(reg);
+ break;
+ case 3:
+ netxen_set_gb_drop_gb3(reg);
+ break;
+ default:
+ return -EIO;
+ }
+ }
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
+ ®, 4))
+ return -EIO;
+ return 0;
+}
+
+/*
+ * Set the MAC address for an XG port
+ * Note that the passed-in value must already be in network byte order.
+ */
+int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter,
+ netxen_ethernet_macaddr_t addr)
+{
+ int phy = physical_port[adapter->portnum];
+ u8 temp[4];
+ u32 val;
+
+ if ((phy < 0) || (phy > NETXEN_NIU_MAX_XG_PORTS))
+ return -EIO;
+
+ temp[0] = temp[1] = 0;
+ switch (phy) {
+ case 0:
+ memcpy(temp + 2, addr, 2);
+ val = le32_to_cpu(*(__le32 *)temp);
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
+ &val, 4))
+ return -EIO;
+
+ memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
+ val = le32_to_cpu(*(__le32 *)temp);
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
+ &val, 4))
+ return -EIO;
+ break;
+
+ case 1:
+ memcpy(temp + 2, addr, 2);
+ val = le32_to_cpu(*(__le32 *)temp);
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_1,
+ &val, 4))
+ return -EIO;
+
+ memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
+ val = le32_to_cpu(*(__le32 *)temp);
+ if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_HI,
+ &val, 4))
+ return -EIO;
+ break;
+
+ default:
+ printk(KERN_ERR "Unknown port %d\n", phy);
+ break;
+ }
+
+ return 0;
+}
+
+/*
+ * Return the current station MAC address.
+ * Note that the passed-in value must already be in network byte order.
+ */
+int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter,
+ netxen_ethernet_macaddr_t * addr)
+{
+ int phy = physical_port[adapter->portnum];
+ u32 stationhigh;
+ u32 stationlow;
+ u8 val[8];
+
+ if (addr == NULL)
+ return -EINVAL;
+ if (phy != 0)
+ return -EINVAL;
+
+ if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
+ &stationhigh, 4))
+ return -EIO;
+ if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
+ &stationlow, 4))
+ return -EIO;
+ ((__le32 *)val)[1] = cpu_to_le32(stationhigh);
+ ((__le32 *)val)[0] = cpu_to_le32(stationlow);
+
+ memcpy(addr, val + 2, 6);
+
+ return 0;
+}
+
+int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
+ netxen_niu_prom_mode_t mode)
+{
+ __u32 reg;
+ u32 port = physical_port[adapter->portnum];
+
+ if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS))
+ return -EINVAL;
+
+ if (netxen_nic_hw_read_wx(adapter,
+ NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), ®, 4))
+ return -EIO;
+ if (mode == NETXEN_NIU_PROMISC_MODE)
+ reg = (reg | 0x2000UL);
+ else
+ reg = (reg & ~0x2000UL);
+
+ netxen_crb_writelit_adapter(adapter,
+ NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
+
+ return 0;
+}
--- linux-2.6.18.x86_64/drivers/net/Kconfig.rhel5
+++ linux-2.6.18.x86_64/drivers/net/Kconfig
@@ -2417,6 +2417,12 @@ config MYRI10GE
<file:Documentation/networking/net-modules.txt>. The module
will be called myri10ge.
+config NETXEN_NIC
+ tristate "NetXen Multi port (1/10) Gigabit Ethernet NIC"
+ depends on PCI
+ help
+ This enables the support for NetXen's Gigabit Ethernet card.
+
endmenu
source "drivers/net/tokenring/Kconfig"
--- linux-2.6.18.x86_64/drivers/net/Makefile.rhel5
+++ linux-2.6.18.x86_64/drivers/net/Makefile
@@ -222,3 +222,4 @@ obj-$(CONFIG_NETCONSOLE) += netconsole.o
obj-$(CONFIG_FS_ENET) += fs_enet/
+obj-$(CONFIG_NETXEN_NIC) += netxen/
distrib
>
Scientific%20Linux
>
5x
>
x86_64
>
by-pkgid
>
27922b4260f65d317aabda37e42bbbff
>
files
>
2943
