From: Andy Gospodarek <gospo@redhat.com>
Date: Tue, 18 Nov 2008 15:12:01 -0500
Subject: [net] e1000e: enable ECC correction on 82571 silicon
Message-id: 20081118201201.GL8237@gospo.rdu.redhat.com
O-Subject: [RHEL5.3 PATCH] e1000e: enable ECC correction on 82571 silicon
Bugzilla: 472095
RH-Acked-by: Ivan Vecera <ivecera@redhat.com>
RH-Acked-by: John W. Linville <linville@redhat.com>
RH-Acked-by: Prarit Bhargava <prarit@redhat.com>

This patch enables ECC on the frame buffer memory of the 82571 cards.
Intel did not intend to turn this off originally and it is a nice
feature to have to ensure there is not data corruption.  This is a
backport for the following upstream commit:

   commit 6ea7ae1d0fc02a6c4ccd27e43346f67c44226e7a
   Author: Alexander Duyck <alexander.h.duyck@intel.com>
   Date:   Fri Nov 14 06:54:36 2008 +0000

       e1000e: enable ECC correction on 82571 silicon

       This change enables ECC correction for the packet buffer on all 82571
       silicon.

This will resolve the request in RHBZ 472095.

diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c
index e16b940..2ab36c9 100644
--- a/drivers/net/e1000e/82571.c
+++ b/drivers/net/e1000e/82571.c
@@ -973,6 +973,12 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
 		ew32(CTRL_EXT, reg);
 	}
 
+	if (hw->mac.type == e1000_82571) {
+		reg = er32(PBA_ECC);
+		reg |= E1000_PBA_ECC_CORR_EN;
+		ew32(PBA_ECC, reg);
+	}
+
 	/* PCI-Ex Control Register */
 	if (hw->mac.type == e1000_82574) {
 		reg = er32(GCR);
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h
index 972cc4a..f2f03ae 100644
--- a/drivers/net/e1000e/defines.h
+++ b/drivers/net/e1000e/defines.h
@@ -372,6 +372,13 @@
 #define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */
 #define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */
 
+/* PBA ECC Register */
+#define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */
+#define E1000_PBA_ECC_COUNTER_SHIFT 20         /* ECC counter shift value */
+#define E1000_PBA_ECC_CORR_EN       0x00000001 /* ECC correction enable */
+#define E1000_PBA_ECC_STAT_CLR      0x00000002 /* Clear ECC error counter */
+#define E1000_PBA_ECC_INT_EN        0x00000004 /* Enable ICR bit 5 for ECC */
+
 /*
  * This defines the bits that are set in the Interrupt Mask
  * Set/Read Register.  Each bit is documented below:
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index f66ed37..c4ffd4b 100644
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -87,6 +87,7 @@ enum e1e_registers {
 	E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
 	E1000_EEWR     = 0x0102C, /* EEPROM Write Register - RW */
 	E1000_FLOP     = 0x0103C, /* FLASH Opcode Register */
+	E1000_PBA_ECC  = 0x01100, /* PBA ECC Register */
 	E1000_ERT      = 0x02008, /* Early Rx Threshold - RW */
 	E1000_FCRTL    = 0x02160, /* Flow Control Receive Threshold Low - RW */
 	E1000_FCRTH    = 0x02168, /* Flow Control Receive Threshold High - RW */