From: Stanislaw Gruszka <sgruszka@redhat.com>
Date: Mon, 30 Nov 2009 07:49:31 -0500
Subject: [net] bnx2x: update to 1.52.1
Message-id: <1259567375-3357-2-git-send-email-sgruszka@redhat.com>
Patchwork-id: 21537
O-Subject: [RHEL5.5 PATCH 1/5] bnx2x: update to 1.52.1
Bugzilla: 515716 522600
RH-Acked-by: David S. Miller <davem@redhat.com>
RH-Acked-by: Andy Gospodarek <gospo@redhat.com>
BZ#515716
BZ#522600
Upstream:
commit c458bc50e31631f7e9333ea6f1832fc54d4e2c1e
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:24:31 2009 +0000
bnx2x: update version to 1.52.1
commit ab6ad5a4875e99dffe957a411fe890402a91f67f
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:24:29 2009 +0000
bnx2x: Whitespaces and comments
commit 9c63de6293775b537614550fd61075a33ada9469
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:24:25 2009 +0000
bnx2x: Removing unused definitions
commit 45a4864d80264f6708528dcaa2c5c0b3933a8d7f
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:24:18 2009 +0000
bnx2x: Beautify bnx2x_dump.h
commit 573f203574581faaf80ca4fc079d33452327fc3b
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:24:14 2009 +0000
bnx2x: Re-factor the initialization code
commit e4ed7113372a04df9b7aa985ce3860207dbb1141
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:24:10 2009 +0000
bnx2x: Using PCI_DEVICE macro
commit 0fc5d0094de11bb005c35f03fb1d3b52b0bd85e3
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:24:05 2009 +0000
bnx2x: Adding explicit casting
commit 659bc5c4f2e84e69e1b10b36c16cd52ff7eb317a
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:24:02 2009 +0000
bnx2x: Using macro for phy address
commit 1ef70b9c12407f0bf332ba775a8aa8f8035d0a24
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:59 2009 +0000
bnx2x: Re-arrange the link structures for better alignment
commit 8924665a7d77bb79ee895b98864e3201507f6ef2
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:56 2009 +0000
bnx2x: Missing smp_wmb for statistics state machine
commit 57937203aa077520a7e1665bfb7071b3cbb3f5a9
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:53 2009 +0000
bnx2x: Remove SGMII configuration when not required
commit 6f65497b567ef9a518d930ef30fe6b8f27051688
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:51 2009 +0000
bnx2x: Keep only one HW path active
commit 54016b260e873d0d4d30cf1fdbd0cdcf0e26251b
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:48 2009 +0000
bnx2x: Check unzip return code
commit 5ff7b6d4c129a430e355b2f88162a36d9e058f88
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:44 2009 +0000
bnx2x: Remove the init_dmae field from bp
commit 0d28e49a2616b927bca5fde0f16dfdfd2a501107
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:40 2009 +0000
bnx2x: Updating regdump_len at drvinfo
commit 938cf5416d59769ec2e7ce4eb7967cb3b61242a3
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:37 2009 +0000
bnx2x: Move printing of version from probe to the init
commit 37f9ce6231cafb2973e09f7f72ad62bc6348d1b3
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:34 2009 +0000
bnx2x: Combine get_pcie_width and get_pcie_speed
commit e3553b29c6f395c6692afccc2ed5eff9c3d1daef
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:31 2009 +0000
bnx2x: Stop loading if error condition detected
commit df4770de03d2eec3f66b0ac4d2248d471a1ccc0b
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:28 2009 +0000
bnx2x: Calling pci_set_drvdata earlier
commit a18f5128828cd1af8091602f5233b00422e74c9a
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:26 2009 +0000
bnx2x: Configurable pause scheme
commit a119a069349b6ad32807ff1b09e417cf23514020
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:23 2009 +0000
bnx2x: Adding Likely directive
commit 619e7a66b515f5f6b1cbe6f378f6a4ca3a65ac52
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:20 2009 +0000
bnx2x: Prefetch the page containing the BD descriptor
commit 6fe49bb978de3de0ba7ff9d6b2d55a15518db2a3
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:17 2009 +0000
bnx2x: Reporting host statistics to management FW
commit 239d686d494f10ecd83a89ddc4e31f9462ca4901
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:04 2009 +0000
bnx2x: Adding XAUI CL73 autoneg support
commit bc7f0a053021491e292fc00810c4f2a8524453dd
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:23:01 2009 +0000
bnx2x: BCM8727 FW load
commit 97b41dad385bce97d60b8cdd56342f07f93fc5d2
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:22:59 2009 +0000
bnx2x: get_ext_phy_fw_version returns NULL if not applicable
commit b1607af526fd408b244c7b32a0c256c1ef163a17
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:22:54 2009 +0000
bnx2x: Reading the FW version of the BCM8481 PHY
commit 2f9044603c8b9ead9eb4d88e360093b44d362b58
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:22:16 2009 +0000
bnx2x: BCM8481 LED4 instead of LASI
commit 0c593270432035b7b9ba27ee7dd4f32f6feea2e0
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:22:13 2009 +0000
bnx2x: Advertize flow control normally in MF mode
commit 2691d51d7243560aa0870dadbf5c6b98f647f751
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 08:22:08 2009 +0000
bnx2x: Supporting Device Control Channel
commit ca00392cb8f5227c67ff52c656d91a764d022ab9
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Aug 12 22:53:28 2009 -0700
bnx2x: Using the new FW
commit 07ce50e434b62c4de05207109ecd3d615b3cce42
Author: Dean Nelson <dnelson@redhat.com>
Date: Fri Jul 31 09:13:25 2009 +0000
bnx2x: return PCI_ERS_RESULT_DISCONNECT on permanent failure
commit 573dd788ccd919f90c78f971c0da124ffa4b8bff
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Jul 29 00:20:11 2009 +0000
bnx2x: Version 1.48.114-1
commit 7d0446c2349da54f2967fb34d984db572fbfc6ac
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Jul 29 00:20:10 2009 +0000
bnx2x: WoL only with current MAC address
commit c1f1a06f926acc267c62a26d5d7435a3b5c7e429
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Jul 29 00:20:08 2009 +0000
bnx2x: Self-test kills management traffic
commit 581ce43d269bb9f9ea85d8f6e6acf68bad129740
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Wed Jul 29 00:20:04 2009 +0000
bnx2x: Receive traffic that maches management filtering rules
commit 0376d5b25ef11e9b6450ebae20781a32d8985170
Author: Julia Lawall <julia@diku.dk>
Date: Sun Jul 19 05:26:35 2009 +0000
drivers/net: Move a dereference below a NULL test
commit e8834a63bddf87f7b85955d1ba60d28343d88469
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Tue Jul 21 05:47:55 2009 +0000
bnx2x: Version 1.48.113-1
commit 5b6402d10328beb8a9b351ac65a31326ed5fe847
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Tue Jul 21 05:47:51 2009 +0000
bnx2x: Missing parenthesis might result with wrong casting
commit ba71d3134176b9791aab7cb78242b6ba1428aac8
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Tue Jul 21 05:47:49 2009 +0000
bnx2x: Set LED in loopback test
commit e15107065d073714dc47cf6b80c8bf5eea1bf18b
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Tue Jul 21 05:47:41 2009 +0000
bnx2x: SMP-safe inter_sem
commit 37dbbf32a0d45f0ed88f92cb6d0c35f4809e3a8e
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Tue Jul 21 05:47:33 2009 +0000
bnx2x: Adding some mmiowb
commit eb8da205a6cac953a46a247b8dd19505eba944e2
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Tue Jul 21 05:47:30 2009 +0000
bnx2x: Fan failure early detection
commit fd4ef40d5977e1c226e9cd9659398e82cc4a1e85
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Tue Jul 21 05:47:27 2009 +0000
bnx2x: Fan failure
commit 279abdf59c766a06db89b50c6d3615b4f2b19ed3
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Tue Jul 21 05:47:22 2009 +0000
bnx2x: Stop management traffic in loopback test
commit ad361c9884e809340f6daca80d56a9e9c871690a
Author: Joe Perches <joe@perches.com>
Date: Mon Jul 6 13:05:40 2009 -0700
Remove multiple KERN_ prefixes from printk formats
commit 1e9d9987598fa58f4bd8e72ee152c879136d6723
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Sun Jul 5 04:18:14 2009 +0000
bnx2x: Fix the maximal values of coalescing timeouts.
commit 3799cf47e3497a472b05f88e7a52a14931597d78
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Sun Jul 5 04:18:12 2009 +0000
bnx2x: Disable HC coalescing when setting timeout to zero.
commit 01e532981460594fffbf9b992ecfc96a78369924
Author: Naohiro Ooiwa <nooiwa@miraclelinux.com>
Date: Tue Jun 30 12:44:19 2009 -0700
bnx2x: Fix the behavior of ethtool when ONBOOT=no
commit dd21ca6de703230785b755c8290365fc1640200e
Author: Stanislaw Gruszka <sgruszka@redhat.com>
Date: Tue May 5 23:22:01 2009 +0000
bnx2x: free workqueue when driver fail to register
commit 56ed4351c2604c221a82276f51e5dfd467921bf3
Author: Vladislav Zolotarov <vladz@broadcom.com>
Date: Mon Apr 27 03:28:25 2009 -0700
bnx2x: driver version 1.48.105-1
commit 94a78b79cb5f14c09a42522738d6694c6a1cdd20
Author: Vladislav Zolotarov <vladz@broadcom.com>
Date: Mon Apr 27 03:27:43 2009 -0700
bnx2x: Separated FW from the source.
commit 6dc7d8c843024c2636cf52d3f93047acbcd765f2
Author: Eilon Greenstein <eilong@broadcom.com>
Date: Mon Mar 9 00:52:17 2009 +0000
bnx2x: Casting page alignment
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 1fde4dc..a3eb3eb 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -87,6 +87,7 @@
} while (0)
#else
#define bnx2x_panic() do { \
+ bp->panic = 1; \
BNX2X_ERR("driver assert\n"); \
bnx2x_panic_dump(bp); \
} while (0)
@@ -113,21 +114,32 @@
#define REG_RD_DMAE(bp, offset, valp, len32) \
do { \
bnx2x_read_dmae(bp, offset, len32);\
- memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
+ memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
} while (0)
#define REG_WR_DMAE(bp, offset, valp, len32) \
do { \
- memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
+ memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
offset, len32); \
} while (0)
+#define VIRT_WR_DMAE_LEN(bp, data, addr, len32) \
+ do { \
+ memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
+ bnx2x_write_big_buf_wb(bp, addr, len32); \
+ } while (0)
+
#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
offsetof(struct shmem_region, field))
#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
+#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
+ offsetof(struct shmem2_region, field))
+#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
+#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
+
#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
@@ -142,6 +154,9 @@ struct sw_rx_bd {
struct sw_tx_bd {
struct sk_buff *skb;
u16 first_bd;
+ u8 flags;
+/* Set on the first BD descriptor when there is a split BD */
+#define BNX2X_TSO_SPLIT_BD (1<<0)
};
struct sw_rx_page {
@@ -149,6 +164,11 @@ struct sw_rx_page {
DECLARE_PCI_UNMAP_ADDR(mapping)
};
+union db_prod {
+ struct doorbell_set_prod data;
+ u32 raw;
+};
+
/* MC hsi */
#define BCM_PAGE_SHIFT 12
@@ -160,7 +180,7 @@ struct sw_rx_page {
#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
#define SGE_PAGE_SIZE PAGE_SIZE
#define SGE_PAGE_SHIFT PAGE_SHIFT
-#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN(addr)
+#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
/* SGE ring related macros */
#define NUM_RX_SGE_PAGES 2
@@ -234,15 +254,14 @@ struct bnx2x_fastpath {
struct net_device dummy_netdev;
+ u8 is_rx_queue;
+
struct host_status_block *status_blk;
dma_addr_t status_blk_mapping;
- struct eth_tx_db_data *hw_tx_prods;
- dma_addr_t tx_prods_mapping;
-
struct sw_tx_bd *tx_buf_ring;
- struct eth_tx_bd *tx_desc_ring;
+ union eth_tx_bd_types *tx_desc_ring;
dma_addr_t tx_desc_mapping;
struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
@@ -272,6 +291,8 @@ struct bnx2x_fastpath {
u8 cl_id; /* eth client id */
u8 sb_id; /* status block number in HW */
+ union db_prod tx_db;
+
u16 tx_pkt_prod;
u16 tx_pkt_cons;
u16 tx_bd_prod;
@@ -291,9 +312,11 @@ struct bnx2x_fastpath {
__le16 *rx_cons_sb;
__le16 *rx_bd_cons_sb;
+
unsigned long tx_pkt,
rx_pkt,
rx_calls;
+
/* TPA related */
struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
@@ -309,21 +332,24 @@ struct bnx2x_fastpath {
struct xstorm_per_client_stats old_xclient;
struct bnx2x_eth_q_stats eth_q_stats;
- char name[IFNAMSIZ];
+ /* The size is calculated using the following:
+ sizeof name field from netdev structure +
+ 4 ('-Xx-' string) +
+ 4 (for the digits and to make it DWORD aligned) */
+#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
+ char name[FP_NAME_SIZE];
struct bnx2x *bp; /* parent */
};
#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
-#define BNX2X_HAS_WORK(fp) (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))
-
/* MC hsi */
#define MAX_FETCH_BD 13 /* HW max BDs per packet */
#define RX_COPY_THRESH 92
#define NUM_TX_RINGS 16
-#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
+#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
#define MAX_TX_BD (NUM_TX_BD - 1)
@@ -395,7 +421,7 @@ struct bnx2x_fastpath {
#define DPM_TRIGER_TYPE 0x40
#define DOORBELL(bp, cid, val) \
do { \
- writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
+ writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
DPM_TRIGER_TYPE); \
} while (0)
@@ -523,6 +549,7 @@ struct bnx2x_common {
#define NVRAM_PAGE_SIZE 256
u32 shmem_base;
+ u32 shmem2_base;
u32 hw_config;
@@ -757,6 +784,7 @@ struct bnx2x_slowpath {
struct nig_stats nig_stats;
struct host_port_stats port_stats;
struct host_func_stats func_stats;
+ struct host_func_stats func_stats_base;
u32 wb_comp;
u32 wb_data[4];
@@ -945,10 +973,11 @@ struct bnx2x {
dma_addr_t qm_mapping;
#endif
+ int dropless_fc;
+
int dmae_ready;
/* used to synchronize dmae accesses */
struct mutex dmae_mutex;
- struct dmae_command init_dmae;
/* used to synchronize stats collecting */
int stats_state;
@@ -966,23 +995,54 @@ struct bnx2x {
dma_addr_t gunzip_mapping;
int gunzip_outlen;
#define FW_BUF_SIZE 0x8000
-
+#define GUNZIP_BUF(bp) (bp->gunzip_buf)
+#define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
+#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
+
+ struct raw_op *init_ops;
+ /* Init blocks offsets inside init_ops */
+ u16 *init_ops_offsets;
+ /* Data blob - has 32 bit granularity */
+ u32 *init_data;
+ /* Zipped PRAM blobs - raw data */
+ const u8 *tsem_int_table_data;
+ const u8 *tsem_pram_data;
+ const u8 *usem_int_table_data;
+ const u8 *usem_pram_data;
+ const u8 *xsem_int_table_data;
+ const u8 *xsem_pram_data;
+ const u8 *csem_int_table_data;
+ const u8 *csem_pram_data;
+#define INIT_OPS(bp) (bp->init_ops)
+#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
+#define INIT_DATA(bp) (bp->init_data)
+#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
+#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
+#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
+#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
+#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
+#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
+#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
+#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
+
+ const struct firmware *firmware;
};
-#define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT / E1HVN_MAX) : \
- MAX_CONTEXT)
-#define BNX2X_NUM_QUEUES(bp) max(bp->num_rx_queues, bp->num_tx_queues)
-#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
+#define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/(2 * E1HVN_MAX)) \
+ : (MAX_CONTEXT/2))
+#define BNX2X_NUM_QUEUES(bp) (bp->num_rx_queues + bp->num_tx_queues)
+#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 2)
#define for_each_rx_queue(bp, var) \
for (var = 0; var < bp->num_rx_queues; var++)
#define for_each_tx_queue(bp, var) \
- for (var = 0; var < bp->num_tx_queues; var++)
+ for (var = bp->num_rx_queues; \
+ var < BNX2X_NUM_QUEUES(bp); var++)
#define for_each_queue(bp, var) \
for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
#define for_each_nondefault_queue(bp, var) \
- for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
+ for (var = 1; var < bp->num_rx_queues; var++)
void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
@@ -992,6 +1052,9 @@ int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
+void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
+void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
+ u32 addr, u32 len);
static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
int wait)
@@ -1049,9 +1112,9 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
#define DMAE_COMP_VAL 0xe0d0d0ae
#define MAX_DMAE_C_PER_PORT 8
-#define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
+#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
BP_E1HVN(bp))
-#define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
+#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
E1HVN_MAX)
@@ -1076,7 +1139,8 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
/* must be used on a CID before placing it on a HW ring */
-#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
+#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
+ (BP_E1HVN(bp) << 17) | (x))
#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
@@ -1164,8 +1228,8 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
- AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
- AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
@@ -1193,7 +1257,6 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
(bp->multi_mode << \
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
-
#define MULTI_MASK 0x7f
diff --git a/drivers/net/bnx2x_dump.h b/drivers/net/bnx2x_dump.h
index 78c6b03..3bb9a91 100644
--- a/drivers/net/bnx2x_dump.h
+++ b/drivers/net/bnx2x_dump.h
@@ -13,31 +13,35 @@
* The signature is time stamp, diag version and grc_dump version
*/
+#ifndef BNX2X_DUMP_H
+#define BNX2X_DUMP_H
+
+
struct dump_sign {
u32 time_stamp;
u32 diag_ver;
u32 grc_dump_ver;
};
-#define TSTORM_WAITP_ADDR 0x1b8a80
-#define CSTORM_WAITP_ADDR 0x238a80
-#define XSTORM_WAITP_ADDR 0x2b8a80
-#define USTORM_WAITP_ADDR 0x338a80
-#define TSTORM_CAM_MODE 0x1b1440
+#define TSTORM_WAITP_ADDR 0x1b8a80
+#define CSTORM_WAITP_ADDR 0x238a80
+#define XSTORM_WAITP_ADDR 0x2b8a80
+#define USTORM_WAITP_ADDR 0x338a80
+#define TSTORM_CAM_MODE 0x1b1440
-#define RI_E1 0x1
-#define RI_E1H 0x2
-#define RI_ONLINE 0x100
+#define RI_E1 0x1
+#define RI_E1H 0x2
+#define RI_ONLINE 0x100
-#define RI_E1_OFFLINE (RI_E1)
-#define RI_E1_ONLINE (RI_E1 | RI_ONLINE)
-#define RI_E1H_OFFLINE (RI_E1H)
-#define RI_E1H_ONLINE (RI_E1H | RI_ONLINE)
-#define RI_ALL_OFFLINE (RI_E1 | RI_E1H)
-#define RI_ALL_ONLINE (RI_E1 | RI_E1H | RI_ONLINE)
+#define RI_E1_OFFLINE (RI_E1)
+#define RI_E1_ONLINE (RI_E1 | RI_ONLINE)
+#define RI_E1H_OFFLINE (RI_E1H)
+#define RI_E1H_ONLINE (RI_E1H | RI_ONLINE)
+#define RI_ALL_OFFLINE (RI_E1 | RI_E1H)
+#define RI_ALL_ONLINE (RI_E1 | RI_E1H | RI_ONLINE)
-#define MAX_TIMER_PENDING 200
-#define TIMER_SCAN_DONT_CARE 0xFF
+#define MAX_TIMER_PENDING 200
+#define TIMER_SCAN_DONT_CARE 0xFF
struct dump_hdr {
@@ -67,443 +71,444 @@ struct wreg_addr {
};
-#define REGS_COUNT 558
+#define REGS_COUNT 558
static const struct reg_addr reg_addrs[REGS_COUNT] = {
- { 0x2000, 341, RI_ALL_ONLINE}, { 0x2800, 103, RI_ALL_ONLINE},
- { 0x3000, 287, RI_ALL_ONLINE}, { 0x3800, 331, RI_ALL_ONLINE},
- { 0x8800, 6, RI_E1_ONLINE}, { 0xa000, 223, RI_ALL_ONLINE},
- { 0xa388, 1, RI_ALL_ONLINE}, { 0xa398, 1, RI_ALL_ONLINE},
- { 0xa39c, 7, RI_E1H_ONLINE}, { 0xa3c0, 3, RI_E1H_ONLINE},
- { 0xa3d0, 1, RI_E1H_ONLINE}, { 0xa3d8, 1, RI_E1H_ONLINE},
- { 0xa3e0, 1, RI_E1H_ONLINE}, { 0xa3e8, 1, RI_E1H_ONLINE},
- { 0xa3f0, 1, RI_E1H_ONLINE}, { 0xa3f8, 1, RI_E1H_ONLINE},
- { 0xa400, 69, RI_ALL_ONLINE}, { 0xa518, 1, RI_ALL_ONLINE},
- { 0xa520, 1, RI_ALL_ONLINE}, { 0xa528, 1, RI_ALL_ONLINE},
- { 0xa530, 1, RI_ALL_ONLINE}, { 0xa538, 1, RI_ALL_ONLINE},
- { 0xa540, 1, RI_ALL_ONLINE}, { 0xa548, 1, RI_ALL_ONLINE},
- { 0xa550, 1, RI_ALL_ONLINE}, { 0xa558, 1, RI_ALL_ONLINE},
- { 0xa560, 1, RI_ALL_ONLINE}, { 0xa568, 1, RI_ALL_ONLINE},
- { 0xa570, 1, RI_ALL_ONLINE}, { 0xa580, 1, RI_ALL_ONLINE},
- { 0xa590, 1, RI_ALL_ONLINE}, { 0xa5a0, 1, RI_ALL_ONLINE},
- { 0xa5c0, 1, RI_ALL_ONLINE}, { 0xa5e0, 1, RI_E1H_ONLINE},
- { 0xa5e8, 1, RI_E1H_ONLINE}, { 0xa5f0, 1, RI_E1H_ONLINE},
- { 0xa5f8, 10, RI_E1H_ONLINE}, { 0x10000, 236, RI_ALL_ONLINE},
- { 0x103bc, 1, RI_ALL_ONLINE}, { 0x103cc, 1, RI_ALL_ONLINE},
- { 0x103dc, 1, RI_ALL_ONLINE}, { 0x10400, 57, RI_ALL_ONLINE},
- { 0x104e8, 2, RI_ALL_ONLINE}, { 0x104f4, 2, RI_ALL_ONLINE},
- { 0x10500, 146, RI_ALL_ONLINE}, { 0x10750, 2, RI_ALL_ONLINE},
- { 0x10760, 2, RI_ALL_ONLINE}, { 0x10770, 2, RI_ALL_ONLINE},
- { 0x10780, 2, RI_ALL_ONLINE}, { 0x10790, 2, RI_ALL_ONLINE},
- { 0x107a0, 2, RI_ALL_ONLINE}, { 0x107b0, 2, RI_ALL_ONLINE},
- { 0x107c0, 2, RI_ALL_ONLINE}, { 0x107d0, 2, RI_ALL_ONLINE},
- { 0x107e0, 2, RI_ALL_ONLINE}, { 0x10880, 2, RI_ALL_ONLINE},
- { 0x10900, 2, RI_ALL_ONLINE}, { 0x12000, 1, RI_ALL_ONLINE},
- { 0x14000, 1, RI_ALL_ONLINE}, { 0x16000, 26, RI_E1H_ONLINE},
- { 0x16070, 18, RI_E1H_ONLINE}, { 0x160c0, 27, RI_E1H_ONLINE},
- { 0x16140, 1, RI_E1H_ONLINE}, { 0x16160, 1, RI_E1H_ONLINE},
- { 0x16180, 2, RI_E1H_ONLINE}, { 0x161c0, 2, RI_E1H_ONLINE},
- { 0x16204, 5, RI_E1H_ONLINE}, { 0x18000, 1, RI_E1H_ONLINE},
- { 0x18008, 1, RI_E1H_ONLINE}, { 0x20000, 24, RI_ALL_ONLINE},
- { 0x20060, 8, RI_ALL_ONLINE}, { 0x20080, 138, RI_ALL_ONLINE},
- { 0x202b4, 1, RI_ALL_ONLINE}, { 0x202c4, 1, RI_ALL_ONLINE},
- { 0x20400, 2, RI_ALL_ONLINE}, { 0x2040c, 8, RI_ALL_ONLINE},
- { 0x2042c, 18, RI_E1H_ONLINE}, { 0x20480, 1, RI_ALL_ONLINE},
- { 0x20500, 1, RI_ALL_ONLINE}, { 0x20600, 1, RI_ALL_ONLINE},
- { 0x28000, 1, RI_ALL_ONLINE}, { 0x28004, 8191, RI_ALL_OFFLINE},
- { 0x30000, 1, RI_ALL_ONLINE}, { 0x30004, 16383, RI_ALL_OFFLINE},
- { 0x40000, 98, RI_ALL_ONLINE}, { 0x40194, 1, RI_ALL_ONLINE},
- { 0x401a4, 1, RI_ALL_ONLINE}, { 0x401a8, 11, RI_E1H_ONLINE},
- { 0x40200, 4, RI_ALL_ONLINE}, { 0x40400, 43, RI_ALL_ONLINE},
- { 0x404b8, 1, RI_ALL_ONLINE}, { 0x404c8, 1, RI_ALL_ONLINE},
- { 0x404cc, 3, RI_E1H_ONLINE}, { 0x40500, 2, RI_ALL_ONLINE},
- { 0x40510, 2, RI_ALL_ONLINE}, { 0x40520, 2, RI_ALL_ONLINE},
- { 0x40530, 2, RI_ALL_ONLINE}, { 0x40540, 2, RI_ALL_ONLINE},
- { 0x42000, 164, RI_ALL_ONLINE}, { 0x4229c, 1, RI_ALL_ONLINE},
- { 0x422ac, 1, RI_ALL_ONLINE}, { 0x422bc, 1, RI_ALL_ONLINE},
- { 0x422d4, 5, RI_E1H_ONLINE}, { 0x42400, 49, RI_ALL_ONLINE},
- { 0x424c8, 38, RI_ALL_ONLINE}, { 0x42568, 2, RI_ALL_ONLINE},
- { 0x42800, 1, RI_ALL_ONLINE}, { 0x50000, 20, RI_ALL_ONLINE},
- { 0x50050, 8, RI_ALL_ONLINE}, { 0x50070, 88, RI_ALL_ONLINE},
- { 0x501dc, 1, RI_ALL_ONLINE}, { 0x501ec, 1, RI_ALL_ONLINE},
- { 0x501f0, 4, RI_E1H_ONLINE}, { 0x50200, 2, RI_ALL_ONLINE},
- { 0x5020c, 7, RI_ALL_ONLINE}, { 0x50228, 6, RI_E1H_ONLINE},
- { 0x50240, 1, RI_ALL_ONLINE}, { 0x50280, 1, RI_ALL_ONLINE},
- { 0x52000, 1, RI_ALL_ONLINE}, { 0x54000, 1, RI_ALL_ONLINE},
- { 0x54004, 3327, RI_ALL_OFFLINE}, { 0x58000, 1, RI_ALL_ONLINE},
- { 0x58004, 8191, RI_ALL_OFFLINE}, { 0x60000, 71, RI_ALL_ONLINE},
- { 0x60128, 1, RI_ALL_ONLINE}, { 0x60138, 1, RI_ALL_ONLINE},
- { 0x6013c, 24, RI_E1H_ONLINE}, { 0x60200, 1, RI_ALL_ONLINE},
- { 0x61000, 1, RI_ALL_ONLINE}, { 0x61004, 511, RI_ALL_OFFLINE},
- { 0x70000, 8, RI_ALL_ONLINE}, { 0x70020, 21496, RI_ALL_OFFLINE},
- { 0x85000, 3, RI_ALL_ONLINE}, { 0x8500c, 4, RI_ALL_OFFLINE},
- { 0x8501c, 7, RI_ALL_ONLINE}, { 0x85038, 4, RI_ALL_OFFLINE},
- { 0x85048, 1, RI_ALL_ONLINE}, { 0x8504c, 109, RI_ALL_OFFLINE},
- { 0x85200, 32, RI_ALL_ONLINE}, { 0x85280, 11104, RI_ALL_OFFLINE},
- { 0xa0000, 16384, RI_ALL_ONLINE}, { 0xb0000, 16384, RI_E1H_ONLINE},
- { 0xc1000, 7, RI_ALL_ONLINE}, { 0xc1028, 1, RI_ALL_ONLINE},
- { 0xc1038, 1, RI_ALL_ONLINE}, { 0xc1800, 2, RI_ALL_ONLINE},
- { 0xc2000, 164, RI_ALL_ONLINE}, { 0xc229c, 1, RI_ALL_ONLINE},
- { 0xc22ac, 1, RI_ALL_ONLINE}, { 0xc22bc, 1, RI_ALL_ONLINE},
- { 0xc2400, 49, RI_ALL_ONLINE}, { 0xc24c8, 38, RI_ALL_ONLINE},
- { 0xc2568, 2, RI_ALL_ONLINE}, { 0xc2600, 1, RI_ALL_ONLINE},
- { 0xc4000, 165, RI_ALL_ONLINE}, { 0xc42a0, 1, RI_ALL_ONLINE},
- { 0xc42b0, 1, RI_ALL_ONLINE}, { 0xc42c0, 1, RI_ALL_ONLINE},
- { 0xc42e0, 7, RI_E1H_ONLINE}, { 0xc4400, 51, RI_ALL_ONLINE},
- { 0xc44d0, 38, RI_ALL_ONLINE}, { 0xc4570, 2, RI_ALL_ONLINE},
- { 0xc4600, 1, RI_ALL_ONLINE}, { 0xd0000, 19, RI_ALL_ONLINE},
- { 0xd004c, 8, RI_ALL_ONLINE}, { 0xd006c, 91, RI_ALL_ONLINE},
- { 0xd01e4, 1, RI_ALL_ONLINE}, { 0xd01f4, 1, RI_ALL_ONLINE},
- { 0xd0200, 2, RI_ALL_ONLINE}, { 0xd020c, 7, RI_ALL_ONLINE},
- { 0xd0228, 18, RI_E1H_ONLINE}, { 0xd0280, 1, RI_ALL_ONLINE},
- { 0xd0300, 1, RI_ALL_ONLINE}, { 0xd0400, 1, RI_ALL_ONLINE},
- { 0xd4000, 1, RI_ALL_ONLINE}, { 0xd4004, 2559, RI_ALL_OFFLINE},
- { 0xd8000, 1, RI_ALL_ONLINE}, { 0xd8004, 8191, RI_ALL_OFFLINE},
- { 0xe0000, 21, RI_ALL_ONLINE}, { 0xe0054, 8, RI_ALL_ONLINE},
- { 0xe0074, 85, RI_ALL_ONLINE}, { 0xe01d4, 1, RI_ALL_ONLINE},
- { 0xe01e4, 1, RI_ALL_ONLINE}, { 0xe0200, 2, RI_ALL_ONLINE},
- { 0xe020c, 8, RI_ALL_ONLINE}, { 0xe022c, 18, RI_E1H_ONLINE},
- { 0xe0280, 1, RI_ALL_ONLINE}, { 0xe0300, 1, RI_ALL_ONLINE},
- { 0xe1000, 1, RI_ALL_ONLINE}, { 0xe2000, 1, RI_ALL_ONLINE},
- { 0xe2004, 2047, RI_ALL_OFFLINE}, { 0xf0000, 1, RI_ALL_ONLINE},
- { 0xf0004, 16383, RI_ALL_OFFLINE}, { 0x101000, 12, RI_ALL_ONLINE},
- { 0x10103c, 1, RI_ALL_ONLINE}, { 0x10104c, 1, RI_ALL_ONLINE},
- { 0x101050, 1, RI_E1H_ONLINE}, { 0x101100, 1, RI_ALL_ONLINE},
- { 0x101800, 8, RI_ALL_ONLINE}, { 0x102000, 18, RI_ALL_ONLINE},
- { 0x102054, 1, RI_ALL_ONLINE}, { 0x102064, 1, RI_ALL_ONLINE},
- { 0x102080, 17, RI_ALL_ONLINE}, { 0x1020c8, 8, RI_E1H_ONLINE},
- { 0x102400, 1, RI_ALL_ONLINE}, { 0x103000, 26, RI_ALL_ONLINE},
- { 0x103074, 1, RI_ALL_ONLINE}, { 0x103084, 1, RI_ALL_ONLINE},
- { 0x103094, 1, RI_ALL_ONLINE}, { 0x103098, 5, RI_E1H_ONLINE},
- { 0x103800, 8, RI_ALL_ONLINE}, { 0x104000, 63, RI_ALL_ONLINE},
- { 0x104108, 1, RI_ALL_ONLINE}, { 0x104118, 1, RI_ALL_ONLINE},
- { 0x104200, 17, RI_ALL_ONLINE}, { 0x104400, 64, RI_ALL_ONLINE},
- { 0x104500, 192, RI_ALL_OFFLINE}, { 0x104800, 64, RI_ALL_ONLINE},
- { 0x104900, 192, RI_ALL_OFFLINE}, { 0x105000, 7, RI_ALL_ONLINE},
- { 0x10501c, 1, RI_ALL_OFFLINE}, { 0x105020, 3, RI_ALL_ONLINE},
- { 0x10502c, 1, RI_ALL_OFFLINE}, { 0x105030, 3, RI_ALL_ONLINE},
- { 0x10503c, 1, RI_ALL_OFFLINE}, { 0x105040, 3, RI_ALL_ONLINE},
- { 0x10504c, 1, RI_ALL_OFFLINE}, { 0x105050, 3, RI_ALL_ONLINE},
- { 0x10505c, 1, RI_ALL_OFFLINE}, { 0x105060, 3, RI_ALL_ONLINE},
- { 0x10506c, 1, RI_ALL_OFFLINE}, { 0x105070, 3, RI_ALL_ONLINE},
- { 0x10507c, 1, RI_ALL_OFFLINE}, { 0x105080, 3, RI_ALL_ONLINE},
- { 0x10508c, 1, RI_ALL_OFFLINE}, { 0x105090, 3, RI_ALL_ONLINE},
- { 0x10509c, 1, RI_ALL_OFFLINE}, { 0x1050a0, 3, RI_ALL_ONLINE},
- { 0x1050ac, 1, RI_ALL_OFFLINE}, { 0x1050b0, 3, RI_ALL_ONLINE},
- { 0x1050bc, 1, RI_ALL_OFFLINE}, { 0x1050c0, 3, RI_ALL_ONLINE},
- { 0x1050cc, 1, RI_ALL_OFFLINE}, { 0x1050d0, 3, RI_ALL_ONLINE},
- { 0x1050dc, 1, RI_ALL_OFFLINE}, { 0x1050e0, 3, RI_ALL_ONLINE},
- { 0x1050ec, 1, RI_ALL_OFFLINE}, { 0x1050f0, 3, RI_ALL_ONLINE},
- { 0x1050fc, 1, RI_ALL_OFFLINE}, { 0x105100, 3, RI_ALL_ONLINE},
- { 0x10510c, 1, RI_ALL_OFFLINE}, { 0x105110, 3, RI_ALL_ONLINE},
- { 0x10511c, 1, RI_ALL_OFFLINE}, { 0x105120, 3, RI_ALL_ONLINE},
- { 0x10512c, 1, RI_ALL_OFFLINE}, { 0x105130, 3, RI_ALL_ONLINE},
- { 0x10513c, 1, RI_ALL_OFFLINE}, { 0x105140, 3, RI_ALL_ONLINE},
- { 0x10514c, 1, RI_ALL_OFFLINE}, { 0x105150, 3, RI_ALL_ONLINE},
- { 0x10515c, 1, RI_ALL_OFFLINE}, { 0x105160, 3, RI_ALL_ONLINE},
- { 0x10516c, 1, RI_ALL_OFFLINE}, { 0x105170, 3, RI_ALL_ONLINE},
- { 0x10517c, 1, RI_ALL_OFFLINE}, { 0x105180, 3, RI_ALL_ONLINE},
- { 0x10518c, 1, RI_ALL_OFFLINE}, { 0x105190, 3, RI_ALL_ONLINE},
- { 0x10519c, 1, RI_ALL_OFFLINE}, { 0x1051a0, 3, RI_ALL_ONLINE},
- { 0x1051ac, 1, RI_ALL_OFFLINE}, { 0x1051b0, 3, RI_ALL_ONLINE},
- { 0x1051bc, 1, RI_ALL_OFFLINE}, { 0x1051c0, 3, RI_ALL_ONLINE},
- { 0x1051cc, 1, RI_ALL_OFFLINE}, { 0x1051d0, 3, RI_ALL_ONLINE},
- { 0x1051dc, 1, RI_ALL_OFFLINE}, { 0x1051e0, 3, RI_ALL_ONLINE},
- { 0x1051ec, 1, RI_ALL_OFFLINE}, { 0x1051f0, 3, RI_ALL_ONLINE},
- { 0x1051fc, 1, RI_ALL_OFFLINE}, { 0x105200, 3, RI_ALL_ONLINE},
- { 0x10520c, 1, RI_ALL_OFFLINE}, { 0x105210, 3, RI_ALL_ONLINE},
- { 0x10521c, 1, RI_ALL_OFFLINE}, { 0x105220, 3, RI_ALL_ONLINE},
- { 0x10522c, 1, RI_ALL_OFFLINE}, { 0x105230, 3, RI_ALL_ONLINE},
- { 0x10523c, 1, RI_ALL_OFFLINE}, { 0x105240, 3, RI_ALL_ONLINE},
- { 0x10524c, 1, RI_ALL_OFFLINE}, { 0x105250, 3, RI_ALL_ONLINE},
- { 0x10525c, 1, RI_ALL_OFFLINE}, { 0x105260, 3, RI_ALL_ONLINE},
- { 0x10526c, 1, RI_ALL_OFFLINE}, { 0x105270, 3, RI_ALL_ONLINE},
- { 0x10527c, 1, RI_ALL_OFFLINE}, { 0x105280, 3, RI_ALL_ONLINE},
- { 0x10528c, 1, RI_ALL_OFFLINE}, { 0x105290, 3, RI_ALL_ONLINE},
- { 0x10529c, 1, RI_ALL_OFFLINE}, { 0x1052a0, 3, RI_ALL_ONLINE},
- { 0x1052ac, 1, RI_ALL_OFFLINE}, { 0x1052b0, 3, RI_ALL_ONLINE},
- { 0x1052bc, 1, RI_ALL_OFFLINE}, { 0x1052c0, 3, RI_ALL_ONLINE},
- { 0x1052cc, 1, RI_ALL_OFFLINE}, { 0x1052d0, 3, RI_ALL_ONLINE},
- { 0x1052dc, 1, RI_ALL_OFFLINE}, { 0x1052e0, 3, RI_ALL_ONLINE},
- { 0x1052ec, 1, RI_ALL_OFFLINE}, { 0x1052f0, 3, RI_ALL_ONLINE},
- { 0x1052fc, 1, RI_ALL_OFFLINE}, { 0x105300, 3, RI_ALL_ONLINE},
- { 0x10530c, 1, RI_ALL_OFFLINE}, { 0x105310, 3, RI_ALL_ONLINE},
- { 0x10531c, 1, RI_ALL_OFFLINE}, { 0x105320, 3, RI_ALL_ONLINE},
- { 0x10532c, 1, RI_ALL_OFFLINE}, { 0x105330, 3, RI_ALL_ONLINE},
- { 0x10533c, 1, RI_ALL_OFFLINE}, { 0x105340, 3, RI_ALL_ONLINE},
- { 0x10534c, 1, RI_ALL_OFFLINE}, { 0x105350, 3, RI_ALL_ONLINE},
- { 0x10535c, 1, RI_ALL_OFFLINE}, { 0x105360, 3, RI_ALL_ONLINE},
- { 0x10536c, 1, RI_ALL_OFFLINE}, { 0x105370, 3, RI_ALL_ONLINE},
- { 0x10537c, 1, RI_ALL_OFFLINE}, { 0x105380, 3, RI_ALL_ONLINE},
- { 0x10538c, 1, RI_ALL_OFFLINE}, { 0x105390, 3, RI_ALL_ONLINE},
- { 0x10539c, 1, RI_ALL_OFFLINE}, { 0x1053a0, 3, RI_ALL_ONLINE},
- { 0x1053ac, 1, RI_ALL_OFFLINE}, { 0x1053b0, 3, RI_ALL_ONLINE},
- { 0x1053bc, 1, RI_ALL_OFFLINE}, { 0x1053c0, 3, RI_ALL_ONLINE},
- { 0x1053cc, 1, RI_ALL_OFFLINE}, { 0x1053d0, 3, RI_ALL_ONLINE},
- { 0x1053dc, 1, RI_ALL_OFFLINE}, { 0x1053e0, 3, RI_ALL_ONLINE},
- { 0x1053ec, 1, RI_ALL_OFFLINE}, { 0x1053f0, 3, RI_ALL_ONLINE},
- { 0x1053fc, 769, RI_ALL_OFFLINE}, { 0x108000, 33, RI_ALL_ONLINE},
- { 0x108090, 1, RI_ALL_ONLINE}, { 0x1080a0, 1, RI_ALL_ONLINE},
- { 0x1080ac, 5, RI_E1H_ONLINE}, { 0x108100, 5, RI_ALL_ONLINE},
- { 0x108120, 5, RI_ALL_ONLINE}, { 0x108200, 74, RI_ALL_ONLINE},
- { 0x108400, 74, RI_ALL_ONLINE}, { 0x108800, 152, RI_ALL_ONLINE},
- { 0x109000, 1, RI_ALL_ONLINE}, { 0x120000, 347, RI_ALL_ONLINE},
- { 0x120578, 1, RI_ALL_ONLINE}, { 0x120588, 1, RI_ALL_ONLINE},
- { 0x120598, 1, RI_ALL_ONLINE}, { 0x12059c, 23, RI_E1H_ONLINE},
- { 0x120614, 1, RI_E1H_ONLINE}, { 0x12061c, 30, RI_E1H_ONLINE},
- { 0x12080c, 65, RI_ALL_ONLINE}, { 0x120a00, 2, RI_ALL_ONLINE},
- { 0x122000, 2, RI_ALL_ONLINE}, { 0x128000, 2, RI_E1H_ONLINE},
- { 0x140000, 114, RI_ALL_ONLINE}, { 0x1401d4, 1, RI_ALL_ONLINE},
- { 0x1401e4, 1, RI_ALL_ONLINE}, { 0x140200, 6, RI_ALL_ONLINE},
- { 0x144000, 4, RI_ALL_ONLINE}, { 0x148000, 4, RI_ALL_ONLINE},
- { 0x14c000, 4, RI_ALL_ONLINE}, { 0x150000, 4, RI_ALL_ONLINE},
- { 0x154000, 4, RI_ALL_ONLINE}, { 0x158000, 4, RI_ALL_ONLINE},
- { 0x15c000, 7, RI_E1H_ONLINE}, { 0x161000, 7, RI_ALL_ONLINE},
- { 0x161028, 1, RI_ALL_ONLINE}, { 0x161038, 1, RI_ALL_ONLINE},
- { 0x161800, 2, RI_ALL_ONLINE}, { 0x164000, 60, RI_ALL_ONLINE},
- { 0x1640fc, 1, RI_ALL_ONLINE}, { 0x16410c, 1, RI_ALL_ONLINE},
- { 0x164110, 2, RI_E1H_ONLINE}, { 0x164200, 1, RI_ALL_ONLINE},
- { 0x164208, 1, RI_ALL_ONLINE}, { 0x164210, 1, RI_ALL_ONLINE},
- { 0x164218, 1, RI_ALL_ONLINE}, { 0x164220, 1, RI_ALL_ONLINE},
- { 0x164228, 1, RI_ALL_ONLINE}, { 0x164230, 1, RI_ALL_ONLINE},
- { 0x164238, 1, RI_ALL_ONLINE}, { 0x164240, 1, RI_ALL_ONLINE},
- { 0x164248, 1, RI_ALL_ONLINE}, { 0x164250, 1, RI_ALL_ONLINE},
- { 0x164258, 1, RI_ALL_ONLINE}, { 0x164260, 1, RI_ALL_ONLINE},
- { 0x164270, 2, RI_ALL_ONLINE}, { 0x164280, 2, RI_ALL_ONLINE},
- { 0x164800, 2, RI_ALL_ONLINE}, { 0x165000, 2, RI_ALL_ONLINE},
- { 0x166000, 164, RI_ALL_ONLINE}, { 0x16629c, 1, RI_ALL_ONLINE},
- { 0x1662ac, 1, RI_ALL_ONLINE}, { 0x1662bc, 1, RI_ALL_ONLINE},
- { 0x166400, 49, RI_ALL_ONLINE}, { 0x1664c8, 38, RI_ALL_ONLINE},
- { 0x166568, 2, RI_ALL_ONLINE}, { 0x166800, 1, RI_ALL_ONLINE},
- { 0x168000, 270, RI_ALL_ONLINE}, { 0x168444, 1, RI_ALL_ONLINE},
- { 0x168454, 1, RI_ALL_ONLINE}, { 0x168800, 19, RI_ALL_ONLINE},
- { 0x168900, 1, RI_ALL_ONLINE}, { 0x168a00, 128, RI_ALL_ONLINE},
- { 0x16a000, 1, RI_ALL_ONLINE}, { 0x16a004, 1535, RI_ALL_OFFLINE},
- { 0x16c000, 1, RI_ALL_ONLINE}, { 0x16c004, 1535, RI_ALL_OFFLINE},
- { 0x16e000, 16, RI_E1H_ONLINE}, { 0x16e100, 1, RI_E1H_ONLINE},
- { 0x16e200, 2, RI_E1H_ONLINE}, { 0x16e400, 183, RI_E1H_ONLINE},
- { 0x170000, 93, RI_ALL_ONLINE}, { 0x170180, 1, RI_ALL_ONLINE},
- { 0x170190, 1, RI_ALL_ONLINE}, { 0x170200, 4, RI_ALL_ONLINE},
- { 0x170214, 1, RI_ALL_ONLINE}, { 0x178000, 1, RI_ALL_ONLINE},
- { 0x180000, 61, RI_ALL_ONLINE}, { 0x180100, 1, RI_ALL_ONLINE},
- { 0x180110, 1, RI_ALL_ONLINE}, { 0x180120, 1, RI_ALL_ONLINE},
- { 0x180130, 1, RI_ALL_ONLINE}, { 0x18013c, 2, RI_E1H_ONLINE},
- { 0x180200, 58, RI_ALL_ONLINE}, { 0x180340, 4, RI_ALL_ONLINE},
- { 0x180400, 1, RI_ALL_ONLINE}, { 0x180404, 255, RI_ALL_OFFLINE},
- { 0x181000, 4, RI_ALL_ONLINE}, { 0x181010, 1020, RI_ALL_OFFLINE},
- { 0x1a0000, 1, RI_ALL_ONLINE}, { 0x1a0004, 1023, RI_ALL_OFFLINE},
- { 0x1a1000, 1, RI_ALL_ONLINE}, { 0x1a1004, 4607, RI_ALL_OFFLINE},
- { 0x1a5800, 2560, RI_E1H_OFFLINE}, { 0x1a8000, 64, RI_ALL_OFFLINE},
- { 0x1a8100, 1984, RI_E1H_OFFLINE}, { 0x1aa000, 1, RI_E1H_ONLINE},
- { 0x1aa004, 6655, RI_E1H_OFFLINE}, { 0x1b1800, 128, RI_ALL_OFFLINE},
- { 0x1b1c00, 128, RI_ALL_OFFLINE}, { 0x1b2000, 1, RI_ALL_OFFLINE},
- { 0x1b2400, 64, RI_E1H_OFFLINE}, { 0x1b8200, 1, RI_ALL_ONLINE},
- { 0x1b8240, 1, RI_ALL_ONLINE}, { 0x1b8280, 1, RI_ALL_ONLINE},
- { 0x1b82c0, 1, RI_ALL_ONLINE}, { 0x1b8a00, 1, RI_ALL_ONLINE},
- { 0x1b8a80, 1, RI_ALL_ONLINE}, { 0x1c0000, 2, RI_ALL_ONLINE},
- { 0x200000, 65, RI_ALL_ONLINE}, { 0x200110, 1, RI_ALL_ONLINE},
- { 0x200120, 1, RI_ALL_ONLINE}, { 0x200130, 1, RI_ALL_ONLINE},
- { 0x200140, 1, RI_ALL_ONLINE}, { 0x20014c, 2, RI_E1H_ONLINE},
- { 0x200200, 58, RI_ALL_ONLINE}, { 0x200340, 4, RI_ALL_ONLINE},
- { 0x200400, 1, RI_ALL_ONLINE}, { 0x200404, 255, RI_ALL_OFFLINE},
- { 0x202000, 4, RI_ALL_ONLINE}, { 0x202010, 2044, RI_ALL_OFFLINE},
- { 0x220000, 1, RI_ALL_ONLINE}, { 0x220004, 1023, RI_ALL_OFFLINE},
- { 0x221000, 1, RI_ALL_ONLINE}, { 0x221004, 4607, RI_ALL_OFFLINE},
- { 0x225800, 1536, RI_E1H_OFFLINE}, { 0x227000, 1, RI_E1H_ONLINE},
- { 0x227004, 1023, RI_E1H_OFFLINE}, { 0x228000, 64, RI_ALL_OFFLINE},
- { 0x228100, 8640, RI_E1H_OFFLINE}, { 0x231800, 128, RI_ALL_OFFLINE},
- { 0x231c00, 128, RI_ALL_OFFLINE}, { 0x232000, 1, RI_ALL_OFFLINE},
- { 0x232400, 64, RI_E1H_OFFLINE}, { 0x238200, 1, RI_ALL_ONLINE},
- { 0x238240, 1, RI_ALL_ONLINE}, { 0x238280, 1, RI_ALL_ONLINE},
- { 0x2382c0, 1, RI_ALL_ONLINE}, { 0x238a00, 1, RI_ALL_ONLINE},
- { 0x238a80, 1, RI_ALL_ONLINE}, { 0x240000, 2, RI_ALL_ONLINE},
- { 0x280000, 65, RI_ALL_ONLINE}, { 0x280110, 1, RI_ALL_ONLINE},
- { 0x280120, 1, RI_ALL_ONLINE}, { 0x280130, 1, RI_ALL_ONLINE},
- { 0x280140, 1, RI_ALL_ONLINE}, { 0x28014c, 2, RI_E1H_ONLINE},
- { 0x280200, 58, RI_ALL_ONLINE}, { 0x280340, 4, RI_ALL_ONLINE},
- { 0x280400, 1, RI_ALL_ONLINE}, { 0x280404, 255, RI_ALL_OFFLINE},
- { 0x282000, 4, RI_ALL_ONLINE}, { 0x282010, 2044, RI_ALL_OFFLINE},
- { 0x2a0000, 1, RI_ALL_ONLINE}, { 0x2a0004, 1023, RI_ALL_OFFLINE},
- { 0x2a1000, 1, RI_ALL_ONLINE}, { 0x2a1004, 4607, RI_ALL_OFFLINE},
- { 0x2a5800, 2560, RI_E1H_OFFLINE}, { 0x2a8000, 64, RI_ALL_OFFLINE},
- { 0x2a8100, 960, RI_E1H_OFFLINE}, { 0x2a9000, 1, RI_E1H_ONLINE},
- { 0x2a9004, 7679, RI_E1H_OFFLINE}, { 0x2b1800, 128, RI_ALL_OFFLINE},
- { 0x2b1c00, 128, RI_ALL_OFFLINE}, { 0x2b2000, 1, RI_ALL_OFFLINE},
- { 0x2b2400, 64, RI_E1H_OFFLINE}, { 0x2b8200, 1, RI_ALL_ONLINE},
- { 0x2b8240, 1, RI_ALL_ONLINE}, { 0x2b8280, 1, RI_ALL_ONLINE},
- { 0x2b82c0, 1, RI_ALL_ONLINE}, { 0x2b8a00, 1, RI_ALL_ONLINE},
- { 0x2b8a80, 1, RI_ALL_ONLINE}, { 0x2c0000, 2, RI_ALL_ONLINE},
- { 0x300000, 65, RI_ALL_ONLINE}, { 0x300110, 1, RI_ALL_ONLINE},
- { 0x300120, 1, RI_ALL_ONLINE}, { 0x300130, 1, RI_ALL_ONLINE},
- { 0x300140, 1, RI_ALL_ONLINE}, { 0x30014c, 2, RI_E1H_ONLINE},
- { 0x300200, 58, RI_ALL_ONLINE}, { 0x300340, 4, RI_ALL_ONLINE},
- { 0x300400, 1, RI_ALL_ONLINE}, { 0x300404, 255, RI_ALL_OFFLINE},
- { 0x302000, 4, RI_ALL_ONLINE}, { 0x302010, 2044, RI_ALL_OFFLINE},
- { 0x320000, 1, RI_ALL_ONLINE}, { 0x320004, 1023, RI_ALL_OFFLINE},
- { 0x321000, 1, RI_ALL_ONLINE}, { 0x321004, 4607, RI_ALL_OFFLINE},
- { 0x325800, 2560, RI_E1H_OFFLINE}, { 0x328000, 64, RI_ALL_OFFLINE},
- { 0x328100, 536, RI_E1H_OFFLINE}, { 0x328960, 1, RI_E1H_ONLINE},
- { 0x328964, 8103, RI_E1H_OFFLINE}, { 0x331800, 128, RI_ALL_OFFLINE},
- { 0x331c00, 128, RI_ALL_OFFLINE}, { 0x332000, 1, RI_ALL_OFFLINE},
- { 0x332400, 64, RI_E1H_OFFLINE}, { 0x338200, 1, RI_ALL_ONLINE},
- { 0x338240, 1, RI_ALL_ONLINE}, { 0x338280, 1, RI_ALL_ONLINE},
- { 0x3382c0, 1, RI_ALL_ONLINE}, { 0x338a00, 1, RI_ALL_ONLINE},
- { 0x338a80, 1, RI_ALL_ONLINE}, { 0x340000, 2, RI_ALL_ONLINE}
+ { 0x2000, 341, RI_ALL_ONLINE }, { 0x2800, 103, RI_ALL_ONLINE },
+ { 0x3000, 287, RI_ALL_ONLINE }, { 0x3800, 331, RI_ALL_ONLINE },
+ { 0x8800, 6, RI_E1_ONLINE }, { 0xa000, 223, RI_ALL_ONLINE },
+ { 0xa388, 1, RI_ALL_ONLINE }, { 0xa398, 1, RI_ALL_ONLINE },
+ { 0xa39c, 7, RI_E1H_ONLINE }, { 0xa3c0, 3, RI_E1H_ONLINE },
+ { 0xa3d0, 1, RI_E1H_ONLINE }, { 0xa3d8, 1, RI_E1H_ONLINE },
+ { 0xa3e0, 1, RI_E1H_ONLINE }, { 0xa3e8, 1, RI_E1H_ONLINE },
+ { 0xa3f0, 1, RI_E1H_ONLINE }, { 0xa3f8, 1, RI_E1H_ONLINE },
+ { 0xa400, 69, RI_ALL_ONLINE }, { 0xa518, 1, RI_ALL_ONLINE },
+ { 0xa520, 1, RI_ALL_ONLINE }, { 0xa528, 1, RI_ALL_ONLINE },
+ { 0xa530, 1, RI_ALL_ONLINE }, { 0xa538, 1, RI_ALL_ONLINE },
+ { 0xa540, 1, RI_ALL_ONLINE }, { 0xa548, 1, RI_ALL_ONLINE },
+ { 0xa550, 1, RI_ALL_ONLINE }, { 0xa558, 1, RI_ALL_ONLINE },
+ { 0xa560, 1, RI_ALL_ONLINE }, { 0xa568, 1, RI_ALL_ONLINE },
+ { 0xa570, 1, RI_ALL_ONLINE }, { 0xa580, 1, RI_ALL_ONLINE },
+ { 0xa590, 1, RI_ALL_ONLINE }, { 0xa5a0, 1, RI_ALL_ONLINE },
+ { 0xa5c0, 1, RI_ALL_ONLINE }, { 0xa5e0, 1, RI_E1H_ONLINE },
+ { 0xa5e8, 1, RI_E1H_ONLINE }, { 0xa5f0, 1, RI_E1H_ONLINE },
+ { 0xa5f8, 10, RI_E1H_ONLINE }, { 0x10000, 236, RI_ALL_ONLINE },
+ { 0x103bc, 1, RI_ALL_ONLINE }, { 0x103cc, 1, RI_ALL_ONLINE },
+ { 0x103dc, 1, RI_ALL_ONLINE }, { 0x10400, 57, RI_ALL_ONLINE },
+ { 0x104e8, 2, RI_ALL_ONLINE }, { 0x104f4, 2, RI_ALL_ONLINE },
+ { 0x10500, 146, RI_ALL_ONLINE }, { 0x10750, 2, RI_ALL_ONLINE },
+ { 0x10760, 2, RI_ALL_ONLINE }, { 0x10770, 2, RI_ALL_ONLINE },
+ { 0x10780, 2, RI_ALL_ONLINE }, { 0x10790, 2, RI_ALL_ONLINE },
+ { 0x107a0, 2, RI_ALL_ONLINE }, { 0x107b0, 2, RI_ALL_ONLINE },
+ { 0x107c0, 2, RI_ALL_ONLINE }, { 0x107d0, 2, RI_ALL_ONLINE },
+ { 0x107e0, 2, RI_ALL_ONLINE }, { 0x10880, 2, RI_ALL_ONLINE },
+ { 0x10900, 2, RI_ALL_ONLINE }, { 0x12000, 1, RI_ALL_ONLINE },
+ { 0x14000, 1, RI_ALL_ONLINE }, { 0x16000, 26, RI_E1H_ONLINE },
+ { 0x16070, 18, RI_E1H_ONLINE }, { 0x160c0, 27, RI_E1H_ONLINE },
+ { 0x16140, 1, RI_E1H_ONLINE }, { 0x16160, 1, RI_E1H_ONLINE },
+ { 0x16180, 2, RI_E1H_ONLINE }, { 0x161c0, 2, RI_E1H_ONLINE },
+ { 0x16204, 5, RI_E1H_ONLINE }, { 0x18000, 1, RI_E1H_ONLINE },
+ { 0x18008, 1, RI_E1H_ONLINE }, { 0x20000, 24, RI_ALL_ONLINE },
+ { 0x20060, 8, RI_ALL_ONLINE }, { 0x20080, 138, RI_ALL_ONLINE },
+ { 0x202b4, 1, RI_ALL_ONLINE }, { 0x202c4, 1, RI_ALL_ONLINE },
+ { 0x20400, 2, RI_ALL_ONLINE }, { 0x2040c, 8, RI_ALL_ONLINE },
+ { 0x2042c, 18, RI_E1H_ONLINE }, { 0x20480, 1, RI_ALL_ONLINE },
+ { 0x20500, 1, RI_ALL_ONLINE }, { 0x20600, 1, RI_ALL_ONLINE },
+ { 0x28000, 1, RI_ALL_ONLINE }, { 0x28004, 8191, RI_ALL_OFFLINE },
+ { 0x30000, 1, RI_ALL_ONLINE }, { 0x30004, 16383, RI_ALL_OFFLINE },
+ { 0x40000, 98, RI_ALL_ONLINE }, { 0x40194, 1, RI_ALL_ONLINE },
+ { 0x401a4, 1, RI_ALL_ONLINE }, { 0x401a8, 11, RI_E1H_ONLINE },
+ { 0x40200, 4, RI_ALL_ONLINE }, { 0x40400, 43, RI_ALL_ONLINE },
+ { 0x404b8, 1, RI_ALL_ONLINE }, { 0x404c8, 1, RI_ALL_ONLINE },
+ { 0x404cc, 3, RI_E1H_ONLINE }, { 0x40500, 2, RI_ALL_ONLINE },
+ { 0x40510, 2, RI_ALL_ONLINE }, { 0x40520, 2, RI_ALL_ONLINE },
+ { 0x40530, 2, RI_ALL_ONLINE }, { 0x40540, 2, RI_ALL_ONLINE },
+ { 0x42000, 164, RI_ALL_ONLINE }, { 0x4229c, 1, RI_ALL_ONLINE },
+ { 0x422ac, 1, RI_ALL_ONLINE }, { 0x422bc, 1, RI_ALL_ONLINE },
+ { 0x422d4, 5, RI_E1H_ONLINE }, { 0x42400, 49, RI_ALL_ONLINE },
+ { 0x424c8, 38, RI_ALL_ONLINE }, { 0x42568, 2, RI_ALL_ONLINE },
+ { 0x42800, 1, RI_ALL_ONLINE }, { 0x50000, 20, RI_ALL_ONLINE },
+ { 0x50050, 8, RI_ALL_ONLINE }, { 0x50070, 88, RI_ALL_ONLINE },
+ { 0x501dc, 1, RI_ALL_ONLINE }, { 0x501ec, 1, RI_ALL_ONLINE },
+ { 0x501f0, 4, RI_E1H_ONLINE }, { 0x50200, 2, RI_ALL_ONLINE },
+ { 0x5020c, 7, RI_ALL_ONLINE }, { 0x50228, 6, RI_E1H_ONLINE },
+ { 0x50240, 1, RI_ALL_ONLINE }, { 0x50280, 1, RI_ALL_ONLINE },
+ { 0x52000, 1, RI_ALL_ONLINE }, { 0x54000, 1, RI_ALL_ONLINE },
+ { 0x54004, 3327, RI_ALL_OFFLINE }, { 0x58000, 1, RI_ALL_ONLINE },
+ { 0x58004, 8191, RI_ALL_OFFLINE }, { 0x60000, 71, RI_ALL_ONLINE },
+ { 0x60128, 1, RI_ALL_ONLINE }, { 0x60138, 1, RI_ALL_ONLINE },
+ { 0x6013c, 24, RI_E1H_ONLINE }, { 0x60200, 1, RI_ALL_ONLINE },
+ { 0x61000, 1, RI_ALL_ONLINE }, { 0x61004, 511, RI_ALL_OFFLINE },
+ { 0x70000, 8, RI_ALL_ONLINE }, { 0x70020, 21496, RI_ALL_OFFLINE },
+ { 0x85000, 3, RI_ALL_ONLINE }, { 0x8500c, 4, RI_ALL_OFFLINE },
+ { 0x8501c, 7, RI_ALL_ONLINE }, { 0x85038, 4, RI_ALL_OFFLINE },
+ { 0x85048, 1, RI_ALL_ONLINE }, { 0x8504c, 109, RI_ALL_OFFLINE },
+ { 0x85200, 32, RI_ALL_ONLINE }, { 0x85280, 11104, RI_ALL_OFFLINE },
+ { 0xa0000, 16384, RI_ALL_ONLINE }, { 0xb0000, 16384, RI_E1H_ONLINE },
+ { 0xc1000, 7, RI_ALL_ONLINE }, { 0xc1028, 1, RI_ALL_ONLINE },
+ { 0xc1038, 1, RI_ALL_ONLINE }, { 0xc1800, 2, RI_ALL_ONLINE },
+ { 0xc2000, 164, RI_ALL_ONLINE }, { 0xc229c, 1, RI_ALL_ONLINE },
+ { 0xc22ac, 1, RI_ALL_ONLINE }, { 0xc22bc, 1, RI_ALL_ONLINE },
+ { 0xc2400, 49, RI_ALL_ONLINE }, { 0xc24c8, 38, RI_ALL_ONLINE },
+ { 0xc2568, 2, RI_ALL_ONLINE }, { 0xc2600, 1, RI_ALL_ONLINE },
+ { 0xc4000, 165, RI_ALL_ONLINE }, { 0xc42a0, 1, RI_ALL_ONLINE },
+ { 0xc42b0, 1, RI_ALL_ONLINE }, { 0xc42c0, 1, RI_ALL_ONLINE },
+ { 0xc42e0, 7, RI_E1H_ONLINE }, { 0xc4400, 51, RI_ALL_ONLINE },
+ { 0xc44d0, 38, RI_ALL_ONLINE }, { 0xc4570, 2, RI_ALL_ONLINE },
+ { 0xc4600, 1, RI_ALL_ONLINE }, { 0xd0000, 19, RI_ALL_ONLINE },
+ { 0xd004c, 8, RI_ALL_ONLINE }, { 0xd006c, 91, RI_ALL_ONLINE },
+ { 0xd01e4, 1, RI_ALL_ONLINE }, { 0xd01f4, 1, RI_ALL_ONLINE },
+ { 0xd0200, 2, RI_ALL_ONLINE }, { 0xd020c, 7, RI_ALL_ONLINE },
+ { 0xd0228, 18, RI_E1H_ONLINE }, { 0xd0280, 1, RI_ALL_ONLINE },
+ { 0xd0300, 1, RI_ALL_ONLINE }, { 0xd0400, 1, RI_ALL_ONLINE },
+ { 0xd4000, 1, RI_ALL_ONLINE }, { 0xd4004, 2559, RI_ALL_OFFLINE },
+ { 0xd8000, 1, RI_ALL_ONLINE }, { 0xd8004, 8191, RI_ALL_OFFLINE },
+ { 0xe0000, 21, RI_ALL_ONLINE }, { 0xe0054, 8, RI_ALL_ONLINE },
+ { 0xe0074, 85, RI_ALL_ONLINE }, { 0xe01d4, 1, RI_ALL_ONLINE },
+ { 0xe01e4, 1, RI_ALL_ONLINE }, { 0xe0200, 2, RI_ALL_ONLINE },
+ { 0xe020c, 8, RI_ALL_ONLINE }, { 0xe022c, 18, RI_E1H_ONLINE },
+ { 0xe0280, 1, RI_ALL_ONLINE }, { 0xe0300, 1, RI_ALL_ONLINE },
+ { 0xe1000, 1, RI_ALL_ONLINE }, { 0xe2000, 1, RI_ALL_ONLINE },
+ { 0xe2004, 2047, RI_ALL_OFFLINE }, { 0xf0000, 1, RI_ALL_ONLINE },
+ { 0xf0004, 16383, RI_ALL_OFFLINE }, { 0x101000, 12, RI_ALL_ONLINE },
+ { 0x10103c, 1, RI_ALL_ONLINE }, { 0x10104c, 1, RI_ALL_ONLINE },
+ { 0x101050, 1, RI_E1H_ONLINE }, { 0x101100, 1, RI_ALL_ONLINE },
+ { 0x101800, 8, RI_ALL_ONLINE }, { 0x102000, 18, RI_ALL_ONLINE },
+ { 0x102054, 1, RI_ALL_ONLINE }, { 0x102064, 1, RI_ALL_ONLINE },
+ { 0x102080, 17, RI_ALL_ONLINE }, { 0x1020c8, 8, RI_E1H_ONLINE },
+ { 0x102400, 1, RI_ALL_ONLINE }, { 0x103000, 26, RI_ALL_ONLINE },
+ { 0x103074, 1, RI_ALL_ONLINE }, { 0x103084, 1, RI_ALL_ONLINE },
+ { 0x103094, 1, RI_ALL_ONLINE }, { 0x103098, 5, RI_E1H_ONLINE },
+ { 0x103800, 8, RI_ALL_ONLINE }, { 0x104000, 63, RI_ALL_ONLINE },
+ { 0x104108, 1, RI_ALL_ONLINE }, { 0x104118, 1, RI_ALL_ONLINE },
+ { 0x104200, 17, RI_ALL_ONLINE }, { 0x104400, 64, RI_ALL_ONLINE },
+ { 0x104500, 192, RI_ALL_OFFLINE }, { 0x104800, 64, RI_ALL_ONLINE },
+ { 0x104900, 192, RI_ALL_OFFLINE }, { 0x105000, 7, RI_ALL_ONLINE },
+ { 0x10501c, 1, RI_ALL_OFFLINE }, { 0x105020, 3, RI_ALL_ONLINE },
+ { 0x10502c, 1, RI_ALL_OFFLINE }, { 0x105030, 3, RI_ALL_ONLINE },
+ { 0x10503c, 1, RI_ALL_OFFLINE }, { 0x105040, 3, RI_ALL_ONLINE },
+ { 0x10504c, 1, RI_ALL_OFFLINE }, { 0x105050, 3, RI_ALL_ONLINE },
+ { 0x10505c, 1, RI_ALL_OFFLINE }, { 0x105060, 3, RI_ALL_ONLINE },
+ { 0x10506c, 1, RI_ALL_OFFLINE }, { 0x105070, 3, RI_ALL_ONLINE },
+ { 0x10507c, 1, RI_ALL_OFFLINE }, { 0x105080, 3, RI_ALL_ONLINE },
+ { 0x10508c, 1, RI_ALL_OFFLINE }, { 0x105090, 3, RI_ALL_ONLINE },
+ { 0x10509c, 1, RI_ALL_OFFLINE }, { 0x1050a0, 3, RI_ALL_ONLINE },
+ { 0x1050ac, 1, RI_ALL_OFFLINE }, { 0x1050b0, 3, RI_ALL_ONLINE },
+ { 0x1050bc, 1, RI_ALL_OFFLINE }, { 0x1050c0, 3, RI_ALL_ONLINE },
+ { 0x1050cc, 1, RI_ALL_OFFLINE }, { 0x1050d0, 3, RI_ALL_ONLINE },
+ { 0x1050dc, 1, RI_ALL_OFFLINE }, { 0x1050e0, 3, RI_ALL_ONLINE },
+ { 0x1050ec, 1, RI_ALL_OFFLINE }, { 0x1050f0, 3, RI_ALL_ONLINE },
+ { 0x1050fc, 1, RI_ALL_OFFLINE }, { 0x105100, 3, RI_ALL_ONLINE },
+ { 0x10510c, 1, RI_ALL_OFFLINE }, { 0x105110, 3, RI_ALL_ONLINE },
+ { 0x10511c, 1, RI_ALL_OFFLINE }, { 0x105120, 3, RI_ALL_ONLINE },
+ { 0x10512c, 1, RI_ALL_OFFLINE }, { 0x105130, 3, RI_ALL_ONLINE },
+ { 0x10513c, 1, RI_ALL_OFFLINE }, { 0x105140, 3, RI_ALL_ONLINE },
+ { 0x10514c, 1, RI_ALL_OFFLINE }, { 0x105150, 3, RI_ALL_ONLINE },
+ { 0x10515c, 1, RI_ALL_OFFLINE }, { 0x105160, 3, RI_ALL_ONLINE },
+ { 0x10516c, 1, RI_ALL_OFFLINE }, { 0x105170, 3, RI_ALL_ONLINE },
+ { 0x10517c, 1, RI_ALL_OFFLINE }, { 0x105180, 3, RI_ALL_ONLINE },
+ { 0x10518c, 1, RI_ALL_OFFLINE }, { 0x105190, 3, RI_ALL_ONLINE },
+ { 0x10519c, 1, RI_ALL_OFFLINE }, { 0x1051a0, 3, RI_ALL_ONLINE },
+ { 0x1051ac, 1, RI_ALL_OFFLINE }, { 0x1051b0, 3, RI_ALL_ONLINE },
+ { 0x1051bc, 1, RI_ALL_OFFLINE }, { 0x1051c0, 3, RI_ALL_ONLINE },
+ { 0x1051cc, 1, RI_ALL_OFFLINE }, { 0x1051d0, 3, RI_ALL_ONLINE },
+ { 0x1051dc, 1, RI_ALL_OFFLINE }, { 0x1051e0, 3, RI_ALL_ONLINE },
+ { 0x1051ec, 1, RI_ALL_OFFLINE }, { 0x1051f0, 3, RI_ALL_ONLINE },
+ { 0x1051fc, 1, RI_ALL_OFFLINE }, { 0x105200, 3, RI_ALL_ONLINE },
+ { 0x10520c, 1, RI_ALL_OFFLINE }, { 0x105210, 3, RI_ALL_ONLINE },
+ { 0x10521c, 1, RI_ALL_OFFLINE }, { 0x105220, 3, RI_ALL_ONLINE },
+ { 0x10522c, 1, RI_ALL_OFFLINE }, { 0x105230, 3, RI_ALL_ONLINE },
+ { 0x10523c, 1, RI_ALL_OFFLINE }, { 0x105240, 3, RI_ALL_ONLINE },
+ { 0x10524c, 1, RI_ALL_OFFLINE }, { 0x105250, 3, RI_ALL_ONLINE },
+ { 0x10525c, 1, RI_ALL_OFFLINE }, { 0x105260, 3, RI_ALL_ONLINE },
+ { 0x10526c, 1, RI_ALL_OFFLINE }, { 0x105270, 3, RI_ALL_ONLINE },
+ { 0x10527c, 1, RI_ALL_OFFLINE }, { 0x105280, 3, RI_ALL_ONLINE },
+ { 0x10528c, 1, RI_ALL_OFFLINE }, { 0x105290, 3, RI_ALL_ONLINE },
+ { 0x10529c, 1, RI_ALL_OFFLINE }, { 0x1052a0, 3, RI_ALL_ONLINE },
+ { 0x1052ac, 1, RI_ALL_OFFLINE }, { 0x1052b0, 3, RI_ALL_ONLINE },
+ { 0x1052bc, 1, RI_ALL_OFFLINE }, { 0x1052c0, 3, RI_ALL_ONLINE },
+ { 0x1052cc, 1, RI_ALL_OFFLINE }, { 0x1052d0, 3, RI_ALL_ONLINE },
+ { 0x1052dc, 1, RI_ALL_OFFLINE }, { 0x1052e0, 3, RI_ALL_ONLINE },
+ { 0x1052ec, 1, RI_ALL_OFFLINE }, { 0x1052f0, 3, RI_ALL_ONLINE },
+ { 0x1052fc, 1, RI_ALL_OFFLINE }, { 0x105300, 3, RI_ALL_ONLINE },
+ { 0x10530c, 1, RI_ALL_OFFLINE }, { 0x105310, 3, RI_ALL_ONLINE },
+ { 0x10531c, 1, RI_ALL_OFFLINE }, { 0x105320, 3, RI_ALL_ONLINE },
+ { 0x10532c, 1, RI_ALL_OFFLINE }, { 0x105330, 3, RI_ALL_ONLINE },
+ { 0x10533c, 1, RI_ALL_OFFLINE }, { 0x105340, 3, RI_ALL_ONLINE },
+ { 0x10534c, 1, RI_ALL_OFFLINE }, { 0x105350, 3, RI_ALL_ONLINE },
+ { 0x10535c, 1, RI_ALL_OFFLINE }, { 0x105360, 3, RI_ALL_ONLINE },
+ { 0x10536c, 1, RI_ALL_OFFLINE }, { 0x105370, 3, RI_ALL_ONLINE },
+ { 0x10537c, 1, RI_ALL_OFFLINE }, { 0x105380, 3, RI_ALL_ONLINE },
+ { 0x10538c, 1, RI_ALL_OFFLINE }, { 0x105390, 3, RI_ALL_ONLINE },
+ { 0x10539c, 1, RI_ALL_OFFLINE }, { 0x1053a0, 3, RI_ALL_ONLINE },
+ { 0x1053ac, 1, RI_ALL_OFFLINE }, { 0x1053b0, 3, RI_ALL_ONLINE },
+ { 0x1053bc, 1, RI_ALL_OFFLINE }, { 0x1053c0, 3, RI_ALL_ONLINE },
+ { 0x1053cc, 1, RI_ALL_OFFLINE }, { 0x1053d0, 3, RI_ALL_ONLINE },
+ { 0x1053dc, 1, RI_ALL_OFFLINE }, { 0x1053e0, 3, RI_ALL_ONLINE },
+ { 0x1053ec, 1, RI_ALL_OFFLINE }, { 0x1053f0, 3, RI_ALL_ONLINE },
+ { 0x1053fc, 769, RI_ALL_OFFLINE }, { 0x108000, 33, RI_ALL_ONLINE },
+ { 0x108090, 1, RI_ALL_ONLINE }, { 0x1080a0, 1, RI_ALL_ONLINE },
+ { 0x1080ac, 5, RI_E1H_ONLINE }, { 0x108100, 5, RI_ALL_ONLINE },
+ { 0x108120, 5, RI_ALL_ONLINE }, { 0x108200, 74, RI_ALL_ONLINE },
+ { 0x108400, 74, RI_ALL_ONLINE }, { 0x108800, 152, RI_ALL_ONLINE },
+ { 0x109000, 1, RI_ALL_ONLINE }, { 0x120000, 347, RI_ALL_ONLINE },
+ { 0x120578, 1, RI_ALL_ONLINE }, { 0x120588, 1, RI_ALL_ONLINE },
+ { 0x120598, 1, RI_ALL_ONLINE }, { 0x12059c, 23, RI_E1H_ONLINE },
+ { 0x120614, 1, RI_E1H_ONLINE }, { 0x12061c, 30, RI_E1H_ONLINE },
+ { 0x12080c, 65, RI_ALL_ONLINE }, { 0x120a00, 2, RI_ALL_ONLINE },
+ { 0x122000, 2, RI_ALL_ONLINE }, { 0x128000, 2, RI_E1H_ONLINE },
+ { 0x140000, 114, RI_ALL_ONLINE }, { 0x1401d4, 1, RI_ALL_ONLINE },
+ { 0x1401e4, 1, RI_ALL_ONLINE }, { 0x140200, 6, RI_ALL_ONLINE },
+ { 0x144000, 4, RI_ALL_ONLINE }, { 0x148000, 4, RI_ALL_ONLINE },
+ { 0x14c000, 4, RI_ALL_ONLINE }, { 0x150000, 4, RI_ALL_ONLINE },
+ { 0x154000, 4, RI_ALL_ONLINE }, { 0x158000, 4, RI_ALL_ONLINE },
+ { 0x15c000, 7, RI_E1H_ONLINE }, { 0x161000, 7, RI_ALL_ONLINE },
+ { 0x161028, 1, RI_ALL_ONLINE }, { 0x161038, 1, RI_ALL_ONLINE },
+ { 0x161800, 2, RI_ALL_ONLINE }, { 0x164000, 60, RI_ALL_ONLINE },
+ { 0x1640fc, 1, RI_ALL_ONLINE }, { 0x16410c, 1, RI_ALL_ONLINE },
+ { 0x164110, 2, RI_E1H_ONLINE }, { 0x164200, 1, RI_ALL_ONLINE },
+ { 0x164208, 1, RI_ALL_ONLINE }, { 0x164210, 1, RI_ALL_ONLINE },
+ { 0x164218, 1, RI_ALL_ONLINE }, { 0x164220, 1, RI_ALL_ONLINE },
+ { 0x164228, 1, RI_ALL_ONLINE }, { 0x164230, 1, RI_ALL_ONLINE },
+ { 0x164238, 1, RI_ALL_ONLINE }, { 0x164240, 1, RI_ALL_ONLINE },
+ { 0x164248, 1, RI_ALL_ONLINE }, { 0x164250, 1, RI_ALL_ONLINE },
+ { 0x164258, 1, RI_ALL_ONLINE }, { 0x164260, 1, RI_ALL_ONLINE },
+ { 0x164270, 2, RI_ALL_ONLINE }, { 0x164280, 2, RI_ALL_ONLINE },
+ { 0x164800, 2, RI_ALL_ONLINE }, { 0x165000, 2, RI_ALL_ONLINE },
+ { 0x166000, 164, RI_ALL_ONLINE }, { 0x16629c, 1, RI_ALL_ONLINE },
+ { 0x1662ac, 1, RI_ALL_ONLINE }, { 0x1662bc, 1, RI_ALL_ONLINE },
+ { 0x166400, 49, RI_ALL_ONLINE }, { 0x1664c8, 38, RI_ALL_ONLINE },
+ { 0x166568, 2, RI_ALL_ONLINE }, { 0x166800, 1, RI_ALL_ONLINE },
+ { 0x168000, 270, RI_ALL_ONLINE }, { 0x168444, 1, RI_ALL_ONLINE },
+ { 0x168454, 1, RI_ALL_ONLINE }, { 0x168800, 19, RI_ALL_ONLINE },
+ { 0x168900, 1, RI_ALL_ONLINE }, { 0x168a00, 128, RI_ALL_ONLINE },
+ { 0x16a000, 1, RI_ALL_ONLINE }, { 0x16a004, 1535, RI_ALL_OFFLINE },
+ { 0x16c000, 1, RI_ALL_ONLINE }, { 0x16c004, 1535, RI_ALL_OFFLINE },
+ { 0x16e000, 16, RI_E1H_ONLINE }, { 0x16e100, 1, RI_E1H_ONLINE },
+ { 0x16e200, 2, RI_E1H_ONLINE }, { 0x16e400, 183, RI_E1H_ONLINE },
+ { 0x170000, 93, RI_ALL_ONLINE }, { 0x170180, 1, RI_ALL_ONLINE },
+ { 0x170190, 1, RI_ALL_ONLINE }, { 0x170200, 4, RI_ALL_ONLINE },
+ { 0x170214, 1, RI_ALL_ONLINE }, { 0x178000, 1, RI_ALL_ONLINE },
+ { 0x180000, 61, RI_ALL_ONLINE }, { 0x180100, 1, RI_ALL_ONLINE },
+ { 0x180110, 1, RI_ALL_ONLINE }, { 0x180120, 1, RI_ALL_ONLINE },
+ { 0x180130, 1, RI_ALL_ONLINE }, { 0x18013c, 2, RI_E1H_ONLINE },
+ { 0x180200, 58, RI_ALL_ONLINE }, { 0x180340, 4, RI_ALL_ONLINE },
+ { 0x180400, 1, RI_ALL_ONLINE }, { 0x180404, 255, RI_ALL_OFFLINE },
+ { 0x181000, 4, RI_ALL_ONLINE }, { 0x181010, 1020, RI_ALL_OFFLINE },
+ { 0x1a0000, 1, RI_ALL_ONLINE }, { 0x1a0004, 1023, RI_ALL_OFFLINE },
+ { 0x1a1000, 1, RI_ALL_ONLINE }, { 0x1a1004, 4607, RI_ALL_OFFLINE },
+ { 0x1a5800, 2560, RI_E1H_OFFLINE }, { 0x1a8000, 64, RI_ALL_OFFLINE },
+ { 0x1a8100, 1984, RI_E1H_OFFLINE }, { 0x1aa000, 1, RI_E1H_ONLINE },
+ { 0x1aa004, 6655, RI_E1H_OFFLINE }, { 0x1b1800, 128, RI_ALL_OFFLINE },
+ { 0x1b1c00, 128, RI_ALL_OFFLINE }, { 0x1b2000, 1, RI_ALL_OFFLINE },
+ { 0x1b2400, 64, RI_E1H_OFFLINE }, { 0x1b8200, 1, RI_ALL_ONLINE },
+ { 0x1b8240, 1, RI_ALL_ONLINE }, { 0x1b8280, 1, RI_ALL_ONLINE },
+ { 0x1b82c0, 1, RI_ALL_ONLINE }, { 0x1b8a00, 1, RI_ALL_ONLINE },
+ { 0x1b8a80, 1, RI_ALL_ONLINE }, { 0x1c0000, 2, RI_ALL_ONLINE },
+ { 0x200000, 65, RI_ALL_ONLINE }, { 0x200110, 1, RI_ALL_ONLINE },
+ { 0x200120, 1, RI_ALL_ONLINE }, { 0x200130, 1, RI_ALL_ONLINE },
+ { 0x200140, 1, RI_ALL_ONLINE }, { 0x20014c, 2, RI_E1H_ONLINE },
+ { 0x200200, 58, RI_ALL_ONLINE }, { 0x200340, 4, RI_ALL_ONLINE },
+ { 0x200400, 1, RI_ALL_ONLINE }, { 0x200404, 255, RI_ALL_OFFLINE },
+ { 0x202000, 4, RI_ALL_ONLINE }, { 0x202010, 2044, RI_ALL_OFFLINE },
+ { 0x220000, 1, RI_ALL_ONLINE }, { 0x220004, 1023, RI_ALL_OFFLINE },
+ { 0x221000, 1, RI_ALL_ONLINE }, { 0x221004, 4607, RI_ALL_OFFLINE },
+ { 0x225800, 1536, RI_E1H_OFFLINE }, { 0x227000, 1, RI_E1H_ONLINE },
+ { 0x227004, 1023, RI_E1H_OFFLINE }, { 0x228000, 64, RI_ALL_OFFLINE },
+ { 0x228100, 8640, RI_E1H_OFFLINE }, { 0x231800, 128, RI_ALL_OFFLINE },
+ { 0x231c00, 128, RI_ALL_OFFLINE }, { 0x232000, 1, RI_ALL_OFFLINE },
+ { 0x232400, 64, RI_E1H_OFFLINE }, { 0x238200, 1, RI_ALL_ONLINE },
+ { 0x238240, 1, RI_ALL_ONLINE }, { 0x238280, 1, RI_ALL_ONLINE },
+ { 0x2382c0, 1, RI_ALL_ONLINE }, { 0x238a00, 1, RI_ALL_ONLINE },
+ { 0x238a80, 1, RI_ALL_ONLINE }, { 0x240000, 2, RI_ALL_ONLINE },
+ { 0x280000, 65, RI_ALL_ONLINE }, { 0x280110, 1, RI_ALL_ONLINE },
+ { 0x280120, 1, RI_ALL_ONLINE }, { 0x280130, 1, RI_ALL_ONLINE },
+ { 0x280140, 1, RI_ALL_ONLINE }, { 0x28014c, 2, RI_E1H_ONLINE },
+ { 0x280200, 58, RI_ALL_ONLINE }, { 0x280340, 4, RI_ALL_ONLINE },
+ { 0x280400, 1, RI_ALL_ONLINE }, { 0x280404, 255, RI_ALL_OFFLINE },
+ { 0x282000, 4, RI_ALL_ONLINE }, { 0x282010, 2044, RI_ALL_OFFLINE },
+ { 0x2a0000, 1, RI_ALL_ONLINE }, { 0x2a0004, 1023, RI_ALL_OFFLINE },
+ { 0x2a1000, 1, RI_ALL_ONLINE }, { 0x2a1004, 4607, RI_ALL_OFFLINE },
+ { 0x2a5800, 2560, RI_E1H_OFFLINE }, { 0x2a8000, 64, RI_ALL_OFFLINE },
+ { 0x2a8100, 960, RI_E1H_OFFLINE }, { 0x2a9000, 1, RI_E1H_ONLINE },
+ { 0x2a9004, 7679, RI_E1H_OFFLINE }, { 0x2b1800, 128, RI_ALL_OFFLINE },
+ { 0x2b1c00, 128, RI_ALL_OFFLINE }, { 0x2b2000, 1, RI_ALL_OFFLINE },
+ { 0x2b2400, 64, RI_E1H_OFFLINE }, { 0x2b8200, 1, RI_ALL_ONLINE },
+ { 0x2b8240, 1, RI_ALL_ONLINE }, { 0x2b8280, 1, RI_ALL_ONLINE },
+ { 0x2b82c0, 1, RI_ALL_ONLINE }, { 0x2b8a00, 1, RI_ALL_ONLINE },
+ { 0x2b8a80, 1, RI_ALL_ONLINE }, { 0x2c0000, 2, RI_ALL_ONLINE },
+ { 0x300000, 65, RI_ALL_ONLINE }, { 0x300110, 1, RI_ALL_ONLINE },
+ { 0x300120, 1, RI_ALL_ONLINE }, { 0x300130, 1, RI_ALL_ONLINE },
+ { 0x300140, 1, RI_ALL_ONLINE }, { 0x30014c, 2, RI_E1H_ONLINE },
+ { 0x300200, 58, RI_ALL_ONLINE }, { 0x300340, 4, RI_ALL_ONLINE },
+ { 0x300400, 1, RI_ALL_ONLINE }, { 0x300404, 255, RI_ALL_OFFLINE },
+ { 0x302000, 4, RI_ALL_ONLINE }, { 0x302010, 2044, RI_ALL_OFFLINE },
+ { 0x320000, 1, RI_ALL_ONLINE }, { 0x320004, 1023, RI_ALL_OFFLINE },
+ { 0x321000, 1, RI_ALL_ONLINE }, { 0x321004, 4607, RI_ALL_OFFLINE },
+ { 0x325800, 2560, RI_E1H_OFFLINE }, { 0x328000, 64, RI_ALL_OFFLINE },
+ { 0x328100, 536, RI_E1H_OFFLINE }, { 0x328960, 1, RI_E1H_ONLINE },
+ { 0x328964, 8103, RI_E1H_OFFLINE }, { 0x331800, 128, RI_ALL_OFFLINE },
+ { 0x331c00, 128, RI_ALL_OFFLINE }, { 0x332000, 1, RI_ALL_OFFLINE },
+ { 0x332400, 64, RI_E1H_OFFLINE }, { 0x338200, 1, RI_ALL_ONLINE },
+ { 0x338240, 1, RI_ALL_ONLINE }, { 0x338280, 1, RI_ALL_ONLINE },
+ { 0x3382c0, 1, RI_ALL_ONLINE }, { 0x338a00, 1, RI_ALL_ONLINE },
+ { 0x338a80, 1, RI_ALL_ONLINE }, { 0x340000, 2, RI_ALL_ONLINE }
};
-#define IDLEREGS_COUNT 277
-static const struct reg_addr idle_addrs[IDLEREGS_COUNT] = {
- { 0x2114, 1, RI_ALL_ONLINE}, { 0x2120, 1, RI_ALL_ONLINE},
- { 0x212c, 4, RI_ALL_ONLINE}, { 0x2814, 1, RI_ALL_ONLINE},
- { 0x281c, 2, RI_ALL_ONLINE}, { 0xa38c, 1, RI_ALL_ONLINE},
- { 0xa408, 1, RI_ALL_ONLINE}, { 0xa42c, 12, RI_ALL_ONLINE},
- { 0xa600, 5, RI_E1H_ONLINE}, { 0xa618, 1, RI_E1H_ONLINE},
- { 0xc09c, 1, RI_ALL_ONLINE}, { 0x103b0, 1, RI_ALL_ONLINE},
- { 0x103c0, 1, RI_ALL_ONLINE}, { 0x103d0, 1, RI_E1H_ONLINE},
- { 0x2021c, 11, RI_ALL_ONLINE}, { 0x202a8, 1, RI_ALL_ONLINE},
- { 0x202b8, 1, RI_ALL_ONLINE}, { 0x20404, 1, RI_ALL_ONLINE},
- { 0x2040c, 2, RI_ALL_ONLINE}, { 0x2041c, 2, RI_ALL_ONLINE},
- { 0x40154, 14, RI_ALL_ONLINE}, { 0x40198, 1, RI_ALL_ONLINE},
- { 0x404ac, 1, RI_ALL_ONLINE}, { 0x404bc, 1, RI_ALL_ONLINE},
- { 0x42290, 1, RI_ALL_ONLINE}, { 0x422a0, 1, RI_ALL_ONLINE},
- { 0x422b0, 1, RI_ALL_ONLINE}, { 0x42548, 1, RI_ALL_ONLINE},
- { 0x42550, 1, RI_ALL_ONLINE}, { 0x42558, 1, RI_ALL_ONLINE},
- { 0x50160, 8, RI_ALL_ONLINE}, { 0x501d0, 1, RI_ALL_ONLINE},
- { 0x501e0, 1, RI_ALL_ONLINE}, { 0x50204, 1, RI_ALL_ONLINE},
- { 0x5020c, 2, RI_ALL_ONLINE}, { 0x5021c, 1, RI_ALL_ONLINE},
- { 0x60090, 1, RI_ALL_ONLINE}, { 0x6011c, 1, RI_ALL_ONLINE},
- { 0x6012c, 1, RI_ALL_ONLINE}, { 0xc101c, 1, RI_ALL_ONLINE},
- { 0xc102c, 1, RI_ALL_ONLINE}, { 0xc2290, 1, RI_ALL_ONLINE},
- { 0xc22a0, 1, RI_ALL_ONLINE}, { 0xc22b0, 1, RI_ALL_ONLINE},
- { 0xc2548, 1, RI_ALL_ONLINE}, { 0xc2550, 1, RI_ALL_ONLINE},
- { 0xc2558, 1, RI_ALL_ONLINE}, { 0xc4294, 1, RI_ALL_ONLINE},
- { 0xc42a4, 1, RI_ALL_ONLINE}, { 0xc42b4, 1, RI_ALL_ONLINE},
- { 0xc4550, 1, RI_ALL_ONLINE}, { 0xc4558, 1, RI_ALL_ONLINE},
- { 0xc4560, 1, RI_ALL_ONLINE}, { 0xd016c, 8, RI_ALL_ONLINE},
- { 0xd01d8, 1, RI_ALL_ONLINE}, { 0xd01e8, 1, RI_ALL_ONLINE},
- { 0xd0204, 1, RI_ALL_ONLINE}, { 0xd020c, 3, RI_ALL_ONLINE},
- { 0xe0154, 8, RI_ALL_ONLINE}, { 0xe01c8, 1, RI_ALL_ONLINE},
- { 0xe01d8, 1, RI_ALL_ONLINE}, { 0xe0204, 1, RI_ALL_ONLINE},
- { 0xe020c, 2, RI_ALL_ONLINE}, { 0xe021c, 2, RI_ALL_ONLINE},
- { 0x101014, 1, RI_ALL_ONLINE}, { 0x101030, 1, RI_ALL_ONLINE},
- { 0x101040, 1, RI_ALL_ONLINE}, { 0x102058, 1, RI_ALL_ONLINE},
- { 0x102080, 16, RI_ALL_ONLINE}, { 0x103004, 2, RI_ALL_ONLINE},
- { 0x103068, 1, RI_ALL_ONLINE}, { 0x103078, 1, RI_ALL_ONLINE},
- { 0x103088, 1, RI_ALL_ONLINE}, { 0x10309c, 2, RI_E1H_ONLINE},
- { 0x104004, 1, RI_ALL_ONLINE}, { 0x104018, 1, RI_ALL_ONLINE},
- { 0x104020, 1, RI_ALL_ONLINE}, { 0x10403c, 1, RI_ALL_ONLINE},
- { 0x1040fc, 1, RI_ALL_ONLINE}, { 0x10410c, 1, RI_ALL_ONLINE},
- { 0x104400, 64, RI_ALL_ONLINE}, { 0x104800, 64, RI_ALL_ONLINE},
- { 0x105000, 3, RI_ALL_ONLINE}, { 0x105010, 3, RI_ALL_ONLINE},
- { 0x105020, 3, RI_ALL_ONLINE}, { 0x105030, 3, RI_ALL_ONLINE},
- { 0x105040, 3, RI_ALL_ONLINE}, { 0x105050, 3, RI_ALL_ONLINE},
- { 0x105060, 3, RI_ALL_ONLINE}, { 0x105070, 3, RI_ALL_ONLINE},
- { 0x105080, 3, RI_ALL_ONLINE}, { 0x105090, 3, RI_ALL_ONLINE},
- { 0x1050a0, 3, RI_ALL_ONLINE}, { 0x1050b0, 3, RI_ALL_ONLINE},
- { 0x1050c0, 3, RI_ALL_ONLINE}, { 0x1050d0, 3, RI_ALL_ONLINE},
- { 0x1050e0, 3, RI_ALL_ONLINE}, { 0x1050f0, 3, RI_ALL_ONLINE},
- { 0x105100, 3, RI_ALL_ONLINE}, { 0x105110, 3, RI_ALL_ONLINE},
- { 0x105120, 3, RI_ALL_ONLINE}, { 0x105130, 3, RI_ALL_ONLINE},
- { 0x105140, 3, RI_ALL_ONLINE}, { 0x105150, 3, RI_ALL_ONLINE},
- { 0x105160, 3, RI_ALL_ONLINE}, { 0x105170, 3, RI_ALL_ONLINE},
- { 0x105180, 3, RI_ALL_ONLINE}, { 0x105190, 3, RI_ALL_ONLINE},
- { 0x1051a0, 3, RI_ALL_ONLINE}, { 0x1051b0, 3, RI_ALL_ONLINE},
- { 0x1051c0, 3, RI_ALL_ONLINE}, { 0x1051d0, 3, RI_ALL_ONLINE},
- { 0x1051e0, 3, RI_ALL_ONLINE}, { 0x1051f0, 3, RI_ALL_ONLINE},
- { 0x105200, 3, RI_ALL_ONLINE}, { 0x105210, 3, RI_ALL_ONLINE},
- { 0x105220, 3, RI_ALL_ONLINE}, { 0x105230, 3, RI_ALL_ONLINE},
- { 0x105240, 3, RI_ALL_ONLINE}, { 0x105250, 3, RI_ALL_ONLINE},
- { 0x105260, 3, RI_ALL_ONLINE}, { 0x105270, 3, RI_ALL_ONLINE},
- { 0x105280, 3, RI_ALL_ONLINE}, { 0x105290, 3, RI_ALL_ONLINE},
- { 0x1052a0, 3, RI_ALL_ONLINE}, { 0x1052b0, 3, RI_ALL_ONLINE},
- { 0x1052c0, 3, RI_ALL_ONLINE}, { 0x1052d0, 3, RI_ALL_ONLINE},
- { 0x1052e0, 3, RI_ALL_ONLINE}, { 0x1052f0, 3, RI_ALL_ONLINE},
- { 0x105300, 3, RI_ALL_ONLINE}, { 0x105310, 3, RI_ALL_ONLINE},
- { 0x105320, 3, RI_ALL_ONLINE}, { 0x105330, 3, RI_ALL_ONLINE},
- { 0x105340, 3, RI_ALL_ONLINE}, { 0x105350, 3, RI_ALL_ONLINE},
- { 0x105360, 3, RI_ALL_ONLINE}, { 0x105370, 3, RI_ALL_ONLINE},
- { 0x105380, 3, RI_ALL_ONLINE}, { 0x105390, 3, RI_ALL_ONLINE},
- { 0x1053a0, 3, RI_ALL_ONLINE}, { 0x1053b0, 3, RI_ALL_ONLINE},
- { 0x1053c0, 3, RI_ALL_ONLINE}, { 0x1053d0, 3, RI_ALL_ONLINE},
- { 0x1053e0, 3, RI_ALL_ONLINE}, { 0x1053f0, 3, RI_ALL_ONLINE},
- { 0x108094, 1, RI_ALL_ONLINE}, { 0x1201b0, 2, RI_ALL_ONLINE},
- { 0x12032c, 1, RI_ALL_ONLINE}, { 0x12036c, 3, RI_ALL_ONLINE},
- { 0x120408, 2, RI_ALL_ONLINE}, { 0x120414, 15, RI_ALL_ONLINE},
- { 0x120478, 2, RI_ALL_ONLINE}, { 0x12052c, 1, RI_ALL_ONLINE},
- { 0x120564, 3, RI_ALL_ONLINE}, { 0x12057c, 1, RI_ALL_ONLINE},
- { 0x12058c, 1, RI_ALL_ONLINE}, { 0x120608, 1, RI_E1H_ONLINE},
- { 0x120808, 1, RI_E1_ONLINE}, { 0x12080c, 2, RI_ALL_ONLINE},
- { 0x120818, 1, RI_ALL_ONLINE}, { 0x120820, 1, RI_ALL_ONLINE},
- { 0x120828, 1, RI_ALL_ONLINE}, { 0x120830, 1, RI_ALL_ONLINE},
- { 0x120838, 1, RI_ALL_ONLINE}, { 0x120840, 1, RI_ALL_ONLINE},
- { 0x120848, 1, RI_ALL_ONLINE}, { 0x120850, 1, RI_ALL_ONLINE},
- { 0x120858, 1, RI_ALL_ONLINE}, { 0x120860, 1, RI_ALL_ONLINE},
- { 0x120868, 1, RI_ALL_ONLINE}, { 0x120870, 1, RI_ALL_ONLINE},
- { 0x120878, 1, RI_ALL_ONLINE}, { 0x120880, 1, RI_ALL_ONLINE},
- { 0x120888, 1, RI_ALL_ONLINE}, { 0x120890, 1, RI_ALL_ONLINE},
- { 0x120898, 1, RI_ALL_ONLINE}, { 0x1208a0, 1, RI_ALL_ONLINE},
- { 0x1208a8, 1, RI_ALL_ONLINE}, { 0x1208b0, 1, RI_ALL_ONLINE},
- { 0x1208b8, 1, RI_ALL_ONLINE}, { 0x1208c0, 1, RI_ALL_ONLINE},
- { 0x1208c8, 1, RI_ALL_ONLINE}, { 0x1208d0, 1, RI_ALL_ONLINE},
- { 0x1208d8, 1, RI_ALL_ONLINE}, { 0x1208e0, 1, RI_ALL_ONLINE},
- { 0x1208e8, 1, RI_ALL_ONLINE}, { 0x1208f0, 1, RI_ALL_ONLINE},
- { 0x1208f8, 1, RI_ALL_ONLINE}, { 0x120900, 1, RI_ALL_ONLINE},
- { 0x120908, 1, RI_ALL_ONLINE}, { 0x14005c, 2, RI_ALL_ONLINE},
- { 0x1400d0, 2, RI_ALL_ONLINE}, { 0x1400e0, 1, RI_ALL_ONLINE},
- { 0x1401c8, 1, RI_ALL_ONLINE}, { 0x140200, 6, RI_ALL_ONLINE},
- { 0x16101c, 1, RI_ALL_ONLINE}, { 0x16102c, 1, RI_ALL_ONLINE},
- { 0x164014, 2, RI_ALL_ONLINE}, { 0x1640f0, 1, RI_ALL_ONLINE},
- { 0x166290, 1, RI_ALL_ONLINE}, { 0x1662a0, 1, RI_ALL_ONLINE},
- { 0x1662b0, 1, RI_ALL_ONLINE}, { 0x166548, 1, RI_ALL_ONLINE},
- { 0x166550, 1, RI_ALL_ONLINE}, { 0x166558, 1, RI_ALL_ONLINE},
- { 0x168000, 1, RI_ALL_ONLINE}, { 0x168008, 1, RI_ALL_ONLINE},
- { 0x168010, 1, RI_ALL_ONLINE}, { 0x168018, 1, RI_ALL_ONLINE},
- { 0x168028, 2, RI_ALL_ONLINE}, { 0x168058, 4, RI_ALL_ONLINE},
- { 0x168070, 1, RI_ALL_ONLINE}, { 0x168238, 1, RI_ALL_ONLINE},
- { 0x1682d0, 2, RI_ALL_ONLINE}, { 0x1682e0, 1, RI_ALL_ONLINE},
- { 0x168300, 67, RI_ALL_ONLINE}, { 0x168410, 2, RI_ALL_ONLINE},
- { 0x168438, 1, RI_ALL_ONLINE}, { 0x168448, 1, RI_ALL_ONLINE},
- { 0x168a00, 128, RI_ALL_ONLINE}, { 0x16e200, 128, RI_E1H_ONLINE},
- { 0x16e404, 2, RI_E1H_ONLINE}, { 0x16e584, 70, RI_E1H_ONLINE},
- { 0x1700a4, 1, RI_ALL_ONLINE}, { 0x1700ac, 2, RI_ALL_ONLINE},
- { 0x1700c0, 1, RI_ALL_ONLINE}, { 0x170174, 1, RI_ALL_ONLINE},
- { 0x170184, 1, RI_ALL_ONLINE}, { 0x1800f4, 1, RI_ALL_ONLINE},
- { 0x180104, 1, RI_ALL_ONLINE}, { 0x180114, 1, RI_ALL_ONLINE},
- { 0x180124, 1, RI_ALL_ONLINE}, { 0x18026c, 1, RI_ALL_ONLINE},
- { 0x1802a0, 1, RI_ALL_ONLINE}, { 0x1a1000, 1, RI_ALL_ONLINE},
- { 0x1aa000, 1, RI_E1H_ONLINE}, { 0x1b8000, 1, RI_ALL_ONLINE},
- { 0x1b8040, 1, RI_ALL_ONLINE}, { 0x1b8080, 1, RI_ALL_ONLINE},
- { 0x1b80c0, 1, RI_ALL_ONLINE}, { 0x200104, 1, RI_ALL_ONLINE},
- { 0x200114, 1, RI_ALL_ONLINE}, { 0x200124, 1, RI_ALL_ONLINE},
- { 0x200134, 1, RI_ALL_ONLINE}, { 0x20026c, 1, RI_ALL_ONLINE},
- { 0x2002a0, 1, RI_ALL_ONLINE}, { 0x221000, 1, RI_ALL_ONLINE},
- { 0x227000, 1, RI_E1H_ONLINE}, { 0x238000, 1, RI_ALL_ONLINE},
- { 0x238040, 1, RI_ALL_ONLINE}, { 0x238080, 1, RI_ALL_ONLINE},
- { 0x2380c0, 1, RI_ALL_ONLINE}, { 0x280104, 1, RI_ALL_ONLINE},
- { 0x280114, 1, RI_ALL_ONLINE}, { 0x280124, 1, RI_ALL_ONLINE},
- { 0x280134, 1, RI_ALL_ONLINE}, { 0x28026c, 1, RI_ALL_ONLINE},
- { 0x2802a0, 1, RI_ALL_ONLINE}, { 0x2a1000, 1, RI_ALL_ONLINE},
- { 0x2a9000, 1, RI_E1H_ONLINE}, { 0x2b8000, 1, RI_ALL_ONLINE},
- { 0x2b8040, 1, RI_ALL_ONLINE}, { 0x2b8080, 1, RI_ALL_ONLINE},
- { 0x2b80c0, 1, RI_ALL_ONLINE}, { 0x300104, 1, RI_ALL_ONLINE},
- { 0x300114, 1, RI_ALL_ONLINE}, { 0x300124, 1, RI_ALL_ONLINE},
- { 0x300134, 1, RI_ALL_ONLINE}, { 0x30026c, 1, RI_ALL_ONLINE},
- { 0x3002a0, 1, RI_ALL_ONLINE}, { 0x321000, 1, RI_ALL_ONLINE},
- { 0x328960, 1, RI_E1H_ONLINE}, { 0x338000, 1, RI_ALL_ONLINE},
- { 0x338040, 1, RI_ALL_ONLINE}, { 0x338080, 1, RI_ALL_ONLINE},
- { 0x3380c0, 1, RI_ALL_ONLINE}
+#define IDLE_REGS_COUNT 277
+static const struct reg_addr idle_addrs[IDLE_REGS_COUNT] = {
+ { 0x2114, 1, RI_ALL_ONLINE }, { 0x2120, 1, RI_ALL_ONLINE },
+ { 0x212c, 4, RI_ALL_ONLINE }, { 0x2814, 1, RI_ALL_ONLINE },
+ { 0x281c, 2, RI_ALL_ONLINE }, { 0xa38c, 1, RI_ALL_ONLINE },
+ { 0xa408, 1, RI_ALL_ONLINE }, { 0xa42c, 12, RI_ALL_ONLINE },
+ { 0xa600, 5, RI_E1H_ONLINE }, { 0xa618, 1, RI_E1H_ONLINE },
+ { 0xc09c, 1, RI_ALL_ONLINE }, { 0x103b0, 1, RI_ALL_ONLINE },
+ { 0x103c0, 1, RI_ALL_ONLINE }, { 0x103d0, 1, RI_E1H_ONLINE },
+ { 0x2021c, 11, RI_ALL_ONLINE }, { 0x202a8, 1, RI_ALL_ONLINE },
+ { 0x202b8, 1, RI_ALL_ONLINE }, { 0x20404, 1, RI_ALL_ONLINE },
+ { 0x2040c, 2, RI_ALL_ONLINE }, { 0x2041c, 2, RI_ALL_ONLINE },
+ { 0x40154, 14, RI_ALL_ONLINE }, { 0x40198, 1, RI_ALL_ONLINE },
+ { 0x404ac, 1, RI_ALL_ONLINE }, { 0x404bc, 1, RI_ALL_ONLINE },
+ { 0x42290, 1, RI_ALL_ONLINE }, { 0x422a0, 1, RI_ALL_ONLINE },
+ { 0x422b0, 1, RI_ALL_ONLINE }, { 0x42548, 1, RI_ALL_ONLINE },
+ { 0x42550, 1, RI_ALL_ONLINE }, { 0x42558, 1, RI_ALL_ONLINE },
+ { 0x50160, 8, RI_ALL_ONLINE }, { 0x501d0, 1, RI_ALL_ONLINE },
+ { 0x501e0, 1, RI_ALL_ONLINE }, { 0x50204, 1, RI_ALL_ONLINE },
+ { 0x5020c, 2, RI_ALL_ONLINE }, { 0x5021c, 1, RI_ALL_ONLINE },
+ { 0x60090, 1, RI_ALL_ONLINE }, { 0x6011c, 1, RI_ALL_ONLINE },
+ { 0x6012c, 1, RI_ALL_ONLINE }, { 0xc101c, 1, RI_ALL_ONLINE },
+ { 0xc102c, 1, RI_ALL_ONLINE }, { 0xc2290, 1, RI_ALL_ONLINE },
+ { 0xc22a0, 1, RI_ALL_ONLINE }, { 0xc22b0, 1, RI_ALL_ONLINE },
+ { 0xc2548, 1, RI_ALL_ONLINE }, { 0xc2550, 1, RI_ALL_ONLINE },
+ { 0xc2558, 1, RI_ALL_ONLINE }, { 0xc4294, 1, RI_ALL_ONLINE },
+ { 0xc42a4, 1, RI_ALL_ONLINE }, { 0xc42b4, 1, RI_ALL_ONLINE },
+ { 0xc4550, 1, RI_ALL_ONLINE }, { 0xc4558, 1, RI_ALL_ONLINE },
+ { 0xc4560, 1, RI_ALL_ONLINE }, { 0xd016c, 8, RI_ALL_ONLINE },
+ { 0xd01d8, 1, RI_ALL_ONLINE }, { 0xd01e8, 1, RI_ALL_ONLINE },
+ { 0xd0204, 1, RI_ALL_ONLINE }, { 0xd020c, 3, RI_ALL_ONLINE },
+ { 0xe0154, 8, RI_ALL_ONLINE }, { 0xe01c8, 1, RI_ALL_ONLINE },
+ { 0xe01d8, 1, RI_ALL_ONLINE }, { 0xe0204, 1, RI_ALL_ONLINE },
+ { 0xe020c, 2, RI_ALL_ONLINE }, { 0xe021c, 2, RI_ALL_ONLINE },
+ { 0x101014, 1, RI_ALL_ONLINE }, { 0x101030, 1, RI_ALL_ONLINE },
+ { 0x101040, 1, RI_ALL_ONLINE }, { 0x102058, 1, RI_ALL_ONLINE },
+ { 0x102080, 16, RI_ALL_ONLINE }, { 0x103004, 2, RI_ALL_ONLINE },
+ { 0x103068, 1, RI_ALL_ONLINE }, { 0x103078, 1, RI_ALL_ONLINE },
+ { 0x103088, 1, RI_ALL_ONLINE }, { 0x10309c, 2, RI_E1H_ONLINE },
+ { 0x104004, 1, RI_ALL_ONLINE }, { 0x104018, 1, RI_ALL_ONLINE },
+ { 0x104020, 1, RI_ALL_ONLINE }, { 0x10403c, 1, RI_ALL_ONLINE },
+ { 0x1040fc, 1, RI_ALL_ONLINE }, { 0x10410c, 1, RI_ALL_ONLINE },
+ { 0x104400, 64, RI_ALL_ONLINE }, { 0x104800, 64, RI_ALL_ONLINE },
+ { 0x105000, 3, RI_ALL_ONLINE }, { 0x105010, 3, RI_ALL_ONLINE },
+ { 0x105020, 3, RI_ALL_ONLINE }, { 0x105030, 3, RI_ALL_ONLINE },
+ { 0x105040, 3, RI_ALL_ONLINE }, { 0x105050, 3, RI_ALL_ONLINE },
+ { 0x105060, 3, RI_ALL_ONLINE }, { 0x105070, 3, RI_ALL_ONLINE },
+ { 0x105080, 3, RI_ALL_ONLINE }, { 0x105090, 3, RI_ALL_ONLINE },
+ { 0x1050a0, 3, RI_ALL_ONLINE }, { 0x1050b0, 3, RI_ALL_ONLINE },
+ { 0x1050c0, 3, RI_ALL_ONLINE }, { 0x1050d0, 3, RI_ALL_ONLINE },
+ { 0x1050e0, 3, RI_ALL_ONLINE }, { 0x1050f0, 3, RI_ALL_ONLINE },
+ { 0x105100, 3, RI_ALL_ONLINE }, { 0x105110, 3, RI_ALL_ONLINE },
+ { 0x105120, 3, RI_ALL_ONLINE }, { 0x105130, 3, RI_ALL_ONLINE },
+ { 0x105140, 3, RI_ALL_ONLINE }, { 0x105150, 3, RI_ALL_ONLINE },
+ { 0x105160, 3, RI_ALL_ONLINE }, { 0x105170, 3, RI_ALL_ONLINE },
+ { 0x105180, 3, RI_ALL_ONLINE }, { 0x105190, 3, RI_ALL_ONLINE },
+ { 0x1051a0, 3, RI_ALL_ONLINE }, { 0x1051b0, 3, RI_ALL_ONLINE },
+ { 0x1051c0, 3, RI_ALL_ONLINE }, { 0x1051d0, 3, RI_ALL_ONLINE },
+ { 0x1051e0, 3, RI_ALL_ONLINE }, { 0x1051f0, 3, RI_ALL_ONLINE },
+ { 0x105200, 3, RI_ALL_ONLINE }, { 0x105210, 3, RI_ALL_ONLINE },
+ { 0x105220, 3, RI_ALL_ONLINE }, { 0x105230, 3, RI_ALL_ONLINE },
+ { 0x105240, 3, RI_ALL_ONLINE }, { 0x105250, 3, RI_ALL_ONLINE },
+ { 0x105260, 3, RI_ALL_ONLINE }, { 0x105270, 3, RI_ALL_ONLINE },
+ { 0x105280, 3, RI_ALL_ONLINE }, { 0x105290, 3, RI_ALL_ONLINE },
+ { 0x1052a0, 3, RI_ALL_ONLINE }, { 0x1052b0, 3, RI_ALL_ONLINE },
+ { 0x1052c0, 3, RI_ALL_ONLINE }, { 0x1052d0, 3, RI_ALL_ONLINE },
+ { 0x1052e0, 3, RI_ALL_ONLINE }, { 0x1052f0, 3, RI_ALL_ONLINE },
+ { 0x105300, 3, RI_ALL_ONLINE }, { 0x105310, 3, RI_ALL_ONLINE },
+ { 0x105320, 3, RI_ALL_ONLINE }, { 0x105330, 3, RI_ALL_ONLINE },
+ { 0x105340, 3, RI_ALL_ONLINE }, { 0x105350, 3, RI_ALL_ONLINE },
+ { 0x105360, 3, RI_ALL_ONLINE }, { 0x105370, 3, RI_ALL_ONLINE },
+ { 0x105380, 3, RI_ALL_ONLINE }, { 0x105390, 3, RI_ALL_ONLINE },
+ { 0x1053a0, 3, RI_ALL_ONLINE }, { 0x1053b0, 3, RI_ALL_ONLINE },
+ { 0x1053c0, 3, RI_ALL_ONLINE }, { 0x1053d0, 3, RI_ALL_ONLINE },
+ { 0x1053e0, 3, RI_ALL_ONLINE }, { 0x1053f0, 3, RI_ALL_ONLINE },
+ { 0x108094, 1, RI_ALL_ONLINE }, { 0x1201b0, 2, RI_ALL_ONLINE },
+ { 0x12032c, 1, RI_ALL_ONLINE }, { 0x12036c, 3, RI_ALL_ONLINE },
+ { 0x120408, 2, RI_ALL_ONLINE }, { 0x120414, 15, RI_ALL_ONLINE },
+ { 0x120478, 2, RI_ALL_ONLINE }, { 0x12052c, 1, RI_ALL_ONLINE },
+ { 0x120564, 3, RI_ALL_ONLINE }, { 0x12057c, 1, RI_ALL_ONLINE },
+ { 0x12058c, 1, RI_ALL_ONLINE }, { 0x120608, 1, RI_E1H_ONLINE },
+ { 0x120808, 1, RI_E1_ONLINE }, { 0x12080c, 2, RI_ALL_ONLINE },
+ { 0x120818, 1, RI_ALL_ONLINE }, { 0x120820, 1, RI_ALL_ONLINE },
+ { 0x120828, 1, RI_ALL_ONLINE }, { 0x120830, 1, RI_ALL_ONLINE },
+ { 0x120838, 1, RI_ALL_ONLINE }, { 0x120840, 1, RI_ALL_ONLINE },
+ { 0x120848, 1, RI_ALL_ONLINE }, { 0x120850, 1, RI_ALL_ONLINE },
+ { 0x120858, 1, RI_ALL_ONLINE }, { 0x120860, 1, RI_ALL_ONLINE },
+ { 0x120868, 1, RI_ALL_ONLINE }, { 0x120870, 1, RI_ALL_ONLINE },
+ { 0x120878, 1, RI_ALL_ONLINE }, { 0x120880, 1, RI_ALL_ONLINE },
+ { 0x120888, 1, RI_ALL_ONLINE }, { 0x120890, 1, RI_ALL_ONLINE },
+ { 0x120898, 1, RI_ALL_ONLINE }, { 0x1208a0, 1, RI_ALL_ONLINE },
+ { 0x1208a8, 1, RI_ALL_ONLINE }, { 0x1208b0, 1, RI_ALL_ONLINE },
+ { 0x1208b8, 1, RI_ALL_ONLINE }, { 0x1208c0, 1, RI_ALL_ONLINE },
+ { 0x1208c8, 1, RI_ALL_ONLINE }, { 0x1208d0, 1, RI_ALL_ONLINE },
+ { 0x1208d8, 1, RI_ALL_ONLINE }, { 0x1208e0, 1, RI_ALL_ONLINE },
+ { 0x1208e8, 1, RI_ALL_ONLINE }, { 0x1208f0, 1, RI_ALL_ONLINE },
+ { 0x1208f8, 1, RI_ALL_ONLINE }, { 0x120900, 1, RI_ALL_ONLINE },
+ { 0x120908, 1, RI_ALL_ONLINE }, { 0x14005c, 2, RI_ALL_ONLINE },
+ { 0x1400d0, 2, RI_ALL_ONLINE }, { 0x1400e0, 1, RI_ALL_ONLINE },
+ { 0x1401c8, 1, RI_ALL_ONLINE }, { 0x140200, 6, RI_ALL_ONLINE },
+ { 0x16101c, 1, RI_ALL_ONLINE }, { 0x16102c, 1, RI_ALL_ONLINE },
+ { 0x164014, 2, RI_ALL_ONLINE }, { 0x1640f0, 1, RI_ALL_ONLINE },
+ { 0x166290, 1, RI_ALL_ONLINE }, { 0x1662a0, 1, RI_ALL_ONLINE },
+ { 0x1662b0, 1, RI_ALL_ONLINE }, { 0x166548, 1, RI_ALL_ONLINE },
+ { 0x166550, 1, RI_ALL_ONLINE }, { 0x166558, 1, RI_ALL_ONLINE },
+ { 0x168000, 1, RI_ALL_ONLINE }, { 0x168008, 1, RI_ALL_ONLINE },
+ { 0x168010, 1, RI_ALL_ONLINE }, { 0x168018, 1, RI_ALL_ONLINE },
+ { 0x168028, 2, RI_ALL_ONLINE }, { 0x168058, 4, RI_ALL_ONLINE },
+ { 0x168070, 1, RI_ALL_ONLINE }, { 0x168238, 1, RI_ALL_ONLINE },
+ { 0x1682d0, 2, RI_ALL_ONLINE }, { 0x1682e0, 1, RI_ALL_ONLINE },
+ { 0x168300, 67, RI_ALL_ONLINE }, { 0x168410, 2, RI_ALL_ONLINE },
+ { 0x168438, 1, RI_ALL_ONLINE }, { 0x168448, 1, RI_ALL_ONLINE },
+ { 0x168a00, 128, RI_ALL_ONLINE }, { 0x16e200, 128, RI_E1H_ONLINE },
+ { 0x16e404, 2, RI_E1H_ONLINE }, { 0x16e584, 70, RI_E1H_ONLINE },
+ { 0x1700a4, 1, RI_ALL_ONLINE }, { 0x1700ac, 2, RI_ALL_ONLINE },
+ { 0x1700c0, 1, RI_ALL_ONLINE }, { 0x170174, 1, RI_ALL_ONLINE },
+ { 0x170184, 1, RI_ALL_ONLINE }, { 0x1800f4, 1, RI_ALL_ONLINE },
+ { 0x180104, 1, RI_ALL_ONLINE }, { 0x180114, 1, RI_ALL_ONLINE },
+ { 0x180124, 1, RI_ALL_ONLINE }, { 0x18026c, 1, RI_ALL_ONLINE },
+ { 0x1802a0, 1, RI_ALL_ONLINE }, { 0x1a1000, 1, RI_ALL_ONLINE },
+ { 0x1aa000, 1, RI_E1H_ONLINE }, { 0x1b8000, 1, RI_ALL_ONLINE },
+ { 0x1b8040, 1, RI_ALL_ONLINE }, { 0x1b8080, 1, RI_ALL_ONLINE },
+ { 0x1b80c0, 1, RI_ALL_ONLINE }, { 0x200104, 1, RI_ALL_ONLINE },
+ { 0x200114, 1, RI_ALL_ONLINE }, { 0x200124, 1, RI_ALL_ONLINE },
+ { 0x200134, 1, RI_ALL_ONLINE }, { 0x20026c, 1, RI_ALL_ONLINE },
+ { 0x2002a0, 1, RI_ALL_ONLINE }, { 0x221000, 1, RI_ALL_ONLINE },
+ { 0x227000, 1, RI_E1H_ONLINE }, { 0x238000, 1, RI_ALL_ONLINE },
+ { 0x238040, 1, RI_ALL_ONLINE }, { 0x238080, 1, RI_ALL_ONLINE },
+ { 0x2380c0, 1, RI_ALL_ONLINE }, { 0x280104, 1, RI_ALL_ONLINE },
+ { 0x280114, 1, RI_ALL_ONLINE }, { 0x280124, 1, RI_ALL_ONLINE },
+ { 0x280134, 1, RI_ALL_ONLINE }, { 0x28026c, 1, RI_ALL_ONLINE },
+ { 0x2802a0, 1, RI_ALL_ONLINE }, { 0x2a1000, 1, RI_ALL_ONLINE },
+ { 0x2a9000, 1, RI_E1H_ONLINE }, { 0x2b8000, 1, RI_ALL_ONLINE },
+ { 0x2b8040, 1, RI_ALL_ONLINE }, { 0x2b8080, 1, RI_ALL_ONLINE },
+ { 0x2b80c0, 1, RI_ALL_ONLINE }, { 0x300104, 1, RI_ALL_ONLINE },
+ { 0x300114, 1, RI_ALL_ONLINE }, { 0x300124, 1, RI_ALL_ONLINE },
+ { 0x300134, 1, RI_ALL_ONLINE }, { 0x30026c, 1, RI_ALL_ONLINE },
+ { 0x3002a0, 1, RI_ALL_ONLINE }, { 0x321000, 1, RI_ALL_ONLINE },
+ { 0x328960, 1, RI_E1H_ONLINE }, { 0x338000, 1, RI_ALL_ONLINE },
+ { 0x338040, 1, RI_ALL_ONLINE }, { 0x338080, 1, RI_ALL_ONLINE },
+ { 0x3380c0, 1, RI_ALL_ONLINE }
};
+#define WREGS_COUNT_E1 1
static const u32 read_reg_e1_0[] = { 0x1b1000 };
-#define WREGS_COUNT_E1 1
static const struct wreg_addr wreg_addrs_e1[WREGS_COUNT_E1] = {
{ 0x1b0c00, 192, 1, read_reg_e1_0, RI_E1_OFFLINE }
};
+
+#define WREGS_COUNT_E1H 1
static const u32 read_reg_e1h_0[] = { 0x1b1040, 0x1b1000 };
-#define WREGS_COUNT_E1H 1
static const struct wreg_addr wreg_addrs_e1h[WREGS_COUNT_E1H] = {
{ 0x1b0c00, 256, 2, read_reg_e1h_0, RI_E1H_OFFLINE }
};
@@ -512,15 +517,18 @@ static const struct wreg_addr wreg_addrs_e1h[WREGS_COUNT_E1H] = {
static const struct dump_sign dump_sign_all = { 0x49aa93ee, 0x40835, 0x22 };
-#define TIMER_REGS_COUNT_E1 2
+#define TIMER_REGS_COUNT_E1 2
static const u32 timer_status_regs_e1[TIMER_REGS_COUNT_E1] =
{ 0x164014, 0x164018 };
static const u32 timer_scan_regs_e1[TIMER_REGS_COUNT_E1] =
{ 0x1640d0, 0x1640d4 };
-#define TIMER_REGS_COUNT_E1H 2
+
+#define TIMER_REGS_COUNT_E1H 2
static const u32 timer_status_regs_e1h[TIMER_REGS_COUNT_E1H] =
{ 0x164014, 0x164018 };
static const u32 timer_scan_regs_e1h[TIMER_REGS_COUNT_E1H] =
{ 0x1640d0, 0x1640d4 };
+
+#endif /* BNX2X_DUMP_H */
diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h
index e2df238..931dcac 100644
--- a/drivers/net/bnx2x_fw_defs.h
+++ b/drivers/net/bnx2x_fw_defs.h
@@ -12,48 +12,117 @@
(IS_E1H_OFFSET ? 0x7000 : 0x1000)
#define CSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
-#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
- (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \
- ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
+#define CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(function, index) \
+ (IS_E1H_OFFSET ? (0x8622 + ((function>>1) * 0x40) + \
+ ((function&1) * 0x100) + (index * 0x4)) : (0x3562 + (function * \
0x40) + (index * 0x4)))
-#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \
- ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
-#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \
- ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
+#define CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(function, index) \
+ (IS_E1H_OFFSET ? (0x8822 + ((function>>1) * 0x80) + \
+ ((function&1) * 0x200) + (index * 0x4)) : (0x35e2 + (function * \
+ 0x80) + (index * 0x4)))
+#define CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8600 + ((function>>1) * 0x40) + \
+ ((function&1) * 0x100)) : (0x3540 + (function * 0x40)))
+#define CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8800 + ((function>>1) * 0x80) + \
+ ((function&1) * 0x200)) : (0x35c0 + (function * 0x80)))
+#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8608 + ((function>>1) * 0x40) + \
+ ((function&1) * 0x100)) : (0x3548 + (function * 0x40)))
+#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8808 + ((function>>1) * 0x80) + \
+ ((function&1) * 0x200)) : (0x35c8 + (function * 0x80)))
#define CSTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
-#define CSTORM_HC_BTR_OFFSET(port) \
- (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
-#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
- (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
- (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
+#define CSTORM_HC_BTR_C_OFFSET(port) \
+ (IS_E1H_OFFSET ? (0x8c04 + (port * 0xf0)) : (0x36c4 + (port * 0xc0)))
+#define CSTORM_HC_BTR_U_OFFSET(port) \
+ (IS_E1H_OFFSET ? (0x8de4 + (port * 0xf0)) : (0x3844 + (port * 0xc0)))
+#define CSTORM_ISCSI_CQ_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6680 + (function * 0x8)) : (0x25a0 + \
+ (function * 0x8)))
+#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x66c0 + (function * 0x8)) : (0x25b0 + \
+ (function * 0x8)))
+#define CSTORM_ISCSI_EQ_CONS_OFFSET(function, eqIdx) \
+ (IS_E1H_OFFSET ? (0x6040 + (function * 0xc0) + (eqIdx * 0x18)) : \
+ (0x2410 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(function, eqIdx) \
+ (IS_E1H_OFFSET ? (0x6044 + (function * 0xc0) + (eqIdx * 0x18)) : \
+ (0x2414 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(function, eqIdx) \
+ (IS_E1H_OFFSET ? (0x604c + (function * 0xc0) + (eqIdx * 0x18)) : \
+ (0x241c + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(function, eqIdx) \
+ (IS_E1H_OFFSET ? (0x6057 + (function * 0xc0) + (eqIdx * 0x18)) : \
+ (0x2427 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_PROD_OFFSET(function, eqIdx) \
+ (IS_E1H_OFFSET ? (0x6042 + (function * 0xc0) + (eqIdx * 0x18)) : \
+ (0x2412 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(function, eqIdx) \
+ (IS_E1H_OFFSET ? (0x6056 + (function * 0xc0) + (eqIdx * 0x18)) : \
+ (0x2426 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(function, eqIdx) \
+ (IS_E1H_OFFSET ? (0x6054 + (function * 0xc0) + (eqIdx * 0x18)) : \
+ (0x2424 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6640 + (function * 0x8)) : (0x2590 + \
+ (function * 0x8)))
+#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x2404 + \
+ (function * 0x8)))
+#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x2402 + \
+ (function * 0x8)))
+#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x2400 + \
+ (function * 0x8)))
+#define CSTORM_SB_HC_DISABLE_C_OFFSET(port, cpu_id, index) \
+ (IS_E1H_OFFSET ? (0x811a + (port * 0x280) + (cpu_id * 0x28) + \
+ (index * 0x4)) : (0x305a + (port * 0x280) + (cpu_id * 0x28) + \
+ (index * 0x4)))
+#define CSTORM_SB_HC_DISABLE_U_OFFSET(port, cpu_id, index) \
+ (IS_E1H_OFFSET ? (0xb01a + (port * 0x800) + (cpu_id * 0x80) + \
+ (index * 0x4)) : (0x401a + (port * 0x800) + (cpu_id * 0x80) + \
(index * 0x4)))
-#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
- (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
- (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
+#define CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, cpu_id, index) \
+ (IS_E1H_OFFSET ? (0x8118 + (port * 0x280) + (cpu_id * 0x28) + \
+ (index * 0x4)) : (0x3058 + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)))
-#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
- (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
- (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
-#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
- (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
- (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
+#define CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, cpu_id, index) \
+ (IS_E1H_OFFSET ? (0xb018 + (port * 0x800) + (cpu_id * 0x80) + \
+ (index * 0x4)) : (0x4018 + (port * 0x800) + (cpu_id * 0x80) + \
+ (index * 0x4)))
+#define CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, cpu_id) \
+ (IS_E1H_OFFSET ? (0x8100 + (port * 0x280) + (cpu_id * 0x28)) : \
+ (0x3040 + (port * 0x280) + (cpu_id * 0x28)))
+#define CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, cpu_id) \
+ (IS_E1H_OFFSET ? (0xb000 + (port * 0x800) + (cpu_id * 0x80)) : \
+ (0x4000 + (port * 0x800) + (cpu_id * 0x80)))
+#define CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, cpu_id) \
+ (IS_E1H_OFFSET ? (0x8108 + (port * 0x280) + (cpu_id * 0x28)) : \
+ (0x3048 + (port * 0x280) + (cpu_id * 0x28)))
+#define CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, cpu_id) \
+ (IS_E1H_OFFSET ? (0xb008 + (port * 0x800) + (cpu_id * 0x80)) : \
+ (0x4008 + (port * 0x800) + (cpu_id * 0x80)))
+#define CSTORM_SB_STATUS_BLOCK_C_SIZE 0x10
+#define CSTORM_SB_STATUS_BLOCK_U_SIZE 0x60
#define CSTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
(function * 0x8)))
#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff)
+ (IS_E1H_OFFSET ? (0x3200 + (function * 0x20)) : 0xffffffff)
#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET ? 0xa000 : 0x1000)
#define TSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
- (IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \
- : (0x9c0 + (port * 0x130) + (client_id * 0x10)))
+ (IS_E1H_OFFSET ? (0x33a0 + (port * 0x1a0) + (client_id * 0x10)) \
+ : (0x9c0 + (port * 0x120) + (client_id * 0x10)))
#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
- (IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff)
+ (IS_E1H_OFFSET ? 0x1ed8 : 0xffffffff)
+#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
+ (IS_E1H_OFFSET ? 0x1eda : 0xffffffff)
#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
@@ -65,95 +134,133 @@
(IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \
+ (IS_E1H_OFFSET ? (0x2940 + (function * 0x8)) : (0x4928 + \
(function * 0x8)))
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \
- (function * 0x38)))
+ (IS_E1H_OFFSET ? (0x3000 + (function * 0x40)) : (0x1500 + \
+ (function * 0x40)))
#define TSTORM_FUNCTION_MODE_OFFSET \
- (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff)
+ (IS_E1H_OFFSET ? 0x1ed0 : 0xffffffff)
#define TSTORM_HC_BTR_OFFSET(port) \
(IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
(function * 0x80)))
#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
+#define TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(function, pblEntry) \
+ (IS_E1H_OFFSET ? (0x60c0 + (function * 0x40) + (pblEntry * 0x8)) \
+ : (0x4c30 + (function * 0x40) + (pblEntry * 0x8)))
+#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6340 + (function * 0x8)) : (0x4cd0 + \
+ (function * 0x8)))
+#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x4c04 + \
+ (function * 0x8)))
+#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x4c02 + \
+ (function * 0x8)))
+#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x4c00 + \
+ (function * 0x8)))
+#define TSTORM_ISCSI_RQ_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6080 + (function * 0x8)) : (0x4c20 + \
+ (function * 0x8)))
+#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6040 + (function * 0x8)) : (0x4c10 + \
+ (function * 0x8)))
+#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6042 + (function * 0x8)) : (0x4c12 + \
+ (function * 0x8)))
+#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x6044 + (function * 0x8)) : (0x4c14 + \
+ (function * 0x8)))
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \
- (function * 0x38)))
+ (IS_E1H_OFFSET ? (0x3008 + (function * 0x40)) : (0x1508 + \
+ (function * 0x40)))
#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
- (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
- 0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50)))
+ (IS_E1H_OFFSET ? (0x2010 + (port * 0x490) + (stats_counter_id * \
+ 0x40)) : (0x4010 + (port * 0x490) + (stats_counter_id * 0x40)))
#define TSTORM_STATS_FLAGS_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
+ (IS_E1H_OFFSET ? (0x29c0 + (function * 0x8)) : (0x4948 + \
(function * 0x8)))
-#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20)
-#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
-#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
+#define TSTORM_TCP_MAX_CWND_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x4004 + (function * 0x8)) : (0x1fb4 + \
+ (function * 0x8)))
+#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa000 : 0x3000)
+#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2000 : 0x1000)
#define USTORM_ASSERT_LIST_INDEX_OFFSET \
- (IS_E1H_OFFSET ? 0x8960 : 0x1000)
+ (IS_E1H_OFFSET ? 0x8000 : 0x1000)
#define USTORM_ASSERT_LIST_OFFSET(idx) \
- (IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+ (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
- (IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \
- (0x5330 + (port * 0x260) + (clientId * 0x20)))
-#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
- (IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \
- ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
- 0x40) + (index * 0x4)))
-#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \
- ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
-#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \
- ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
+ (IS_E1H_OFFSET ? (0x1010 + (port * 0x680) + (clientId * 0x40)) : \
+ (0x4010 + (port * 0x360) + (clientId * 0x30)))
+#define USTORM_CQE_PAGE_NEXT_OFFSET(port, clientId) \
+ (IS_E1H_OFFSET ? (0x1028 + (port * 0x680) + (clientId * 0x40)) : \
+ (0x4028 + (port * 0x360) + (clientId * 0x30)))
+#define USTORM_ETH_PAUSE_ENABLED_OFFSET(port) \
+ (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
#define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \
- (IS_E1H_OFFSET ? (0x8020 + (port * 0x4b0) + (clientId * 0x30)) : \
+ (IS_E1H_OFFSET ? (0x1030 + (port * 0x680) + (clientId * 0x40)) : \
0xffffffff)
#define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1d98 + \
+ (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1dd0 + \
(function * 0x8)))
#define USTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
-#define USTORM_HC_BTR_OFFSET(port) \
- (IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
+#define USTORM_ISCSI_CQ_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x7044 + (function * 0x8)) : (0x2414 + \
+ (function * 0x8)))
+#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x7046 + (function * 0x8)) : (0x2416 + \
+ (function * 0x8)))
+#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x7688 + (function * 0x8)) : (0x29c8 + \
+ (function * 0x8)))
+#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x7648 + (function * 0x8)) : (0x29b8 + \
+ (function * 0x8)))
+#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x7004 + (function * 0x8)) : (0x2404 + \
+ (function * 0x8)))
+#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x7002 + (function * 0x8)) : (0x2402 + \
+ (function * 0x8)))
+#define USTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x7000 + (function * 0x8)) : (0x2400 + \
+ (function * 0x8)))
+#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x7040 + (function * 0x8)) : (0x2410 + \
+ (function * 0x8)))
+#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x7080 + (function * 0x8)) : (0x2420 + \
+ (function * 0x8)))
+#define USTORM_ISCSI_RQ_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x7084 + (function * 0x8)) : (0x2424 + \
+ (function * 0x8)))
#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
- (IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \
- (0x5328 + (port * 0x260) + (clientId * 0x20)))
+ (IS_E1H_OFFSET ? (0x1018 + (port * 0x680) + (clientId * 0x40)) : \
+ (0x4018 + (port * 0x360) + (clientId * 0x30)))
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \
+ (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x1da8 + \
(function * 0x8)))
-#define USTORM_PAUSE_ENABLED_OFFSET(port) \
- (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
#define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
(IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \
- 0x28)) : (0x4740 + (port * 0x2d0) + (stats_counter_id * 0x28)))
+ 0x28)) : (0x1500 + (port * 0x2d0) + (stats_counter_id * 0x28)))
#define USTORM_RX_PRODS_OFFSET(port, client_id) \
- (IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \
- : (0x5318 + (port * 0x260) + (client_id * 0x20)))
-#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
- (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
- (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
- (index * 0x4)))
-#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
- (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
- (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
- (index * 0x4)))
-#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
- (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
- (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
-#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
- (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
- (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
+ (IS_E1H_OFFSET ? (0x1000 + (port * 0x680) + (client_id * 0x40)) \
+ : (0x4000 + (port * 0x360) + (client_id * 0x30)))
#define USTORM_STATS_FLAGS_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1d80 + \
+ (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1db8 + \
(function * 0x8)))
+#define USTORM_TPA_BTR_OFFSET (IS_E1H_OFFSET ? 0x3da5 : 0x5095)
+#define USTORM_TPA_BTR_SIZE 0x1
#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET ? 0x9000 : 0x1000)
#define XSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
- (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50)))
+ (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3a80 + (port * 0x50)))
#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
@@ -165,22 +272,73 @@
(IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
#define XSTORM_E1HOV_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff)
+ (IS_E1H_OFFSET ? (0x2c10 + (function * 0x8)) : 0xffffffff)
#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
+ (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3a50 + \
(function * 0x8)))
#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \
+ (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3b60 + \
(function * 0x90)))
#define XSTORM_FUNCTION_MODE_OFFSET \
- (IS_E1H_OFFSET ? 0x2c20 : 0xffffffff)
+ (IS_E1H_OFFSET ? 0x2c50 : 0xffffffff)
#define XSTORM_HC_BTR_OFFSET(port) \
(IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
+#define XSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x80c0 + (function * 0x8)) : (0x1c30 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8080 + (function * 0x8)) : (0x1c20 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8081 + (function * 0x8)) : (0x1c21 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8082 + (function * 0x8)) : (0x1c22 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8083 + (function * 0x8)) : (0x1c23 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8084 + (function * 0x8)) : (0x1c24 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8085 + (function * 0x8)) : (0x1c25 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8086 + (function * 0x8)) : (0x1c26 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8004 + (function * 0x8)) : (0x1c04 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8002 + (function * 0x8)) : (0x1c02 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8000 + (function * 0x8)) : (0x1c00 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x80c4 + (function * 0x8)) : (0x1c34 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_SQ_SIZE_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x80c2 + (function * 0x8)) : (0x1c32 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8043 + (function * 0x8)) : (0x1c13 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8042 + (function * 0x8)) : (0x1c12 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8041 + (function * 0x8)) : (0x1c11 + \
+ (function * 0x8)))
+#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x8040 + (function * 0x8)) : (0x1c10 + \
+ (function * 0x8)))
#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
- (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
- 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
+ (IS_E1H_OFFSET ? (0xc000 + (port * 0x360) + (stats_counter_id * \
+ 0x30)) : (0x3378 + (port * 0x360) + (stats_counter_id * 0x30)))
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \
+ (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3b20 + \
(function * 0x90)))
#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
@@ -189,8 +347,15 @@
(IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
(function * 0x10)))
#define XSTORM_STATS_FLAGS_OFFSET(function) \
- (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \
+ (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3a40 + \
(function * 0x8)))
+#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port) \
+ (IS_E1H_OFFSET ? (0x4000 + (port * 0x8)) : (0x1960 + (port * 0x8)))
+#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port) \
+ (IS_E1H_OFFSET ? (0x4001 + (port * 0x8)) : (0x1961 + (port * 0x8)))
+#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(function) \
+ (IS_E1H_OFFSET ? (0x4060 + ((function>>1) * 0x8) + ((function&1) \
+ * 0x4)) : (0x1978 + (function * 0x4)))
#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
/**
@@ -211,6 +376,9 @@
#define TCP_IPV4_HASH_TYPE 2
#define IPV6_HASH_TYPE 3
#define TCP_IPV6_HASH_TYPE 4
+#define VLAN_PRI_HASH_TYPE 5
+#define E1HOV_PRI_HASH_TYPE 6
+#define DSCP_HASH_TYPE 7
/* Ethernet Ring parameters */
@@ -218,30 +386,26 @@
#define FIRST_BD_IN_PKT 0
#define PARSE_BD_INDEX 1
#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
-
+#define U_ETH_NUM_OF_SGES_TO_FETCH 8
+#define U_ETH_MAX_SGES_FOR_PACKET 3
/* Rx ring params */
-#define U_ETH_LOCAL_BD_RING_SIZE 16
-#define U_ETH_LOCAL_SGE_RING_SIZE 12
+#define U_ETH_LOCAL_BD_RING_SIZE 8
+#define U_ETH_LOCAL_SGE_RING_SIZE 10
#define U_ETH_SGL_SIZE 8
-#define U_ETH_BDS_PER_PAGE_MASK \
- ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
-#define U_ETH_CQE_PER_PAGE_MASK \
- ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
-#define U_ETH_SGES_PER_PAGE_MASK \
- ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
-
#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
(0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
-
-#define TU_ETH_CQES_PER_PAGE \
- (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
+#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
+#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
+#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
+#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
+
#define U_ETH_UNDEFINED_Q 0xFF
/* values of command IDs in the ramrod message */
@@ -266,8 +430,8 @@
#define T_ETH_CRC32_HASH_SEED 0x00000000
/* Maximal L2 clients supported */
-#define ETH_MAX_RX_CLIENTS_E1 19
-#define ETH_MAX_RX_CLIENTS_E1H 25
+#define ETH_MAX_RX_CLIENTS_E1 18
+#define ETH_MAX_RX_CLIENTS_E1H 26
/* Maximal aggregation queues supported */
#define ETH_MAX_AGGREGATION_QUEUES_E1 32
@@ -276,6 +440,9 @@
/* ETH RSS modes */
#define ETH_RSS_MODE_DISABLED 0
#define ETH_RSS_MODE_REGULAR 1
+#define ETH_RSS_MODE_VLAN_PRI 2
+#define ETH_RSS_MODE_E1HOV_PRI 3
+#define ETH_RSS_MODE_IP_DSCP 4
/**
@@ -332,12 +499,14 @@
#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
+#define HC_INDEX_DEF_C_ETH_FCOE_CQ_CONS 6
#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
-
+#define HC_INDEX_DEF_U_ETH_FCOE_RX_CQ_CONS 4
+#define HC_INDEX_DEF_U_ETH_FCOE_RX_BD_CONS 5
/* used by the driver to get the SB offset */
#define USTORM_ID 0
diff --git a/drivers/net/bnx2x_fw_file_hdr.h b/drivers/net/bnx2x_fw_file_hdr.h
new file mode 100644
index 0000000..3f5ee5d
--- /dev/null
+++ b/drivers/net/bnx2x_fw_file_hdr.h
@@ -0,0 +1,37 @@
+/* bnx2x_fw_file_hdr.h: FW binary file header structure.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Maintained by: Eilon Greenstein <eilong@broadcom.com>
+ * Written by: Vladislav Zolotarov <vladz@broadcom.com>
+ * Based on the original idea of John Wright <john.wright@hp.com>.
+ */
+
+#ifndef BNX2X_INIT_FILE_HDR_H
+#define BNX2X_INIT_FILE_HDR_H
+
+struct bnx2x_fw_file_section {
+ __be32 len;
+ __be32 offset;
+};
+
+struct bnx2x_fw_file_hdr {
+ struct bnx2x_fw_file_section init_ops;
+ struct bnx2x_fw_file_section init_ops_offsets;
+ struct bnx2x_fw_file_section init_data;
+ struct bnx2x_fw_file_section tsem_int_table_data;
+ struct bnx2x_fw_file_section tsem_pram_data;
+ struct bnx2x_fw_file_section usem_int_table_data;
+ struct bnx2x_fw_file_section usem_pram_data;
+ struct bnx2x_fw_file_section csem_int_table_data;
+ struct bnx2x_fw_file_section csem_pram_data;
+ struct bnx2x_fw_file_section xsem_int_table_data;
+ struct bnx2x_fw_file_section xsem_pram_data;
+ struct bnx2x_fw_file_section fw_version;
+};
+
+#endif /* BNX2X_INIT_FILE_HDR_H */
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
index a7fd1ba..8e2261f 100644
--- a/drivers/net/bnx2x_hsi.h
+++ b/drivers/net/bnx2x_hsi.h
@@ -91,6 +91,21 @@ struct shared_hw_cfg { /* NVRAM Offset */
#define SHARED_HW_CFG_HIDE_PORT1 0x00002000
+ /* The fan failure mechanism is usually related to the PHY type
+ since the power consumption of the board is determined by the PHY.
+ Currently, fan is required for most designs with SFX7101, BCM8727
+ and BCM8481. If a fan is not required for a board which uses one
+ of those PHYs, this field should be set to "Disabled". If a fan is
+ required for a different PHY type, this option should be set to
+ "Enabled".
+ The fan failure indication is expected on
+ SPIO5 */
+#define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
+#define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
+#define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
+#define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
+#define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
+
u32 power_dissipated; /* 0x11c */
#define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
#define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
@@ -643,6 +658,8 @@ struct drv_func_mb {
#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
+#define DRV_MSG_CODE_DCC_OK 0x30000000
+#define DRV_MSG_CODE_DCC_FAILURE 0x31000000
#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
@@ -677,6 +694,7 @@ struct drv_func_mb {
#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
+#define FW_MSG_CODE_DCC_DONE 0x30100000
#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
#define FW_MSG_CODE_DIAG_REFUSE 0x50200000
#define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
@@ -727,6 +745,14 @@ struct drv_func_mb {
u32 drv_status;
#define DRV_STATUS_PMF 0x00000001
+#define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
+#define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
+#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
+#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
+#define DRV_STATUS_DCC_RESERVED1 0x00000800
+#define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
+#define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
+
u32 virt_mac_upper;
#define VIRT_MAC_SIGN_MASK 0xffff0000
#define VIRT_MAC_SIGNATURE 0x564d0000
@@ -763,10 +789,9 @@ struct shared_mf_cfg {
struct port_mf_cfg {
u32 dynamic_cfg; /* device control channel */
-#define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff
-#define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0
-#define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000
-#define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000
+#define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
+#define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
+#define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
u32 reserved[3];
@@ -870,6 +895,22 @@ struct shmem_region { /* SharedMem Offset (size) */
}; /* 0x6dc */
+struct shmem2_region {
+
+ u32 size;
+
+ u32 dcc_support;
+#define SHMEM_DCC_SUPPORT_NONE 0x00000000
+#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
+#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
+#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
+#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
+#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
+#define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE
+
+};
+
+
struct emac_stats {
u32 rx_stat_ifhcinoctets;
u32 rx_stat_ifhcinbadoctets;
@@ -1203,9 +1244,9 @@ struct host_func_stats {
};
-#define BCM_5710_FW_MAJOR_VERSION 4
-#define BCM_5710_FW_MINOR_VERSION 8
-#define BCM_5710_FW_REVISION_VERSION 53
+#define BCM_5710_FW_MAJOR_VERSION 5
+#define BCM_5710_FW_MINOR_VERSION 0
+#define BCM_5710_FW_REVISION_VERSION 21
#define BCM_5710_FW_ENGINEERING_VERSION 0
#define BCM_5710_FW_COMPILE_FLAGS 1
@@ -1255,6 +1296,22 @@ struct doorbell {
/*
+ * doorbell message sent to the chip
+ */
+struct doorbell_set_prod {
+#if defined(__BIG_ENDIAN)
+ u16 prod;
+ u8 zero_fill1;
+ struct doorbell_hdr header;
+#elif defined(__LITTLE_ENDIAN)
+ struct doorbell_hdr header;
+ u8 zero_fill1;
+ u16 prod;
+#endif
+};
+
+
+/*
* IGU driver acknowledgement register
*/
struct igu_ack_register {
@@ -1289,6 +1346,62 @@ struct igu_ack_register {
/*
+ * IGU driver acknowledgement register
+ */
+struct igu_backward_compatible {
+ u32 sb_id_and_flags;
+#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
+#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
+#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
+#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
+#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
+#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
+#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
+#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
+#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
+#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
+#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
+#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
+ u32 reserved_2;
+};
+
+
+/*
+ * IGU driver acknowledgement register
+ */
+struct igu_regular {
+ u32 sb_id_and_flags;
+#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
+#define IGU_REGULAR_SB_INDEX_SHIFT 0
+#define IGU_REGULAR_RESERVED0 (0x1<<20)
+#define IGU_REGULAR_RESERVED0_SHIFT 20
+#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
+#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
+#define IGU_REGULAR_BUPDATE (0x1<<24)
+#define IGU_REGULAR_BUPDATE_SHIFT 24
+#define IGU_REGULAR_ENABLE_INT (0x3<<25)
+#define IGU_REGULAR_ENABLE_INT_SHIFT 25
+#define IGU_REGULAR_RESERVED_1 (0x1<<27)
+#define IGU_REGULAR_RESERVED_1_SHIFT 27
+#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
+#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
+#define IGU_REGULAR_CLEANUP_SET (0x1<<30)
+#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
+#define IGU_REGULAR_BCLEANUP (0x1<<31)
+#define IGU_REGULAR_BCLEANUP_SHIFT 31
+ u32 reserved_2;
+};
+
+/*
+ * IGU driver acknowledgement register
+ */
+union igu_consprod_reg {
+ struct igu_regular regular;
+ struct igu_backward_compatible backward_compatible;
+};
+
+
+/*
* Parser parsing flags field
*/
struct parsing_flags {
@@ -1419,12 +1532,10 @@ struct ustorm_eth_st_context_config {
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
-#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
-#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
-#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
-#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
-#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
-#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3
+#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
+#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
u8 status_block_id;
u8 clientId;
u8 sb_index_numbers;
@@ -1447,12 +1558,10 @@ struct ustorm_eth_st_context_config {
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
-#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
-#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
-#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
-#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
-#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
-#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3
+#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
+#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
#endif
#if defined(__BIG_ENDIAN)
u16 bd_buff_size;
@@ -1472,11 +1581,36 @@ struct ustorm_eth_st_context_config {
u8 __local_bd_prod;
u8 __local_sge_prod;
#endif
- u32 reserved;
+#if defined(__BIG_ENDIAN)
+ u16 __sdm_bd_expected_counter;
+ u8 cstorm_agg_int;
+ u8 __expected_bds_on_ram;
+#elif defined(__LITTLE_ENDIAN)
+ u8 __expected_bds_on_ram;
+ u8 cstorm_agg_int;
+ u16 __sdm_bd_expected_counter;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 __ring_data_ram_addr;
+ u16 __hc_cstorm_ram_addr;
+#elif defined(__LITTLE_ENDIAN)
+ u16 __hc_cstorm_ram_addr;
+ u16 __ring_data_ram_addr;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 reserved1;
+ u8 max_sges_for_packet;
+ u16 __bd_ring_ram_addr;
+#elif defined(__LITTLE_ENDIAN)
+ u16 __bd_ring_ram_addr;
+ u8 max_sges_for_packet;
+ u8 reserved1;
+#endif
u32 bd_page_base_lo;
u32 bd_page_base_hi;
u32 sge_page_base_lo;
u32 sge_page_base_hi;
+ struct regpair reserved2;
};
/*
@@ -1499,8 +1633,8 @@ struct eth_rx_sge {
* Local BDs and SGEs rings (in ETH)
*/
struct eth_local_rx_rings {
- struct eth_rx_bd __local_bd_ring[16];
- struct eth_rx_sge __local_sge_ring[12];
+ struct eth_rx_bd __local_bd_ring[8];
+ struct eth_rx_sge __local_sge_ring[10];
};
/*
@@ -1592,13 +1726,13 @@ struct xstorm_eth_extra_ag_context_section {
*/
struct xstorm_eth_ag_context {
#if defined(__BIG_ENDIAN)
- u16 __bd_prod;
+ u16 agg_val1;
u8 __agg_vars1;
u8 __state;
#elif defined(__LITTLE_ENDIAN)
u8 __state;
u8 __agg_vars1;
- u16 __bd_prod;
+ u16 agg_val1;
#endif
#if defined(__BIG_ENDIAN)
u8 cdu_reserved;
@@ -1611,7 +1745,7 @@ struct xstorm_eth_ag_context {
u8 __agg_vars4;
u8 cdu_reserved;
#endif
- u32 __more_packets_to_send;
+ u32 __bd_prod;
#if defined(__BIG_ENDIAN)
u16 __agg_vars5;
u16 __agg_val4_th;
@@ -1877,8 +2011,8 @@ struct eth_tx_bd_flags {
#define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
-#define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
-#define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
+#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<2)
+#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 2
#define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
#define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
@@ -1894,7 +2028,7 @@ struct eth_tx_bd_flags {
/*
* The eth Tx Buffer Descriptor
*/
-struct eth_tx_bd {
+struct eth_tx_start_bd {
__le32 addr_lo;
__le32 addr_hi;
__le16 nbd;
@@ -1902,10 +2036,21 @@ struct eth_tx_bd {
__le16 vlan;
struct eth_tx_bd_flags bd_flags;
u8 general_data;
-#define ETH_TX_BD_HDR_NBDS (0x3F<<0)
-#define ETH_TX_BD_HDR_NBDS_SHIFT 0
-#define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
-#define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
+#define ETH_TX_START_BD_HDR_NBDS (0x3F<<0)
+#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
+#define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
+#define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
+};
+
+/*
+ * Tx regular BD structure
+ */
+struct eth_tx_bd {
+ u32 addr_lo;
+ u32 addr_hi;
+ u16 total_pkt_bytes;
+ u16 nbytes;
+ u8 reserved[4];
};
/*
@@ -1915,8 +2060,8 @@ struct eth_tx_parse_bd {
u8 global_data;
#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
-#define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
-#define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
+#define ETH_TX_PARSE_BD_UDP_CS_FLG (0x1<<4)
+#define ETH_TX_PARSE_BD_UDP_CS_FLG_SHIFT 4
#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
#define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
@@ -1941,10 +2086,10 @@ struct eth_tx_parse_bd {
#define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
#define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
u8 ip_hlen;
- s8 cs_offset;
+ s8 reserved;
__le16 total_hlen;
- __le16 lso_mss;
__le16 tcp_pseudo_csum;
+ __le16 lso_mss;
__le16 ip_id;
__le32 tcp_send_seq;
};
@@ -1953,15 +2098,16 @@ struct eth_tx_parse_bd {
* The last BD in the BD memory will hold a pointer to the next BD memory
*/
struct eth_tx_next_bd {
- u32 addr_lo;
- u32 addr_hi;
+ __le32 addr_lo;
+ __le32 addr_hi;
u8 reserved[8];
};
/*
- * union for 3 Bd types
+ * union for 4 Bd types
*/
union eth_tx_bd_types {
+ struct eth_tx_start_bd start_bd;
struct eth_tx_bd reg_bd;
struct eth_tx_parse_bd parse_bd;
struct eth_tx_next_bd next_bd;
@@ -1990,11 +2136,35 @@ struct xstorm_eth_st_context {
#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
u16 tx_bd_cons;
#endif
- u32 db_data_addr_lo;
- u32 db_data_addr_hi;
- u32 __pkt_cons;
- u32 __gso_next;
- u32 is_eth_conn_1b;
+ u32 __reserved1;
+ u32 __reserved2;
+#if defined(__BIG_ENDIAN)
+ u8 __ram_cache_index;
+ u8 __double_buffer_client;
+ u16 __pkt_cons;
+#elif defined(__LITTLE_ENDIAN)
+ u16 __pkt_cons;
+ u8 __double_buffer_client;
+ u8 __ram_cache_index;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 __statistics_address;
+ u16 __gso_next;
+#elif defined(__LITTLE_ENDIAN)
+ u16 __gso_next;
+ u16 __statistics_address;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 __local_tx_bd_cons;
+ u8 safc_group_num;
+ u8 safc_group_en;
+ u8 __is_eth_conn;
+#elif defined(__LITTLE_ENDIAN)
+ u8 __is_eth_conn;
+ u8 safc_group_en;
+ u8 safc_group_num;
+ u8 __local_tx_bd_cons;
+#endif
union eth_tx_bd_types __bds[13];
};
@@ -2059,9 +2229,9 @@ struct eth_tx_doorbell {
/*
- * ustorm status block
+ * cstorm default status block, generated by ustorm
*/
-struct ustorm_def_status_block {
+struct cstorm_def_status_block_u {
__le16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
__le16 status_block_index;
u8 func;
@@ -2070,9 +2240,9 @@ struct ustorm_def_status_block {
};
/*
- * cstorm status block
+ * cstorm default status block, generated by cstorm
*/
-struct cstorm_def_status_block {
+struct cstorm_def_status_block_c {
__le16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
__le16 status_block_index;
u8 func;
@@ -2107,17 +2277,17 @@ struct tstorm_def_status_block {
*/
struct host_def_status_block {
struct atten_def_status_block atten_status_block;
- struct ustorm_def_status_block u_def_status_block;
- struct cstorm_def_status_block c_def_status_block;
+ struct cstorm_def_status_block_u u_def_status_block;
+ struct cstorm_def_status_block_c c_def_status_block;
struct xstorm_def_status_block x_def_status_block;
struct tstorm_def_status_block t_def_status_block;
};
/*
- * ustorm status block
+ * cstorm status block, generated by ustorm
*/
-struct ustorm_status_block {
+struct cstorm_status_block_u {
__le16 index_values[HC_USTORM_SB_NUM_INDICES];
__le16 status_block_index;
u8 func;
@@ -2126,9 +2296,9 @@ struct ustorm_status_block {
};
/*
- * cstorm status block
+ * cstorm status block, generated by cstorm
*/
-struct cstorm_status_block {
+struct cstorm_status_block_c {
__le16 index_values[HC_CSTORM_SB_NUM_INDICES];
__le16 status_block_index;
u8 func;
@@ -2140,8 +2310,8 @@ struct cstorm_status_block {
* host status block
*/
struct host_status_block {
- struct ustorm_status_block u_status_block;
- struct cstorm_status_block c_status_block;
+ struct cstorm_status_block_u u_status_block;
+ struct cstorm_status_block_c c_status_block;
};
@@ -2157,15 +2327,6 @@ struct eth_client_setup_ramrod_data {
/*
- * L2 dynamic host coalescing init parameters
- */
-struct eth_dynamic_hc_config {
- u32 threshold[3];
- u8 hc_timeout[4];
-};
-
-
-/*
* regular eth FP CQE parameters struct
*/
struct eth_fast_path_rx_cqe {
@@ -2329,12 +2490,10 @@ struct eth_spe {
/*
- * doorbell data in host memory
+ * array of 13 bds as appears in the eth xstorm context
*/
-struct eth_tx_db_data {
- __le32 packets_prod;
- __le16 bds_prod;
- __le16 reserved;
+struct eth_tx_bds_array {
+ union eth_tx_bd_types bds[13];
};
@@ -2362,8 +2521,10 @@ struct tstorm_eth_function_common_config {
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
-#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
-#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11)
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11
#elif defined(__LITTLE_ENDIAN)
u16 config_flags;
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
@@ -2382,8 +2543,10 @@ struct tstorm_eth_function_common_config {
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
-#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
-#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11)
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11
u8 rss_result_mask;
u8 leading_client_id;
#endif
@@ -2391,11 +2554,38 @@ struct tstorm_eth_function_common_config {
};
/*
+ * RSS idirection table update configuration
+ */
+struct rss_update_config {
+#if defined(__BIG_ENDIAN)
+ u16 toe_rss_bitmap;
+ u16 flags;
+#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
+#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
+#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
+#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
+#define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
+#define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
+#elif defined(__LITTLE_ENDIAN)
+ u16 flags;
+#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
+#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
+#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
+#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
+#define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
+#define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
+ u16 toe_rss_bitmap;
+#endif
+ u32 reserved1;
+};
+
+/*
* parameters for eth update ramrod
*/
struct eth_update_ramrod_data {
struct tstorm_eth_function_common_config func_config;
u8 indirectionTable[128];
+ struct rss_update_config rss_config;
};
@@ -2440,8 +2630,9 @@ struct tstorm_cam_target_table_entry {
#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
- u8 client_id;
+ u8 reserved1;
u16 vlan_id;
+ u32 clients_bit_vector;
};
/*
@@ -2470,7 +2661,7 @@ struct mac_configuration_entry_e1h {
__le16 msb_mac_addr;
__le16 vlan_id;
__le16 e1hov_id;
- u8 client_id;
+ u8 reserved0;
u8 flags;
#define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
#define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
@@ -2478,8 +2669,9 @@ struct mac_configuration_entry_e1h {
#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
-#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
-#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
+#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1 (0x1F<<3)
+#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1_SHIFT 3
+ u32 clients_bit_vector;
};
/*
@@ -2504,13 +2696,13 @@ struct tstorm_eth_approximate_match_multicast_filtering {
*/
struct tstorm_eth_client_config {
#if defined(__BIG_ENDIAN)
- u8 max_sges_for_packet;
+ u8 reserved0;
u8 statistics_counter_id;
u16 mtu;
#elif defined(__LITTLE_ENDIAN)
u16 mtu;
u8 statistics_counter_id;
- u8 max_sges_for_packet;
+ u8 reserved0;
#endif
#if defined(__BIG_ENDIAN)
u16 drop_flags;
@@ -2522,8 +2714,8 @@ struct tstorm_eth_client_config {
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4
u16 config_flags;
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
@@ -2531,10 +2723,8 @@ struct tstorm_eth_client_config {
#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
-#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
-#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3
#elif defined(__LITTLE_ENDIAN)
u16 config_flags;
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
@@ -2543,10 +2733,8 @@ struct tstorm_eth_client_config {
#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
-#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
-#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3
u16 drop_flags;
#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
@@ -2556,8 +2744,8 @@ struct tstorm_eth_client_config {
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
-#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4
#endif
};
@@ -2680,7 +2868,6 @@ struct rate_shaping_vars_per_port {
u32 rs_threshold;
};
-
/*
* per-port fairness variables
*/
@@ -2690,7 +2877,6 @@ struct fairness_vars_per_port {
u32 fairness_timeout;
};
-
/*
* per-port SAFC variables
*/
@@ -2707,7 +2893,6 @@ struct safc_struct_per_port {
u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
};
-
/*
* Per-port congestion management variables
*/
@@ -2720,11 +2905,23 @@ struct cmng_struct_per_port {
/*
+ * Dynamic host coalescing init parameters
+ */
+struct dynamic_hc_config {
+ u32 threshold[3];
+ u8 shift_per_protocol[HC_USTORM_SB_NUM_INDICES];
+ u8 hc_timeout0[HC_USTORM_SB_NUM_INDICES];
+ u8 hc_timeout1[HC_USTORM_SB_NUM_INDICES];
+ u8 hc_timeout2[HC_USTORM_SB_NUM_INDICES];
+ u8 hc_timeout3[HC_USTORM_SB_NUM_INDICES];
+};
+
+
+/*
* Protocol-common statistics collected by the Xstorm (per client)
*/
struct xstorm_per_client_stats {
- struct regpair total_sent_bytes;
- __le32 total_sent_pkts;
+ __le32 reserved0;
__le32 unicast_pkts_sent;
struct regpair unicast_bytes_sent;
struct regpair multicast_bytes_sent;
@@ -2732,11 +2929,10 @@ struct xstorm_per_client_stats {
__le32 broadcast_pkts_sent;
struct regpair broadcast_bytes_sent;
__le16 stats_counter;
- __le16 reserved0;
- __le32 reserved1;
+ __le16 reserved1;
+ __le32 reserved2;
};
-
/*
* Common statistics collected by the Xstorm (per port)
*/
@@ -2744,7 +2940,6 @@ struct xstorm_common_stats {
struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
};
-
/*
* Protocol-common statistics collected by the Tstorm (per port)
*/
@@ -2755,19 +2950,16 @@ struct tstorm_per_port_stats {
__le32 mac_discard;
};
-
/*
* Protocol-common statistics collected by the Tstorm (per client)
*/
struct tstorm_per_client_stats {
- struct regpair total_rcv_bytes;
struct regpair rcv_unicast_bytes;
struct regpair rcv_broadcast_bytes;
struct regpair rcv_multicast_bytes;
struct regpair rcv_error_bytes;
__le32 checksum_discard;
__le32 packets_too_big_discard;
- __le32 total_rcv_pkts;
__le32 rcv_unicast_pkts;
__le32 rcv_broadcast_pkts;
__le32 rcv_multicast_pkts;
@@ -2775,7 +2967,6 @@ struct tstorm_per_client_stats {
__le32 ttl0_discard;
__le16 stats_counter;
__le16 reserved0;
- __le32 reserved1;
};
/*
@@ -2878,6 +3069,15 @@ struct pram_fw_version {
/*
+ * The send queue element
+ */
+struct protocol_common_spe {
+ struct spe_hdr hdr;
+ struct regpair phy_address;
+};
+
+
+/*
* a single rate shaping counter. can be used as protocol or vnic counter
*/
struct rate_shaping_counter {
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 5362d5a..65b26cb 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -1,4 +1,5 @@
/* bnx2x_init.h: Broadcom Everest network driver.
+ * Structures and macroes needed during the initialization.
*
* Copyright (c) 2007-2009 Broadcom Corporation
*
@@ -8,29 +9,17 @@
*
* Maintained by: Eilon Greenstein <eilong@broadcom.com>
* Written by: Eliezer Tamir
+ * Modified by: Vladislav Zolotarov <vladz@broadcom.com>
*/
#ifndef BNX2X_INIT_H
#define BNX2X_INIT_H
-#define COMMON 0x1
-#define PORT0 0x2
-#define PORT1 0x4
-
-#define INIT_EMULATION 0x1
-#define INIT_FPGA 0x2
-#define INIT_ASIC 0x4
-#define INIT_HARDWARE 0x7
-
-#define TSTORM_INTMEM_ADDR TSEM_REG_FAST_MEMORY
-#define CSTORM_INTMEM_ADDR CSEM_REG_FAST_MEMORY
-#define XSTORM_INTMEM_ADDR XSEM_REG_FAST_MEMORY
-#define USTORM_INTMEM_ADDR USEM_REG_FAST_MEMORY
/* RAM0 size in bytes */
#define STORM_INTMEM_SIZE_E1 0x5800
#define STORM_INTMEM_SIZE_E1H 0x10000
-#define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1H(bp) ? STORM_INTMEM_SIZE_E1H : \
- STORM_INTMEM_SIZE_E1) / 4)
+#define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1(bp) ? STORM_INTMEM_SIZE_E1 : \
+ STORM_INTMEM_SIZE_E1H) / 4)
/* Init operation types and structures */
@@ -45,33 +34,74 @@
#define OP_WR_64 0x8 /* write 64 bit pattern */
#define OP_WB 0x9 /* copy a string using DMAE */
-/* Operation specific for E1 */
-#define OP_RD_E1 0xa /* read single register */
-#define OP_WR_E1 0xb /* write single register */
-#define OP_IW_E1 0xc /* write single register using mailbox */
-#define OP_SW_E1 0xd /* copy a string to the device */
-#define OP_SI_E1 0xe /* copy a string using mailbox */
-#define OP_ZR_E1 0xf /* clear memory */
-#define OP_ZP_E1 0x10 /* unzip then copy with DMAE */
-#define OP_WR_64_E1 0x11 /* write 64 bit pattern on E1 */
-#define OP_WB_E1 0x12 /* copy a string using DMAE */
-
-/* Operation specific for E1H */
-#define OP_RD_E1H 0x13 /* read single register */
-#define OP_WR_E1H 0x14 /* write single register */
-#define OP_IW_E1H 0x15 /* write single register using mailbox */
-#define OP_SW_E1H 0x16 /* copy a string to the device */
-#define OP_SI_E1H 0x17 /* copy a string using mailbox */
-#define OP_ZR_E1H 0x18 /* clear memory */
-#define OP_ZP_E1H 0x19 /* unzip then copy with DMAE */
-#define OP_WR_64_E1H 0x1a /* write 64 bit pattern on E1H */
-#define OP_WB_E1H 0x1b /* copy a string using DMAE */
-
/* FPGA and EMUL specific operations */
-#define OP_WR_EMUL_E1H 0x1c /* write single register on E1H Emul */
-#define OP_WR_EMUL 0x1d /* write single register on Emulation */
-#define OP_WR_FPGA 0x1e /* write single register on FPGA */
-#define OP_WR_ASIC 0x1f /* write single register on ASIC */
+#define OP_WR_EMUL 0xa /* write single register on Emulation */
+#define OP_WR_FPGA 0xb /* write single register on FPGA */
+#define OP_WR_ASIC 0xc /* write single register on ASIC */
+
+/* Init stages */
+/* Never reorder stages !!! */
+#define COMMON_STAGE 0
+#define PORT0_STAGE 1
+#define PORT1_STAGE 2
+#define FUNC0_STAGE 3
+#define FUNC1_STAGE 4
+#define FUNC2_STAGE 5
+#define FUNC3_STAGE 6
+#define FUNC4_STAGE 7
+#define FUNC5_STAGE 8
+#define FUNC6_STAGE 9
+#define FUNC7_STAGE 10
+#define STAGE_IDX_MAX 11
+
+#define STAGE_START 0
+#define STAGE_END 1
+
+
+/* Indices of blocks */
+#define PRS_BLOCK 0
+#define SRCH_BLOCK 1
+#define TSDM_BLOCK 2
+#define TCM_BLOCK 3
+#define BRB1_BLOCK 4
+#define TSEM_BLOCK 5
+#define PXPCS_BLOCK 6
+#define EMAC0_BLOCK 7
+#define EMAC1_BLOCK 8
+#define DBU_BLOCK 9
+#define MISC_BLOCK 10
+#define DBG_BLOCK 11
+#define NIG_BLOCK 12
+#define MCP_BLOCK 13
+#define UPB_BLOCK 14
+#define CSDM_BLOCK 15
+#define USDM_BLOCK 16
+#define CCM_BLOCK 17
+#define UCM_BLOCK 18
+#define USEM_BLOCK 19
+#define CSEM_BLOCK 20
+#define XPB_BLOCK 21
+#define DQ_BLOCK 22
+#define TIMERS_BLOCK 23
+#define XSDM_BLOCK 24
+#define QM_BLOCK 25
+#define PBF_BLOCK 26
+#define XCM_BLOCK 27
+#define XSEM_BLOCK 28
+#define CDU_BLOCK 29
+#define DMAE_BLOCK 30
+#define PXP_BLOCK 31
+#define CFC_BLOCK 32
+#define HC_BLOCK 33
+#define PXP2_BLOCK 34
+#define MISC_AEU_BLOCK 35
+#define PGLUE_B_BLOCK 36
+#define IGU_BLOCK 37
+
+
+/* Returns the index of start or end of a specific block stage in ops array*/
+#define BLOCK_OPS_IDX(block, stage, end) \
+ (2*(((block)*STAGE_IDX_MAX) + (stage)) + (end))
struct raw_op {
@@ -118,706 +148,5 @@ union init_op {
struct raw_op raw;
};
-#include "bnx2x_init_values.h"
-
-static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
-static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len);
-
-static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
- u32 len)
-{
- int i;
-
- for (i = 0; i < len; i++) {
- REG_WR(bp, addr + i*4, data[i]);
- if (!(i % 10000)) {
- touch_softlockup_watchdog();
- cpu_relax();
- }
- }
-}
-
-static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
- u16 len)
-{
- int i;
-
- for (i = 0; i < len; i++) {
- REG_WR_IND(bp, addr + i*4, data[i]);
- if (!(i % 10000)) {
- touch_softlockup_watchdog();
- cpu_relax();
- }
- }
-}
-
-static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
-{
- int offset = 0;
-
- if (bp->dmae_ready) {
- while (len > DMAE_LEN32_WR_MAX) {
- bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
- addr + offset, DMAE_LEN32_WR_MAX);
- offset += DMAE_LEN32_WR_MAX * 4;
- len -= DMAE_LEN32_WR_MAX;
- }
- bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
- addr + offset, len);
- } else
- bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
-}
-
-static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
-{
- u32 buf_len = (((len * 4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len * 4));
- u32 buf_len32 = buf_len / 4;
- int i;
-
- memset(bp->gunzip_buf, fill, buf_len);
-
- for (i = 0; i < len; i += buf_len32) {
- u32 cur_len = min(buf_len32, len - i);
-
- bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
- }
-}
-
-static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
- u32 len64)
-{
- u32 buf_len32 = FW_BUF_SIZE/4;
- u32 len = len64*2;
- u64 data64 = 0;
- int i;
-
- /* 64 bit value is in a blob: first low DWORD, then high DWORD */
- data64 = HILO_U64((*(data + 1)), (*data));
- len64 = min((u32)(FW_BUF_SIZE/8), len64);
- for (i = 0; i < len64; i++) {
- u64 *pdata = ((u64 *)(bp->gunzip_buf)) + i;
-
- *pdata = data64;
- }
-
- for (i = 0; i < len; i += buf_len32) {
- u32 cur_len = min(buf_len32, len - i);
-
- bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
- }
-}
-
-/*********************************************************
- There are different blobs for each PRAM section.
- In addition, each blob write operation is divided into a few operations
- in order to decrease the amount of phys. contiguous buffer needed.
- Thus, when we select a blob the address may be with some offset
- from the beginning of PRAM section.
- The same holds for the INT_TABLE sections.
-**********************************************************/
-#define IF_IS_INT_TABLE_ADDR(base, addr) \
- if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
-
-#define IF_IS_PRAM_ADDR(base, addr) \
- if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
-
-static const u32 *bnx2x_sel_blob(u32 addr, const u32 *data, int is_e1)
-{
- IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
- data = is_e1 ? tsem_int_table_data_e1 :
- tsem_int_table_data_e1h;
- else
- IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
- data = is_e1 ? csem_int_table_data_e1 :
- csem_int_table_data_e1h;
- else
- IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
- data = is_e1 ? usem_int_table_data_e1 :
- usem_int_table_data_e1h;
- else
- IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
- data = is_e1 ? xsem_int_table_data_e1 :
- xsem_int_table_data_e1h;
- else
- IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
- data = is_e1 ? tsem_pram_data_e1 : tsem_pram_data_e1h;
- else
- IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
- data = is_e1 ? csem_pram_data_e1 : csem_pram_data_e1h;
- else
- IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
- data = is_e1 ? usem_pram_data_e1 : usem_pram_data_e1h;
- else
- IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
- data = is_e1 ? xsem_pram_data_e1 : xsem_pram_data_e1h;
-
- return data;
-}
-
-static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
- u32 len, int gunzip, int is_e1, u32 blob_off)
-{
- int offset = 0;
-
- data = bnx2x_sel_blob(addr, data, is_e1) + blob_off;
-
- if (gunzip) {
- int rc;
-#ifdef __BIG_ENDIAN
- int i, size;
- u32 *temp;
-
- temp = kmalloc(len, GFP_KERNEL);
- size = (len / 4) + ((len % 4) ? 1 : 0);
- for (i = 0; i < size; i++)
- temp[i] = swab32(data[i]);
- data = temp;
-#endif
- rc = bnx2x_gunzip(bp, (u8 *)data, len);
- if (rc) {
- BNX2X_ERR("gunzip failed ! rc %d\n", rc);
-#ifdef __BIG_ENDIAN
- kfree(temp);
-#endif
- return;
- }
- len = bp->gunzip_outlen;
-#ifdef __BIG_ENDIAN
- kfree(temp);
- for (i = 0; i < len; i++)
- ((u32 *)bp->gunzip_buf)[i] =
- swab32(((u32 *)bp->gunzip_buf)[i]);
-#endif
- } else {
- if ((len * 4) > FW_BUF_SIZE) {
- BNX2X_ERR("LARGE DMAE OPERATION ! "
- "addr 0x%x len 0x%x\n", addr, len*4);
- return;
- }
- memcpy(bp->gunzip_buf, data, len * 4);
- }
-
- if (bp->dmae_ready) {
- while (len > DMAE_LEN32_WR_MAX) {
- bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
- addr + offset, DMAE_LEN32_WR_MAX);
- offset += DMAE_LEN32_WR_MAX * 4;
- len -= DMAE_LEN32_WR_MAX;
- }
- bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
- addr + offset, len);
- } else
- bnx2x_init_ind_wr(bp, addr, bp->gunzip_buf, len);
-}
-
-static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
-{
- int is_e1 = CHIP_IS_E1(bp);
- int is_e1h = CHIP_IS_E1H(bp);
- int is_emul_e1h = (CHIP_REV_IS_EMUL(bp) && is_e1h);
- int hw_wr, i;
- union init_op *op;
- u32 op_type, addr, len;
- const u32 *data, *data_base;
-
- if (CHIP_REV_IS_FPGA(bp))
- hw_wr = OP_WR_FPGA;
- else if (CHIP_REV_IS_EMUL(bp))
- hw_wr = OP_WR_EMUL;
- else
- hw_wr = OP_WR_ASIC;
-
- if (is_e1)
- data_base = init_data_e1;
- else /* CHIP_IS_E1H(bp) */
- data_base = init_data_e1h;
-
- for (i = op_start; i < op_end; i++) {
-
- op = (union init_op *)&(init_ops[i]);
-
- op_type = op->str_wr.op;
- addr = op->str_wr.offset;
- len = op->str_wr.data_len;
- data = data_base + op->str_wr.data_off;
-
- /* careful! it must be in order */
- if (unlikely(op_type > OP_WB)) {
-
- /* If E1 only */
- if (op_type <= OP_WB_E1) {
- if (is_e1)
- op_type -= (OP_RD_E1 - OP_RD);
-
- /* If E1H only */
- } else if (op_type <= OP_WB_E1H) {
- if (is_e1h)
- op_type -= (OP_RD_E1H - OP_RD);
- }
-
- /* HW/EMUL specific */
- if (op_type == hw_wr)
- op_type = OP_WR;
-
- /* EMUL on E1H is special */
- if ((op_type == OP_WR_EMUL_E1H) && is_emul_e1h)
- op_type = OP_WR;
- }
-
- switch (op_type) {
- case OP_RD:
- REG_RD(bp, addr);
- break;
- case OP_WR:
- REG_WR(bp, addr, op->write.val);
- break;
- case OP_SW:
- bnx2x_init_str_wr(bp, addr, data, len);
- break;
- case OP_WB:
- bnx2x_init_wr_wb(bp, addr, data, len, 0, is_e1, 0);
- break;
- case OP_SI:
- bnx2x_init_ind_wr(bp, addr, data, len);
- break;
- case OP_ZR:
- bnx2x_init_fill(bp, addr, 0, op->zero.len);
- break;
- case OP_ZP:
- bnx2x_init_wr_wb(bp, addr, data, len, 1, is_e1,
- op->str_wr.data_off);
- break;
- case OP_WR_64:
- bnx2x_init_wr_64(bp, addr, data, len);
- break;
- default:
- /* happens whenever an op is of a diff HW */
-#if 0
- DP(NETIF_MSG_HW, "skipping init operation "
- "index %d[%d:%d]: type %d addr 0x%x "
- "len %d(0x%x)\n",
- i, op_start, op_end, op_type, addr, len, len);
-#endif
- break;
- }
- }
-}
-
-
-/****************************************************************************
-* PXP
-****************************************************************************/
-/*
- * This code configures the PCI read/write arbiter
- * which implements a weighted round robin
- * between the virtual queues in the chip.
- *
- * The values were derived for each PCI max payload and max request size.
- * since max payload and max request size are only known at run time,
- * this is done as a separate init stage.
- */
-
-#define NUM_WR_Q 13
-#define NUM_RD_Q 29
-#define MAX_RD_ORD 3
-#define MAX_WR_ORD 2
-
-/* configuration for one arbiter queue */
-struct arb_line {
- int l;
- int add;
- int ubound;
-};
-
-/* derived configuration for each read queue for each max request size */
-static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
-/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
- { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
- { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
- { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
- { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
-/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
- { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
-};
-
-/* derived configuration for each write queue for each max request size */
-static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
-/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
- { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
- { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
- { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
- { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
- { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
- { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
- { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
- { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
-/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
- { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
- { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
- { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
-};
-
-/* register addresses for read queues */
-static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
-/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
- PXP2_REG_RQ_BW_RD_UBOUND0},
- {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
- PXP2_REG_PSWRQ_BW_UB1},
- {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
- PXP2_REG_PSWRQ_BW_UB2},
- {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
- PXP2_REG_PSWRQ_BW_UB3},
- {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
- PXP2_REG_RQ_BW_RD_UBOUND4},
- {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
- PXP2_REG_RQ_BW_RD_UBOUND5},
- {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
- PXP2_REG_PSWRQ_BW_UB6},
- {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
- PXP2_REG_PSWRQ_BW_UB7},
- {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
- PXP2_REG_PSWRQ_BW_UB8},
-/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
- PXP2_REG_PSWRQ_BW_UB9},
- {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
- PXP2_REG_PSWRQ_BW_UB10},
- {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
- PXP2_REG_PSWRQ_BW_UB11},
- {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
- PXP2_REG_RQ_BW_RD_UBOUND12},
- {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
- PXP2_REG_RQ_BW_RD_UBOUND13},
- {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
- PXP2_REG_RQ_BW_RD_UBOUND14},
- {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
- PXP2_REG_RQ_BW_RD_UBOUND15},
- {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
- PXP2_REG_RQ_BW_RD_UBOUND16},
- {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
- PXP2_REG_RQ_BW_RD_UBOUND17},
- {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
- PXP2_REG_RQ_BW_RD_UBOUND18},
-/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
- PXP2_REG_RQ_BW_RD_UBOUND19},
- {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
- PXP2_REG_RQ_BW_RD_UBOUND20},
- {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
- PXP2_REG_RQ_BW_RD_UBOUND22},
- {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
- PXP2_REG_RQ_BW_RD_UBOUND23},
- {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
- PXP2_REG_RQ_BW_RD_UBOUND24},
- {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
- PXP2_REG_RQ_BW_RD_UBOUND25},
- {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
- PXP2_REG_RQ_BW_RD_UBOUND26},
- {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
- PXP2_REG_RQ_BW_RD_UBOUND27},
- {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
- PXP2_REG_PSWRQ_BW_UB28}
-};
-
-/* register addresses for write queues */
-static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
-/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
- PXP2_REG_PSWRQ_BW_UB1},
- {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
- PXP2_REG_PSWRQ_BW_UB2},
- {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
- PXP2_REG_PSWRQ_BW_UB3},
- {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
- PXP2_REG_PSWRQ_BW_UB6},
- {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
- PXP2_REG_PSWRQ_BW_UB7},
- {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
- PXP2_REG_PSWRQ_BW_UB8},
- {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
- PXP2_REG_PSWRQ_BW_UB9},
- {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
- PXP2_REG_PSWRQ_BW_UB10},
- {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
- PXP2_REG_PSWRQ_BW_UB11},
-/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
- PXP2_REG_PSWRQ_BW_UB28},
- {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
- PXP2_REG_RQ_BW_WR_UBOUND29},
- {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
- PXP2_REG_RQ_BW_WR_UBOUND30}
-};
-
-static void bnx2x_init_pxp(struct bnx2x *bp)
-{
- u16 devctl;
- int r_order, w_order;
- u32 val, i;
-
- pci_read_config_word(bp->pdev,
- bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
- DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
- w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
- if (bp->mrrs == -1)
- r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
- else {
- DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
- r_order = bp->mrrs;
- }
-
- if (r_order > MAX_RD_ORD) {
- DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
- r_order, MAX_RD_ORD);
- r_order = MAX_RD_ORD;
- }
- if (w_order > MAX_WR_ORD) {
- DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n",
- w_order, MAX_WR_ORD);
- w_order = MAX_WR_ORD;
- }
- if (CHIP_REV_IS_FPGA(bp)) {
- DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
- w_order = 0;
- }
- DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
-
- for (i = 0; i < NUM_RD_Q-1; i++) {
- REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
- REG_WR(bp, read_arb_addr[i].add,
- read_arb_data[i][r_order].add);
- REG_WR(bp, read_arb_addr[i].ubound,
- read_arb_data[i][r_order].ubound);
- }
-
- for (i = 0; i < NUM_WR_Q-1; i++) {
- if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
- (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
-
- REG_WR(bp, write_arb_addr[i].l,
- write_arb_data[i][w_order].l);
-
- REG_WR(bp, write_arb_addr[i].add,
- write_arb_data[i][w_order].add);
-
- REG_WR(bp, write_arb_addr[i].ubound,
- write_arb_data[i][w_order].ubound);
- } else {
-
- val = REG_RD(bp, write_arb_addr[i].l);
- REG_WR(bp, write_arb_addr[i].l,
- val | (write_arb_data[i][w_order].l << 10));
-
- val = REG_RD(bp, write_arb_addr[i].add);
- REG_WR(bp, write_arb_addr[i].add,
- val | (write_arb_data[i][w_order].add << 10));
-
- val = REG_RD(bp, write_arb_addr[i].ubound);
- REG_WR(bp, write_arb_addr[i].ubound,
- val | (write_arb_data[i][w_order].ubound << 7));
- }
- }
-
- val = write_arb_data[NUM_WR_Q-1][w_order].add;
- val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
- val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
- REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
-
- val = read_arb_data[NUM_RD_Q-1][r_order].add;
- val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
- val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
- REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
-
- REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
- REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
- REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
- REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
-
- if (r_order == MAX_RD_ORD)
- REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
-
- REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
-
- if (CHIP_IS_E1H(bp)) {
- val = ((w_order == 0) ? 2 : 3);
- REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
- REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
- REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
- REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
- REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
- REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
- REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
- REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
- REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
- REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
- REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
- }
-}
-
-
-/****************************************************************************
-* CDU
-****************************************************************************/
-
-#define CDU_REGION_NUMBER_XCM_AG 2
-#define CDU_REGION_NUMBER_UCM_AG 4
-
-/**
- * String-to-compress [31:8] = CID (all 24 bits)
- * String-to-compress [7:4] = Region
- * String-to-compress [3:0] = Type
- */
-#define CDU_VALID_DATA(_cid, _region, _type) \
- (((_cid) << 8) | (((_region) & 0xf) << 4) | (((_type) & 0xf)))
-#define CDU_CRC8(_cid, _region, _type) \
- calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)
-#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
- (0x80 | (CDU_CRC8(_cid, _region, _type) & 0x7f))
-#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \
- (0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7))
-#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
-
-/*****************************************************************************
- * Description:
- * Calculates crc 8 on a word value: polynomial 0-1-2-8
- * Code was translated from Verilog.
- ****************************************************************************/
-static u8 calc_crc8(u32 data, u8 crc)
-{
- u8 D[32];
- u8 NewCRC[8];
- u8 C[8];
- u8 crc_res;
- u8 i;
-
- /* split the data into 31 bits */
- for (i = 0; i < 32; i++) {
- D[i] = data & 1;
- data = data >> 1;
- }
-
- /* split the crc into 8 bits */
- for (i = 0; i < 8; i++) {
- C[i] = crc & 1;
- crc = crc >> 1;
- }
-
- NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
- D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
- C[6] ^ C[7];
- NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
- D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
- D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];
- NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
- D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
- C[0] ^ C[1] ^ C[4] ^ C[5];
- NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
- D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
- C[1] ^ C[2] ^ C[5] ^ C[6];
- NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
- D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
- C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
- NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
- D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
- C[3] ^ C[4] ^ C[7];
- NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
- D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
- C[5];
- NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
- D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
- C[6];
-
- crc_res = 0;
- for (i = 0; i < 8; i++)
- crc_res |= (NewCRC[i] << i);
-
- return crc_res;
-}
-
-/* registers addresses are not in order
- so these arrays help simplify the code */
-static const int cm_start[E1H_FUNC_MAX][9] = {
- {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START,
- XCM_FUNC0_START, TSEM_FUNC0_START, USEM_FUNC0_START, CSEM_FUNC0_START,
- XSEM_FUNC0_START},
- {MISC_FUNC1_START, TCM_FUNC1_START, UCM_FUNC1_START, CCM_FUNC1_START,
- XCM_FUNC1_START, TSEM_FUNC1_START, USEM_FUNC1_START, CSEM_FUNC1_START,
- XSEM_FUNC1_START},
- {MISC_FUNC2_START, TCM_FUNC2_START, UCM_FUNC2_START, CCM_FUNC2_START,
- XCM_FUNC2_START, TSEM_FUNC2_START, USEM_FUNC2_START, CSEM_FUNC2_START,
- XSEM_FUNC2_START},
- {MISC_FUNC3_START, TCM_FUNC3_START, UCM_FUNC3_START, CCM_FUNC3_START,
- XCM_FUNC3_START, TSEM_FUNC3_START, USEM_FUNC3_START, CSEM_FUNC3_START,
- XSEM_FUNC3_START},
- {MISC_FUNC4_START, TCM_FUNC4_START, UCM_FUNC4_START, CCM_FUNC4_START,
- XCM_FUNC4_START, TSEM_FUNC4_START, USEM_FUNC4_START, CSEM_FUNC4_START,
- XSEM_FUNC4_START},
- {MISC_FUNC5_START, TCM_FUNC5_START, UCM_FUNC5_START, CCM_FUNC5_START,
- XCM_FUNC5_START, TSEM_FUNC5_START, USEM_FUNC5_START, CSEM_FUNC5_START,
- XSEM_FUNC5_START},
- {MISC_FUNC6_START, TCM_FUNC6_START, UCM_FUNC6_START, CCM_FUNC6_START,
- XCM_FUNC6_START, TSEM_FUNC6_START, USEM_FUNC6_START, CSEM_FUNC6_START,
- XSEM_FUNC6_START},
- {MISC_FUNC7_START, TCM_FUNC7_START, UCM_FUNC7_START, CCM_FUNC7_START,
- XCM_FUNC7_START, TSEM_FUNC7_START, USEM_FUNC7_START, CSEM_FUNC7_START,
- XSEM_FUNC7_START}
-};
-
-static const int cm_end[E1H_FUNC_MAX][9] = {
- {MISC_FUNC0_END, TCM_FUNC0_END, UCM_FUNC0_END, CCM_FUNC0_END,
- XCM_FUNC0_END, TSEM_FUNC0_END, USEM_FUNC0_END, CSEM_FUNC0_END,
- XSEM_FUNC0_END},
- {MISC_FUNC1_END, TCM_FUNC1_END, UCM_FUNC1_END, CCM_FUNC1_END,
- XCM_FUNC1_END, TSEM_FUNC1_END, USEM_FUNC1_END, CSEM_FUNC1_END,
- XSEM_FUNC1_END},
- {MISC_FUNC2_END, TCM_FUNC2_END, UCM_FUNC2_END, CCM_FUNC2_END,
- XCM_FUNC2_END, TSEM_FUNC2_END, USEM_FUNC2_END, CSEM_FUNC2_END,
- XSEM_FUNC2_END},
- {MISC_FUNC3_END, TCM_FUNC3_END, UCM_FUNC3_END, CCM_FUNC3_END,
- XCM_FUNC3_END, TSEM_FUNC3_END, USEM_FUNC3_END, CSEM_FUNC3_END,
- XSEM_FUNC3_END},
- {MISC_FUNC4_END, TCM_FUNC4_END, UCM_FUNC4_END, CCM_FUNC4_END,
- XCM_FUNC4_END, TSEM_FUNC4_END, USEM_FUNC4_END, CSEM_FUNC4_END,
- XSEM_FUNC4_END},
- {MISC_FUNC5_END, TCM_FUNC5_END, UCM_FUNC5_END, CCM_FUNC5_END,
- XCM_FUNC5_END, TSEM_FUNC5_END, USEM_FUNC5_END, CSEM_FUNC5_END,
- XSEM_FUNC5_END},
- {MISC_FUNC6_END, TCM_FUNC6_END, UCM_FUNC6_END, CCM_FUNC6_END,
- XCM_FUNC6_END, TSEM_FUNC6_END, USEM_FUNC6_END, CSEM_FUNC6_END,
- XSEM_FUNC6_END},
- {MISC_FUNC7_END, TCM_FUNC7_END, UCM_FUNC7_END, CCM_FUNC7_END,
- XCM_FUNC7_END, TSEM_FUNC7_END, USEM_FUNC7_END, CSEM_FUNC7_END,
- XSEM_FUNC7_END},
-};
-
-static const int hc_limits[E1H_FUNC_MAX][2] = {
- {HC_FUNC0_START, HC_FUNC0_END},
- {HC_FUNC1_START, HC_FUNC1_END},
- {HC_FUNC2_START, HC_FUNC2_END},
- {HC_FUNC3_START, HC_FUNC3_END},
- {HC_FUNC4_START, HC_FUNC4_END},
- {HC_FUNC5_START, HC_FUNC5_END},
- {HC_FUNC6_START, HC_FUNC6_END},
- {HC_FUNC7_START, HC_FUNC7_END}
-};
-
#endif /* BNX2X_INIT_H */
diff --git a/drivers/net/bnx2x_init_ops.h b/drivers/net/bnx2x_init_ops.h
new file mode 100644
index 0000000..38b970a
--- /dev/null
+++ b/drivers/net/bnx2x_init_ops.h
@@ -0,0 +1,501 @@
+/* bnx2x_init_ops.h: Broadcom Everest network driver.
+ * Static functions needed during the initialization.
+ * This file is "included" in bnx2x_main.c.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Maintained by: Eilon Greenstein <eilong@broadcom.com>
+ * Written by: Vladislav Zolotarov <vladz@broadcom.com>
+ */
+
+#ifndef BNX2X_INIT_OPS_H
+#define BNX2X_INIT_OPS_H
+
+static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len);
+
+
+static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
+ u32 len)
+{
+ u32 i;
+
+ for (i = 0; i < len; i++)
+ REG_WR(bp, addr + i*4, data[i]);
+}
+
+static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
+ u32 len)
+{
+ u32 i;
+
+ for (i = 0; i < len; i++)
+ REG_WR_IND(bp, addr + i*4, data[i]);
+}
+
+static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
+{
+ if (bp->dmae_ready)
+ bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
+ else
+ bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
+}
+
+static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
+{
+ u32 buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
+ u32 buf_len32 = buf_len/4;
+ u32 i;
+
+ memset(GUNZIP_BUF(bp), (u8)fill, buf_len);
+
+ for (i = 0; i < len; i += buf_len32) {
+ u32 cur_len = min(buf_len32, len - i);
+
+ bnx2x_write_big_buf(bp, addr + i*4, cur_len);
+ }
+}
+
+static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
+ u32 len64)
+{
+ u32 buf_len32 = FW_BUF_SIZE/4;
+ u32 len = len64*2;
+ u64 data64 = 0;
+ u32 i;
+
+ /* 64 bit value is in a blob: first low DWORD, then high DWORD */
+ data64 = HILO_U64((*(data + 1)), (*data));
+
+ len64 = min((u32)(FW_BUF_SIZE/8), len64);
+ for (i = 0; i < len64; i++) {
+ u64 *pdata = ((u64 *)(GUNZIP_BUF(bp))) + i;
+
+ *pdata = data64;
+ }
+
+ for (i = 0; i < len; i += buf_len32) {
+ u32 cur_len = min(buf_len32, len - i);
+
+ bnx2x_write_big_buf(bp, addr + i*4, cur_len);
+ }
+}
+
+/*********************************************************
+ There are different blobs for each PRAM section.
+ In addition, each blob write operation is divided into a few operations
+ in order to decrease the amount of phys. contiguous buffer needed.
+ Thus, when we select a blob the address may be with some offset
+ from the beginning of PRAM section.
+ The same holds for the INT_TABLE sections.
+**********************************************************/
+#define IF_IS_INT_TABLE_ADDR(base, addr) \
+ if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
+
+#define IF_IS_PRAM_ADDR(base, addr) \
+ if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
+
+static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr, const u8 *data)
+{
+ IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
+ data = INIT_TSEM_INT_TABLE_DATA(bp);
+ else
+ IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
+ data = INIT_CSEM_INT_TABLE_DATA(bp);
+ else
+ IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
+ data = INIT_USEM_INT_TABLE_DATA(bp);
+ else
+ IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
+ data = INIT_XSEM_INT_TABLE_DATA(bp);
+ else
+ IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
+ data = INIT_TSEM_PRAM_DATA(bp);
+ else
+ IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
+ data = INIT_CSEM_PRAM_DATA(bp);
+ else
+ IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
+ data = INIT_USEM_PRAM_DATA(bp);
+ else
+ IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
+ data = INIT_XSEM_PRAM_DATA(bp);
+
+ return data;
+}
+
+static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len)
+{
+ if (bp->dmae_ready)
+ bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
+ else
+ bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
+}
+
+static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
+ u32 len)
+{
+ data = (const u32 *)bnx2x_sel_blob(bp, addr, (const u8 *)data);
+
+ if (bp->dmae_ready)
+ VIRT_WR_DMAE_LEN(bp, data, addr, len);
+ else
+ bnx2x_init_ind_wr(bp, addr, data, len);
+}
+
+static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len, u32 blob_off)
+{
+ const u8 *data = NULL;
+ int rc;
+ u32 i;
+
+ data = bnx2x_sel_blob(bp, addr, data) + blob_off*4;
+
+ rc = bnx2x_gunzip(bp, data, len);
+ if (rc)
+ return;
+
+ /* gunzip_outlen is in dwords */
+ len = GUNZIP_OUTLEN(bp);
+ for (i = 0; i < len; i++)
+ ((u32 *)GUNZIP_BUF(bp))[i] =
+ cpu_to_le32(((u32 *)GUNZIP_BUF(bp))[i]);
+
+ bnx2x_write_big_buf_wb(bp, addr, len);
+}
+
+static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage)
+{
+ u16 op_start =
+ INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, STAGE_START)];
+ u16 op_end =
+ INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, STAGE_END)];
+ union init_op *op;
+ int hw_wr;
+ u32 i, op_type, addr, len;
+ const u32 *data, *data_base;
+
+ /* If empty block */
+ if (op_start == op_end)
+ return;
+
+ if (CHIP_REV_IS_FPGA(bp))
+ hw_wr = OP_WR_FPGA;
+ else if (CHIP_REV_IS_EMUL(bp))
+ hw_wr = OP_WR_EMUL;
+ else
+ hw_wr = OP_WR_ASIC;
+
+ data_base = INIT_DATA(bp);
+
+ for (i = op_start; i < op_end; i++) {
+
+ op = (union init_op *)&(INIT_OPS(bp)[i]);
+
+ op_type = op->str_wr.op;
+ addr = op->str_wr.offset;
+ len = op->str_wr.data_len;
+ data = data_base + op->str_wr.data_off;
+
+ /* HW/EMUL specific */
+ if ((op_type > OP_WB) && (op_type == hw_wr))
+ op_type = OP_WR;
+
+ switch (op_type) {
+ case OP_RD:
+ REG_RD(bp, addr);
+ break;
+ case OP_WR:
+ REG_WR(bp, addr, op->write.val);
+ break;
+ case OP_SW:
+ bnx2x_init_str_wr(bp, addr, data, len);
+ break;
+ case OP_WB:
+ bnx2x_init_wr_wb(bp, addr, data, len);
+ break;
+ case OP_SI:
+ bnx2x_init_ind_wr(bp, addr, data, len);
+ break;
+ case OP_ZR:
+ bnx2x_init_fill(bp, addr, 0, op->zero.len);
+ break;
+ case OP_ZP:
+ bnx2x_init_wr_zp(bp, addr, len,
+ op->str_wr.data_off);
+ break;
+ case OP_WR_64:
+ bnx2x_init_wr_64(bp, addr, data, len);
+ break;
+ default:
+ /* happens whenever an op is of a diff HW */
+ break;
+ }
+ }
+}
+
+
+/****************************************************************************
+* PXP Arbiter
+****************************************************************************/
+/*
+ * This code configures the PCI read/write arbiter
+ * which implements a weighted round robin
+ * between the virtual queues in the chip.
+ *
+ * The values were derived for each PCI max payload and max request size.
+ * since max payload and max request size are only known at run time,
+ * this is done as a separate init stage.
+ */
+
+#define NUM_WR_Q 13
+#define NUM_RD_Q 29
+#define MAX_RD_ORD 3
+#define MAX_WR_ORD 2
+
+/* configuration for one arbiter queue */
+struct arb_line {
+ int l;
+ int add;
+ int ubound;
+};
+
+/* derived configuration for each read queue for each max request size */
+static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
+/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
+ { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
+ { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
+ { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
+ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
+/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
+ { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
+};
+
+/* derived configuration for each write queue for each max request size */
+static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
+/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
+ { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
+ { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
+ { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
+ { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
+ { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
+ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
+ { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
+ { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
+/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
+ { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
+ { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
+ { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
+};
+
+/* register addresses for read queues */
+static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
+/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
+ PXP2_REG_RQ_BW_RD_UBOUND0},
+ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
+ PXP2_REG_PSWRQ_BW_UB1},
+ {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
+ PXP2_REG_PSWRQ_BW_UB2},
+ {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
+ PXP2_REG_PSWRQ_BW_UB3},
+ {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
+ PXP2_REG_RQ_BW_RD_UBOUND4},
+ {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
+ PXP2_REG_RQ_BW_RD_UBOUND5},
+ {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
+ PXP2_REG_PSWRQ_BW_UB6},
+ {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
+ PXP2_REG_PSWRQ_BW_UB7},
+ {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
+ PXP2_REG_PSWRQ_BW_UB8},
+/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
+ PXP2_REG_PSWRQ_BW_UB9},
+ {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
+ PXP2_REG_PSWRQ_BW_UB10},
+ {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
+ PXP2_REG_PSWRQ_BW_UB11},
+ {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
+ PXP2_REG_RQ_BW_RD_UBOUND12},
+ {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
+ PXP2_REG_RQ_BW_RD_UBOUND13},
+ {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
+ PXP2_REG_RQ_BW_RD_UBOUND14},
+ {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
+ PXP2_REG_RQ_BW_RD_UBOUND15},
+ {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
+ PXP2_REG_RQ_BW_RD_UBOUND16},
+ {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
+ PXP2_REG_RQ_BW_RD_UBOUND17},
+ {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
+ PXP2_REG_RQ_BW_RD_UBOUND18},
+/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
+ PXP2_REG_RQ_BW_RD_UBOUND19},
+ {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
+ PXP2_REG_RQ_BW_RD_UBOUND20},
+ {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
+ PXP2_REG_RQ_BW_RD_UBOUND22},
+ {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
+ PXP2_REG_RQ_BW_RD_UBOUND23},
+ {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
+ PXP2_REG_RQ_BW_RD_UBOUND24},
+ {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
+ PXP2_REG_RQ_BW_RD_UBOUND25},
+ {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
+ PXP2_REG_RQ_BW_RD_UBOUND26},
+ {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
+ PXP2_REG_RQ_BW_RD_UBOUND27},
+ {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
+ PXP2_REG_PSWRQ_BW_UB28}
+};
+
+/* register addresses for write queues */
+static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
+/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
+ PXP2_REG_PSWRQ_BW_UB1},
+ {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
+ PXP2_REG_PSWRQ_BW_UB2},
+ {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
+ PXP2_REG_PSWRQ_BW_UB3},
+ {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
+ PXP2_REG_PSWRQ_BW_UB6},
+ {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
+ PXP2_REG_PSWRQ_BW_UB7},
+ {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
+ PXP2_REG_PSWRQ_BW_UB8},
+ {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
+ PXP2_REG_PSWRQ_BW_UB9},
+ {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
+ PXP2_REG_PSWRQ_BW_UB10},
+ {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
+ PXP2_REG_PSWRQ_BW_UB11},
+/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
+ PXP2_REG_PSWRQ_BW_UB28},
+ {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
+ PXP2_REG_RQ_BW_WR_UBOUND29},
+ {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
+ PXP2_REG_RQ_BW_WR_UBOUND30}
+};
+
+static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order, int w_order)
+{
+ u32 val, i;
+
+ if (r_order > MAX_RD_ORD) {
+ DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
+ r_order, MAX_RD_ORD);
+ r_order = MAX_RD_ORD;
+ }
+ if (w_order > MAX_WR_ORD) {
+ DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n",
+ w_order, MAX_WR_ORD);
+ w_order = MAX_WR_ORD;
+ }
+ if (CHIP_REV_IS_FPGA(bp)) {
+ DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
+ w_order = 0;
+ }
+ DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
+
+ for (i = 0; i < NUM_RD_Q-1; i++) {
+ REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
+ REG_WR(bp, read_arb_addr[i].add,
+ read_arb_data[i][r_order].add);
+ REG_WR(bp, read_arb_addr[i].ubound,
+ read_arb_data[i][r_order].ubound);
+ }
+
+ for (i = 0; i < NUM_WR_Q-1; i++) {
+ if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
+ (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
+
+ REG_WR(bp, write_arb_addr[i].l,
+ write_arb_data[i][w_order].l);
+
+ REG_WR(bp, write_arb_addr[i].add,
+ write_arb_data[i][w_order].add);
+
+ REG_WR(bp, write_arb_addr[i].ubound,
+ write_arb_data[i][w_order].ubound);
+ } else {
+
+ val = REG_RD(bp, write_arb_addr[i].l);
+ REG_WR(bp, write_arb_addr[i].l,
+ val | (write_arb_data[i][w_order].l << 10));
+
+ val = REG_RD(bp, write_arb_addr[i].add);
+ REG_WR(bp, write_arb_addr[i].add,
+ val | (write_arb_data[i][w_order].add << 10));
+
+ val = REG_RD(bp, write_arb_addr[i].ubound);
+ REG_WR(bp, write_arb_addr[i].ubound,
+ val | (write_arb_data[i][w_order].ubound << 7));
+ }
+ }
+
+ val = write_arb_data[NUM_WR_Q-1][w_order].add;
+ val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
+ val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
+ REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
+
+ val = read_arb_data[NUM_RD_Q-1][r_order].add;
+ val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
+ val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
+ REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
+
+ REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
+ REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
+ REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
+ REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
+
+ if (r_order == MAX_RD_ORD)
+ REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
+
+ REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
+
+ if (CHIP_IS_E1H(bp)) {
+ /* MPS w_order optimal TH presently TH
+ * 128 0 0 2
+ * 256 1 1 3
+ * >=512 2 2 3
+ */
+ val = ((w_order == 0) ? 2 : 3);
+ REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
+ REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
+ REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
+ REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
+ REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
+ REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
+ REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
+ REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
+ REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
+ REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
+ REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
+ }
+}
+
+#endif /* BNX2X_INIT_OPS_H */
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index f33fad7..b3d4d94 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -37,6 +37,10 @@
/* Shortcut definitions */
/***********************************************************/
+#define NIG_LATCH_BC_ENABLE_MI_INT 0
+
+#define NIG_STATUS_EMAC0_MI_INT \
+ NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
#define NIG_STATUS_XGXS0_LINK10G \
NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
#define NIG_STATUS_XGXS0_LINK_STATUS \
@@ -178,6 +182,7 @@ static void bnx2x_set_serdes_access(struct link_params *params)
{
struct bnx2x *bp = params->bp;
u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
/* Set Clause 22 */
REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1);
REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
@@ -190,6 +195,7 @@ static void bnx2x_set_serdes_access(struct link_params *params)
static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags)
{
struct bnx2x *bp = params->bp;
+
if (phy_flags & PHY_XGXS_FLAG) {
REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
params->port*0x18, 0);
@@ -393,7 +399,8 @@ static u8 bnx2x_emac_enable(struct link_params *params,
/* enable access for bmac registers */
REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
- }
+ } else
+ REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
vars->mac_type = MAC_TYPE_EMAC;
return 0;
@@ -460,7 +467,6 @@ static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars,
REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
wb_data, 2);
-
/* set rx mtu */
wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
wb_data[1] = 0;
@@ -679,6 +685,7 @@ void bnx2x_link_status_update(struct link_params *params,
static void bnx2x_update_mng(struct link_params *params, u32 link_status)
{
struct bnx2x *bp = params->bp;
+
REG_WR(bp, params->shmem_base +
offsetof(struct shmem_region,
port_mb[params->port].link_status),
@@ -775,7 +782,6 @@ static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
line_speed);
return -EINVAL;
- break;
}
}
REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
@@ -795,6 +801,7 @@ static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
static u32 bnx2x_get_emac_base(struct bnx2x *bp, u32 ext_phy_type, u8 port)
{
u32 emac_base;
+
switch (ext_phy_type) {
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
@@ -900,7 +907,7 @@ u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL |
EMAC_MDIO_MODE_CLOCK_CNT));
val |= (EMAC_MDIO_MODE_CLAUSE_45 |
- (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
+ (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
udelay(40);
@@ -1017,8 +1024,8 @@ static u8 bnx2x_reset_unicore(struct link_params *params)
MDIO_COMBO_IEEE0_MII_CONTROL,
(mii_control |
MDIO_COMBO_IEEO_MII_CONTROL_RESET));
-
- bnx2x_set_serdes_access(params);
+ if (params->switch_cfg == SWITCH_CFG_1G)
+ bnx2x_set_serdes_access(params);
/* wait for the reset to self clear */
for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
@@ -1147,7 +1154,8 @@ static void bnx2x_set_parallel_detection(struct link_params *params,
}
static void bnx2x_set_autoneg(struct link_params *params,
- struct link_vars *vars)
+ struct link_vars *vars,
+ u8 enable_cl73)
{
struct bnx2x *bp = params->bp;
u16 reg_val;
@@ -1177,7 +1185,9 @@ static void bnx2x_set_autoneg(struct link_params *params,
params->phy_addr,
MDIO_REG_BANK_SERDES_DIGITAL,
MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
- reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
+ reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
+ reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
if (vars->line_speed == SPEED_AUTO_NEG)
reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
else
@@ -1209,8 +1219,51 @@ static void bnx2x_set_autoneg(struct link_params *params,
MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
reg_val);
- /* CL73 Autoneg Disabled */
- reg_val = 0;
+ if (enable_cl73) {
+ /* Enable Cl73 FSM status bits */
+ CL45_WR_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_CL73_USERB0,
+ MDIO_CL73_USERB0_CL73_UCTRL,
+ MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL);
+
+ /* Enable BAM Station Manager*/
+ CL45_WR_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_CL73_USERB0,
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1,
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
+
+ /* Merge CL73 and CL37 aneg resolution */
+ CL45_RD_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_CL73_USERB0,
+ MDIO_CL73_USERB0_CL73_BAM_CTRL3,
+ ®_val);
+
+ if (params->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
+ /* Set the CL73 AN speed */
+ CL45_RD_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_CL73_IEEEB1,
+ MDIO_CL73_IEEEB1_AN_ADV2,
+ ®_val);
+
+ CL45_WR_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_CL73_IEEEB1,
+ MDIO_CL73_IEEEB1_AN_ADV2,
+ reg_val | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4);
+
+ }
+ /* CL73 Autoneg Enabled */
+ reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
+
+ } else /* CL73 Autoneg Disabled */
+ reg_val = 0;
CL45_WR_OVER_CL22(bp, params->port,
params->phy_addr,
@@ -1225,14 +1278,14 @@ static void bnx2x_program_serdes(struct link_params *params,
struct bnx2x *bp = params->bp;
u16 reg_val;
- /* program duplex, disable autoneg */
-
+ /* program duplex, disable autoneg and sgmii*/
CL45_RD_OVER_CL22(bp, params->port,
params->phy_addr,
MDIO_REG_BANK_COMBO_IEEE0,
MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
- MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
+ MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
+ MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
if (params->req_duplex == DUPLEX_FULL)
reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
CL45_WR_OVER_CL22(bp, params->port,
@@ -1293,10 +1346,10 @@ static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
CL45_WR_OVER_CL22(bp, params->port,
params->phy_addr,
MDIO_REG_BANK_OVER_1G,
- MDIO_OVER_1G_UP3, 0);
+ MDIO_OVER_1G_UP3, 0x400);
}
-static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc)
+static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc)
{
*ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
/* resolve pause mode and advertisement
@@ -1330,7 +1383,7 @@ static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc)
}
static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
- u32 ieee_fc)
+ u16 ieee_fc)
{
struct bnx2x *bp = params->bp;
/* for AN, we are always publishing full duplex */
@@ -1338,31 +1391,49 @@ static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
CL45_WR_OVER_CL22(bp, params->port,
params->phy_addr,
MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV, (u16)ieee_fc);
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
}
-static void bnx2x_restart_autoneg(struct link_params *params)
+static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
{
struct bnx2x *bp = params->bp;
u16 mii_control;
+
DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
/* Enable and restart BAM/CL37 aneg */
- CL45_RD_OVER_CL22(bp, params->port,
- params->phy_addr,
- MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_MII_CONTROL,
- &mii_control);
- DP(NETIF_MSG_LINK,
- "bnx2x_restart_autoneg mii_control before = 0x%x\n",
- mii_control);
- CL45_WR_OVER_CL22(bp, params->port,
- params->phy_addr,
- MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_MII_CONTROL,
- (mii_control |
- MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
- MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
+ if (enable_cl73) {
+ CL45_RD_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_CL73_IEEEB0,
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+ &mii_control);
+
+ CL45_WR_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_CL73_IEEEB0,
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+ (mii_control |
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
+ } else {
+
+ CL45_RD_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_COMBO_IEEE0,
+ MDIO_COMBO_IEEE0_MII_CONTROL,
+ &mii_control);
+ DP(NETIF_MSG_LINK,
+ "bnx2x_restart_autoneg mii_control before = 0x%x\n",
+ mii_control);
+ CL45_WR_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_COMBO_IEEE0,
+ MDIO_COMBO_IEEE0_MII_CONTROL,
+ (mii_control |
+ MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
+ MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
+ }
}
static void bnx2x_initialize_sgmii_process(struct link_params *params,
@@ -1434,7 +1505,7 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params,
} else { /* AN mode */
/* enable and restart AN */
- bnx2x_restart_autoneg(params);
+ bnx2x_restart_autoneg(params, 0);
}
}
@@ -1466,22 +1537,19 @@ static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
}
}
-static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
+static u8 bnx2x_ext_phy_resolve_fc(struct link_params *params,
struct link_vars *vars)
{
struct bnx2x *bp = params->bp;
u8 ext_phy_addr;
- u16 ld_pause; /* local */
- u16 lp_pause; /* link partner */
- u16 an_complete; /* AN complete */
+ u16 ld_pause; /* local */
+ u16 lp_pause; /* link partner */
+ u16 an_complete; /* AN complete */
u16 pause_result;
u8 ret = 0;
u32 ext_phy_type;
u8 port = params->port;
- ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
-
+ ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
/* read twice */
@@ -1576,7 +1644,7 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
bnx2x_pause_resolve(vars, pause_result);
} else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
- (bnx2x_ext_phy_resove_fc(params, vars))) {
+ (bnx2x_ext_phy_resolve_fc(params, vars))) {
return;
} else {
if (params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
@@ -1587,10 +1655,77 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
}
-
+static void bnx2x_check_fallback_to_cl37(struct link_params *params)
+{
+ struct bnx2x *bp = params->bp;
+ u16 rx_status, ustat_val, cl37_fsm_recieved;
+ DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
+ /* Step 1: Make sure signal is detected */
+ CL45_RD_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_RX0,
+ MDIO_RX0_RX_STATUS,
+ &rx_status);
+ if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
+ (MDIO_RX0_RX_STATUS_SIGDET)) {
+ DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
+ "rx_status(0x80b0) = 0x%x\n", rx_status);
+ CL45_WR_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_CL73_IEEEB0,
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
+ return;
+ }
+ /* Step 2: Check CL73 state machine */
+ CL45_RD_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_CL73_USERB0,
+ MDIO_CL73_USERB0_CL73_USTAT1,
+ &ustat_val);
+ if ((ustat_val &
+ (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
+ MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
+ (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
+ MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
+ DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
+ "ustat_val(0x8371) = 0x%x\n", ustat_val);
+ return;
+ }
+ /* Step 3: Check CL37 Message Pages received to indicate LP
+ supports only CL37 */
+ CL45_RD_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_REMOTE_PHY,
+ MDIO_REMOTE_PHY_MISC_RX_STATUS,
+ &cl37_fsm_recieved);
+ if ((cl37_fsm_recieved &
+ (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
+ MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
+ (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
+ MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
+ DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
+ "misc_rx_status(0x8330) = 0x%x\n",
+ cl37_fsm_recieved);
+ return;
+ }
+ /* The combined cl37/cl73 fsm state information indicating that we are
+ connected to a device which does not support cl73, but does support
+ cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
+ /* Disable CL73 */
+ CL45_WR_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_CL73_IEEEB0,
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+ 0);
+ /* Restart CL37 autoneg */
+ bnx2x_restart_autoneg(params, 0);
+ DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
+}
static u8 bnx2x_link_settings_status(struct link_params *params,
- struct link_vars *vars,
- u32 gp_status)
+ struct link_vars *vars,
+ u32 gp_status,
+ u8 ext_phy_link_up)
{
struct bnx2x *bp = params->bp;
u16 new_line_speed;
@@ -1651,7 +1786,7 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
"link speed unsupported gp_status 0x%x\n",
gp_status);
return -EINVAL;
- break;
+
case GP_STATUS_10G_KX4:
case GP_STATUS_10G_HIG:
case GP_STATUS_10G_CX4:
@@ -1688,14 +1823,23 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
DP(NETIF_MSG_LINK,
"link speed unsupported gp_status 0x%x\n",
gp_status);
- return -EINVAL;
- break;
+ return -EINVAL;
}
/* Upon link speed change set the NIG into drain mode.
Comes to deals with possible FIFO glitch due to clk change
when speed is decreased without link down indicator */
if (new_line_speed != vars->line_speed) {
+ if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) !=
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT &&
+ ext_phy_link_up) {
+ DP(NETIF_MSG_LINK, "Internal link speed %d is"
+ " different than the external"
+ " link speed %d\n", new_line_speed,
+ vars->line_speed);
+ vars->phy_link_up = 0;
+ return 0;
+ }
REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
+ params->port*4, 0);
msleep(1);
@@ -1709,9 +1853,7 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
(XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
(XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
- (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481))) {
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) {
vars->autoneg = AUTO_NEG_ENABLED;
if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
@@ -1742,6 +1884,13 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
vars->autoneg = AUTO_NEG_DISABLED;
vars->mac_type = MAC_TYPE_NONE;
+
+ if ((params->req_line_speed == SPEED_AUTO_NEG) &&
+ ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT))) {
+ /* Check signal is detected */
+ bnx2x_check_fallback_to_cl37(params);
+ }
}
DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x \n",
@@ -1860,9 +2009,8 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
{
struct bnx2x *bp = params->bp;
u32 ext_phy_type;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+
DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port);
ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
/* The PHY reset is controled by GPIO 1
@@ -1914,16 +2062,17 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_CTRL,
1<<15);
-
break;
+
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+ DP(NETIF_MSG_LINK, "XGXS 8072\n");
+
/* Unset Low Power Mode and SW reset */
/* Restore normal power mode*/
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_HIGH,
params->port);
- DP(NETIF_MSG_LINK, "XGXS 8072\n");
bnx2x_cl45_write(bp, params->port,
ext_phy_type,
ext_phy_addr,
@@ -1931,8 +2080,9 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
MDIO_PMA_REG_CTRL,
1<<15);
break;
+
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
- {
+ DP(NETIF_MSG_LINK, "XGXS 8073\n");
/* Restore normal power mode*/
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
@@ -1942,9 +2092,6 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_OUTPUT_HIGH,
params->port);
-
- DP(NETIF_MSG_LINK, "XGXS 8073\n");
- }
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
@@ -1961,7 +2108,6 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
-
/* Restore normal power mode*/
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_HIGH,
@@ -2000,20 +2146,18 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
break;
default:
- DP(NETIF_MSG_LINK,
- "BAD SerDes ext_phy_config 0x%x\n",
+ DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
params->ext_phy_config);
break;
}
}
}
-
static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
u32 shmem_base, u32 spirom_ver)
{
- DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x\n",
- (u16)(spirom_ver>>16), (u16)spirom_ver);
+ DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
+ (u16)(spirom_ver>>16), (u16)spirom_ver, port);
REG_WR(bp, shmem_base +
offsetof(struct shmem_region,
port_mb[port].ext_phy_fw_version),
@@ -2025,6 +2169,7 @@ static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port,
u32 shmem_base)
{
u16 fw_ver1, fw_ver2;
+
bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
MDIO_PMA_REG_ROM_VER1, &fw_ver1);
bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
@@ -2033,13 +2178,116 @@ static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port,
(u32)(fw_ver1<<16 | fw_ver2));
}
+
+static void bnx2x_save_8481_spirom_version(struct bnx2x *bp, u8 port,
+ u8 ext_phy_addr, u32 shmem_base)
+{
+ u16 val, fw_ver1, fw_ver2, cnt;
+ /* For the 32 bits registers in 8481, access via MDIO2ARM interface.*/
+ /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
+ bnx2x_cl45_write(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+ ext_phy_addr, MDIO_PMA_DEVAD,
+ 0xA819, 0x0014);
+ bnx2x_cl45_write(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ 0xA81A,
+ 0xc200);
+ bnx2x_cl45_write(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ 0xA81B,
+ 0x0000);
+ bnx2x_cl45_write(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ 0xA81C,
+ 0x0300);
+ bnx2x_cl45_write(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ 0xA817,
+ 0x0009);
+
+ for (cnt = 0; cnt < 100; cnt++) {
+ bnx2x_cl45_read(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ 0xA818,
+ &val);
+ if (val & 1)
+ break;
+ udelay(5);
+ }
+ if (cnt == 100) {
+ DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(1)\n");
+ bnx2x_save_spirom_version(bp, port,
+ shmem_base, 0);
+ return;
+ }
+
+
+ /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
+ bnx2x_cl45_write(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+ ext_phy_addr, MDIO_PMA_DEVAD,
+ 0xA819, 0x0000);
+ bnx2x_cl45_write(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+ ext_phy_addr, MDIO_PMA_DEVAD,
+ 0xA81A, 0xc200);
+ bnx2x_cl45_write(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+ ext_phy_addr, MDIO_PMA_DEVAD,
+ 0xA817, 0x000A);
+ for (cnt = 0; cnt < 100; cnt++) {
+ bnx2x_cl45_read(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ 0xA818,
+ &val);
+ if (val & 1)
+ break;
+ udelay(5);
+ }
+ if (cnt == 100) {
+ DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(2)\n");
+ bnx2x_save_spirom_version(bp, port,
+ shmem_base, 0);
+ return;
+ }
+
+ /* lower 16 bits of the register SPI_FW_STATUS */
+ bnx2x_cl45_read(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ 0xA81B,
+ &fw_ver1);
+ /* upper 16 bits of register SPI_FW_STATUS */
+ bnx2x_cl45_read(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ 0xA81C,
+ &fw_ver2);
+
+ bnx2x_save_spirom_version(bp, port,
+ shmem_base, (fw_ver2<<16) | fw_ver1);
+}
+
static void bnx2x_bcm8072_external_rom_boot(struct link_params *params)
{
struct bnx2x *bp = params->bp;
u8 port = params->port;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
/* Need to wait 200ms after reset */
@@ -2087,9 +2335,7 @@ static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
/* This is only required for 8073A1, version 102 only */
struct bnx2x *bp = params->bp;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u16 val;
/* Read 8073 HW revision*/
@@ -2120,9 +2366,7 @@ static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
{
struct bnx2x *bp = params->bp;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u16 val, cnt, cnt1 ;
bnx2x_cl45_read(bp, params->port,
@@ -2178,7 +2422,6 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
}
DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
return -EINVAL;
-
}
static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
@@ -2264,9 +2507,7 @@ static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
{
struct bnx2x *bp = params->bp;
u8 port = params->port;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
/* Need to wait 100ms after reset */
@@ -2322,6 +2563,7 @@ static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, u8 port,
u8 tx_en)
{
u16 val;
+
DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
tx_en, port);
/* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
@@ -2352,10 +2594,9 @@ static u8 bnx2x_8726_read_sfp_module_eeprom(struct link_params *params,
u16 val = 0;
u16 i;
u8 port = params->port;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
if (byte_cnt > 16) {
DP(NETIF_MSG_LINK, "Reading from eeprom is"
" is limited to 0xf\n");
@@ -2436,9 +2677,7 @@ static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params,
struct bnx2x *bp = params->bp;
u16 val, i;
u8 port = params->port;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
if (byte_cnt > 16) {
@@ -2569,6 +2808,7 @@ static u8 bnx2x_get_edc_mode(struct link_params *params,
case SFP_EEPROM_CON_TYPE_VAL_COPPER:
{
u8 copper_module_type;
+
/* Check if its active cable( includes SFP+ module)
of passive cable*/
if (bnx2x_read_sfp_module_eeprom(params,
@@ -2603,7 +2843,6 @@ static u8 bnx2x_get_edc_mode(struct link_params *params,
DP(NETIF_MSG_LINK, "Optic module detected\n");
check_limiting_mode = 1;
break;
-
default:
DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
val);
@@ -2691,9 +2930,7 @@ static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
{
struct bnx2x *bp = params->bp;
u8 port = params->port;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u16 cur_limiting_mode;
bnx2x_cl45_read(bp, port,
@@ -2759,9 +2996,7 @@ static u8 bnx2x_bcm8727_set_limiting_mode(struct link_params *params,
u8 port = params->port;
u16 phy_identifier;
u16 rom_ver2_val;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
bnx2x_cl45_read(bp, port,
PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
@@ -2865,9 +3100,7 @@ static u8 bnx2x_sfp_module_detection(struct link_params *params)
struct bnx2x *bp = params->bp;
u16 edc_mode;
u8 rc = 0;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
u32 val = REG_RD(bp, params->shmem_base +
offsetof(struct shmem_region, dev_info.
@@ -2936,6 +3169,7 @@ void bnx2x_handle_module_detect_int(struct link_params *params)
struct bnx2x *bp = params->bp;
u32 gpio_val;
u8 port = params->port;
+
/* Set valid module led off */
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
MISC_REGISTERS_GPIO_HIGH,
@@ -2957,9 +3191,8 @@ void bnx2x_handle_module_detect_int(struct link_params *params)
else
DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
} else {
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+
u32 ext_phy_type =
XGXS_EXT_PHY_TYPE(params->ext_phy_config);
u32 val = REG_RD(bp, params->shmem_base +
@@ -2983,9 +3216,7 @@ static void bnx2x_bcm807x_force_10G(struct link_params *params)
{
struct bnx2x *bp = params->bp;
u8 port = params->port;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
/* Force KR or KX */
@@ -3006,14 +3237,13 @@ static void bnx2x_bcm807x_force_10G(struct link_params *params)
MDIO_AN_REG_CTRL,
0x0000);
}
+
static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
{
struct bnx2x *bp = params->bp;
u8 port = params->port;
u16 val;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
bnx2x_cl45_read(bp, params->port,
@@ -3075,12 +3305,9 @@ static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
static void bnx2x_8073_set_pause_cl37(struct link_params *params,
struct link_vars *vars)
{
-
struct bnx2x *bp = params->bp;
u16 cl37_val;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
bnx2x_cl45_read(bp, params->port,
@@ -3123,9 +3350,7 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
{
struct bnx2x *bp = params->bp;
u16 val;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
/* read modify write pause advertizing */
@@ -3182,10 +3407,136 @@ static void bnx2x_set_preemphasis(struct link_params *params)
}
}
+
+static void bnx2x_8481_set_led4(struct link_params *params,
+ u32 ext_phy_type, u8 ext_phy_addr)
+{
+ struct bnx2x *bp = params->bp;
+
+ /* PHYC_CTL_LED_CTL */
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LINK_SIGNAL, 0xa482);
+
+ /* Unmask LED4 for 10G link */
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_SIGNAL_MASK, (1<<6));
+ /* 'Interrupt Mask' */
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ 0xFFFB, 0xFFFD);
+}
+static void bnx2x_8481_set_legacy_led_mode(struct link_params *params,
+ u32 ext_phy_type, u8 ext_phy_addr)
+{
+ struct bnx2x *bp = params->bp;
+
+ /* LED1 (10G Link): Disable LED1 when 10/100/1000 link */
+ /* LED2 (1G/100/10 Link): Enable LED2 when 10/100/1000 link) */
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_LEGACY_SHADOW,
+ (1<<15) | (0xd << 10) | (0xc<<4) | 0xe);
+}
+
+static void bnx2x_8481_set_10G_led_mode(struct link_params *params,
+ u32 ext_phy_type, u8 ext_phy_addr)
+{
+ struct bnx2x *bp = params->bp;
+ u16 val1;
+
+ /* LED1 (10G Link) */
+ /* Enable continuse based on source 7(10G-link) */
+ bnx2x_cl45_read(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ &val1);
+ /* Set bit 2 to 0, and bits [1:0] to 10 */
+ val1 &= ~((1<<0) | (1<<2)); /* Clear bits 0,2*/
+ val1 |= (1<<1); /* Set bit 1 */
+
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ val1);
+
+ /* Unmask LED1 for 10G link */
+ bnx2x_cl45_read(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED1_MASK,
+ &val1);
+ /* Set bit 2 to 0, and bits [1:0] to 10 */
+ val1 |= (1<<7);
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED1_MASK,
+ val1);
+
+ /* LED2 (1G/100/10G Link) */
+ /* Mask LED2 for 10G link */
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED2_MASK,
+ 0);
+
+ /* LED3 (10G/1G/100/10G Activity) */
+ bnx2x_cl45_read(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ &val1);
+ /* Enable blink based on source 4(Activity) */
+ val1 &= ~((1<<7) | (1<<8)); /* Clear bits 7,8 */
+ val1 |= (1<<6); /* Set only bit 6 */
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ val1);
+
+ bnx2x_cl45_read(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED3_MASK,
+ &val1);
+ val1 |= (1<<4); /* Unmask LED3 for 10G link */
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED3_MASK,
+ val1);
+}
+
+
static void bnx2x_init_internal_phy(struct link_params *params,
- struct link_vars *vars)
+ struct link_vars *vars,
+ u8 enable_cl73)
{
struct bnx2x *bp = params->bp;
+
if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
@@ -3198,7 +3549,7 @@ static void bnx2x_init_internal_phy(struct link_params *params,
DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
/* disable autoneg */
- bnx2x_set_autoneg(params, vars);
+ bnx2x_set_autoneg(params, vars, 0);
/* program speed and duplex */
bnx2x_program_serdes(params, vars);
@@ -3214,10 +3565,10 @@ static void bnx2x_init_internal_phy(struct link_params *params,
vars->ieee_fc);
/* enable autoneg */
- bnx2x_set_autoneg(params, vars);
+ bnx2x_set_autoneg(params, vars, enable_cl73);
/* enable and restart AN */
- bnx2x_restart_autoneg(params);
+ bnx2x_restart_autoneg(params, enable_cl73);
}
} else { /* SGMII mode */
@@ -3236,10 +3587,9 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
u16 ctrl = 0;
u16 val = 0;
u8 rc = 0;
+
if (vars->phy_flags & PHY_XGXS_FLAG) {
- ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
/* Make sure that the soft reset is off (expect for the 8072:
@@ -3534,14 +3884,12 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
bnx2x_8073_set_pause_cl37(params, vars);
if (ext_phy_type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072)
bnx2x_bcm8072_external_rom_boot(params);
- } else {
-
+ else
/* In case of 8073 with long xaui lines,
don't set the 8073 xaui low power*/
bnx2x_bcm8073_set_xaui_low_power_mode(params);
- }
bnx2x_cl45_read(bp, params->port,
ext_phy_type,
@@ -3606,10 +3954,8 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
ext_phy_addr,
MDIO_AN_DEVAD,
MDIO_AN_REG_ADV, val);
-
if (ext_phy_type ==
PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
-
bnx2x_cl45_read(bp, params->port,
ext_phy_type,
ext_phy_addr,
@@ -3943,20 +4289,112 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
bnx2x_save_spirom_version(params->bp, params->port,
params->shmem_base,
(u32)(fw_ver1<<16 | fw_ver2));
-
break;
}
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
- DP(NETIF_MSG_LINK,
- "Setting the BCM8481 LASI control\n");
+ /* This phy uses the NIG latch mechanism since link
+ indication arrives through its LED4 and not via
+ its LASI signal, so we get steady signal
+ instead of clear on read */
+ bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
+ 1 << NIG_LATCH_BC_ENABLE_MI_INT);
+
+ bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr);
+ if (params->req_line_speed == SPEED_AUTO_NEG) {
+
+ u16 autoneg_val, an_1000_val, an_10_100_val;
+ /* set 1000 speed advertisement */
+ bnx2x_cl45_read(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_1000T_CTRL,
+ &an_1000_val);
- bnx2x_cl45_write(bp, params->port,
- ext_phy_type,
- ext_phy_addr,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_LASI_CTRL, 0x1);
+ if (params->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) {
+ an_1000_val |= (1<<8);
+ if (params->req_duplex == DUPLEX_FULL)
+ an_1000_val |= (1<<9);
+ DP(NETIF_MSG_LINK, "Advertising 1G\n");
+ } else
+ an_1000_val &= ~((1<<8) | (1<<9));
- /* Restart autoneg */
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_1000T_CTRL,
+ an_1000_val);
+
+ /* set 100 speed advertisement */
+ bnx2x_cl45_read(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_LEGACY_AN_ADV,
+ &an_10_100_val);
+
+ if (params->speed_cap_mask &
+ (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
+ an_10_100_val |= (1<<7);
+ if (params->req_duplex == DUPLEX_FULL)
+ an_10_100_val |= (1<<8);
+ DP(NETIF_MSG_LINK,
+ "Advertising 100M\n");
+ } else
+ an_10_100_val &= ~((1<<7) | (1<<8));
+
+ /* set 10 speed advertisement */
+ if (params->speed_cap_mask &
+ (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
+ an_10_100_val |= (1<<5);
+ if (params->req_duplex == DUPLEX_FULL)
+ an_10_100_val |= (1<<6);
+ DP(NETIF_MSG_LINK, "Advertising 10M\n");
+ }
+ else
+ an_10_100_val &= ~((1<<5) | (1<<6));
+
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_LEGACY_AN_ADV,
+ an_10_100_val);
+
+ bnx2x_cl45_read(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+ &autoneg_val);
+
+ /* Disable forced speed */
+ autoneg_val &= ~(1<<6|1<<13);
+
+ /* Enable autoneg and restart autoneg
+ for legacy speeds */
+ autoneg_val |= (1<<9|1<<12);
+
+ if (params->req_duplex == DUPLEX_FULL)
+ autoneg_val |= (1<<8);
+ else
+ autoneg_val &= ~(1<<8);
+
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+ autoneg_val);
+
+ if (params->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
+ DP(NETIF_MSG_LINK, "Advertising 10G\n");
+ /* Restart autoneg for 10G*/
bnx2x_cl45_read(bp, params->port,
ext_phy_type,
ext_phy_addr,
@@ -3968,12 +4406,81 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
ext_phy_addr,
MDIO_AN_DEVAD,
MDIO_AN_REG_CTRL, val);
+ }
+ } else {
+ /* Force speed */
+ u16 autoneg_ctrl, pma_ctrl;
+ bnx2x_cl45_read(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+ &autoneg_ctrl);
- bnx2x_save_bcm_spirom_ver(bp, params->port,
- ext_phy_type,
- ext_phy_addr,
- params->shmem_base);
+ /* Disable autoneg */
+ autoneg_ctrl &= ~(1<<12);
+ /* Set 1000 force */
+ switch (params->req_line_speed) {
+ case SPEED_10000:
+ DP(NETIF_MSG_LINK,
+ "Unable to set 10G force !\n");
+ break;
+ case SPEED_1000:
+ bnx2x_cl45_read(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_CTRL,
+ &pma_ctrl);
+ autoneg_ctrl &= ~(1<<13);
+ autoneg_ctrl |= (1<<6);
+ pma_ctrl &= ~(1<<13);
+ pma_ctrl |= (1<<6);
+ DP(NETIF_MSG_LINK,
+ "Setting 1000M force\n");
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_CTRL,
+ pma_ctrl);
+ break;
+ case SPEED_100:
+ autoneg_ctrl |= (1<<13);
+ autoneg_ctrl &= ~(1<<6);
+ DP(NETIF_MSG_LINK,
+ "Setting 100M force\n");
+ break;
+ case SPEED_10:
+ autoneg_ctrl &= ~(1<<13);
+ autoneg_ctrl &= ~(1<<6);
+ DP(NETIF_MSG_LINK,
+ "Setting 10M force\n");
+ break;
+ }
+
+ /* Duplex mode */
+ if (params->req_duplex == DUPLEX_FULL) {
+ autoneg_ctrl |= (1<<8);
+ DP(NETIF_MSG_LINK,
+ "Setting full duplex\n");
+ } else
+ autoneg_ctrl &= ~(1<<8);
+
+ /* Update autoneg ctrl and pma ctrl */
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+ autoneg_ctrl);
+ }
+
+ /* Save spirom version */
+ bnx2x_save_8481_spirom_version(bp, params->port,
+ ext_phy_addr,
+ params->shmem_base);
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
DP(NETIF_MSG_LINK,
@@ -4013,9 +4520,7 @@ static void bnx2x_8727_handle_mod_abs(struct link_params *params)
{
struct bnx2x *bp = params->bp;
u16 mod_abs, rx_alarm_status;
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
u32 val = REG_RD(bp, params->shmem_base +
offsetof(struct shmem_region, dev_info.
port_feature_config[params->port].
@@ -4104,7 +4609,8 @@ static void bnx2x_8727_handle_mod_abs(struct link_params *params)
static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
- struct link_vars *vars)
+ struct link_vars *vars,
+ u8 is_mi_int)
{
struct bnx2x *bp = params->bp;
u32 ext_phy_type;
@@ -4113,11 +4619,9 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
u16 rx_sd, pcs_status;
u8 ext_phy_link_up = 0;
u8 port = params->port;
- if (vars->phy_flags & PHY_XGXS_FLAG) {
- ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ if (vars->phy_flags & PHY_XGXS_FLAG) {
+ ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
switch (ext_phy_type) {
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
@@ -4224,7 +4728,6 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
break;
}
}
-
if (val2 & (1<<1))
vars->line_speed = SPEED_1000;
else
@@ -4281,8 +4784,9 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
if ((val1 & (1<<8)) == 0) {
DP(NETIF_MSG_LINK, "8727 Power fault"
- " has been detected on port"
- " %d\n", params->port);
+ " has been detected on "
+ "port %d\n",
+ params->port);
printk(KERN_ERR PFX "Error: Power"
" fault on %s Port %d has"
" been detected and the"
@@ -4389,6 +4893,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
{
u16 link_status = 0;
u16 an1000_status = 0;
+
if (ext_phy_type ==
PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
bnx2x_cl45_read(bp, params->port,
@@ -4404,7 +4909,6 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
DP(NETIF_MSG_LINK,
"870x LASI status 0x%x->0x%x\n",
val1, val2);
-
} else {
/* In 8073, port1 is directed through emac0 and
* port0 is directed through emac1
@@ -4534,8 +5038,6 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_CDR_BANDWIDTH,
0x0333);
-
-
}
bnx2x_cl45_read(bp, params->port,
ext_phy_type,
@@ -4647,51 +5149,79 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
}
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
- /* Clear LASI interrupt */
- bnx2x_cl45_read(bp, params->port,
- ext_phy_type,
- ext_phy_addr,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_LASI_STATUS, &val1);
- DP(NETIF_MSG_LINK, "8481 LASI status reg = 0x%x\n",
- val1);
-
/* Check 10G-BaseT link status */
- /* Check Global PMD signal ok */
+ /* Check PMD signal ok */
bnx2x_cl45_read(bp, params->port, ext_phy_type,
- ext_phy_addr,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
- &rx_sd);
- /* Check PCS block lock */
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ 0xFFFA,
+ &val1);
bnx2x_cl45_read(bp, params->port, ext_phy_type,
ext_phy_addr,
- MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
- &pcs_status);
- DP(NETIF_MSG_LINK, "8481 1.a = 0x%x, 1.20 = 0x%x\n",
- rx_sd, pcs_status);
- if (rx_sd & pcs_status & 0x1) {
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_PMD_SIGNAL,
+ &val2);
+ DP(NETIF_MSG_LINK, "PMD_SIGNAL 1.a811 = 0x%x\n", val2);
+
+ /* Check link 10G */
+ if (val2 & (1<<11)) {
vars->line_speed = SPEED_10000;
ext_phy_link_up = 1;
- } else {
-
- /* Check 1000-BaseT link status */
- bnx2x_cl45_read(bp, params->port, ext_phy_type,
- ext_phy_addr,
- MDIO_AN_DEVAD, 0xFFE1,
- &val1);
+ bnx2x_8481_set_10G_led_mode(params,
+ ext_phy_type,
+ ext_phy_addr);
+ } else { /* Check Legacy speed link */
+ u16 legacy_status, legacy_speed;
+
+ /* Enable expansion register 0x42
+ (Operation mode status) */
+ bnx2x_cl45_write(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_EXPANSION_REG_ACCESS,
+ 0xf42);
- bnx2x_cl45_read(bp, params->port, ext_phy_type,
- ext_phy_addr,
- MDIO_AN_DEVAD, 0xFFE1,
- &val2);
- DP(NETIF_MSG_LINK, "8481 7.FFE1 ="
- "0x%x-->0x%x\n", val1, val2);
- if (val2 & (1<<2)) {
- vars->line_speed = SPEED_1000;
- ext_phy_link_up = 1;
+ /* Get legacy speed operation status */
+ bnx2x_cl45_read(bp, params->port,
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
+ &legacy_status);
+
+ DP(NETIF_MSG_LINK, "Legacy speed status"
+ " = 0x%x\n", legacy_status);
+ ext_phy_link_up = ((legacy_status & (1<<11))
+ == (1<<11));
+ if (ext_phy_link_up) {
+ legacy_speed = (legacy_status & (3<<9));
+ if (legacy_speed == (0<<9))
+ vars->line_speed = SPEED_10;
+ else if (legacy_speed == (1<<9))
+ vars->line_speed =
+ SPEED_100;
+ else if (legacy_speed == (2<<9))
+ vars->line_speed =
+ SPEED_1000;
+ else /* Should not happen */
+ vars->line_speed = 0;
+
+ if (legacy_status & (1<<8))
+ vars->duplex = DUPLEX_FULL;
+ else
+ vars->duplex = DUPLEX_HALF;
+
+ DP(NETIF_MSG_LINK, "Link is up "
+ "in %dMbps, is_duplex_full"
+ "= %d\n",
+ vars->line_speed,
+ (vars->duplex == DUPLEX_FULL));
+ bnx2x_8481_set_legacy_led_mode(params,
+ ext_phy_type,
+ ext_phy_addr);
}
}
-
break;
default:
DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
@@ -4699,6 +5229,13 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
ext_phy_link_up = 0;
break;
}
+ /* Set SGMII mode for external phy */
+ if (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
+ if (vars->line_speed < SPEED_1000)
+ vars->phy_flags |= PHY_SGMII_FLAG;
+ else
+ vars->phy_flags &= ~PHY_SGMII_FLAG;
+ }
} else { /* SerDes */
ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
@@ -4731,6 +5268,7 @@ static void bnx2x_link_int_enable(struct link_params *params)
u32 ext_phy_type;
u32 mask;
struct bnx2x *bp = params->bp;
+
/* setting the status to report on link up
for either XGXS or SerDes */
@@ -4762,10 +5300,10 @@ static void bnx2x_link_int_enable(struct link_params *params)
bnx2x_bits_en(bp,
NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
mask);
- DP(NETIF_MSG_LINK, "port %x, is_xgxs=%x, int_status 0x%x\n", port,
+
+ DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
(params->switch_cfg == SWITCH_CFG_10G),
REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
-
DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
@@ -4775,12 +5313,47 @@ static void bnx2x_link_int_enable(struct link_params *params)
REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
}
-
+static void bnx2x_8481_rearm_latch_signal(struct bnx2x *bp, u8 port,
+ u8 is_mi_int)
+{
+ u32 latch_status = 0, is_mi_int_status;
+ /* Disable the MI INT ( external phy int )
+ * by writing 1 to the status register. Link down indication
+ * is high-active-signal, so in this case we need to write the
+ * status to clear the XOR
+ */
+ /* Read Latched signals */
+ latch_status = REG_RD(bp,
+ NIG_REG_LATCH_STATUS_0 + port*8);
+ is_mi_int_status = REG_RD(bp,
+ NIG_REG_STATUS_INTERRUPT_PORT0 + port*4);
+ DP(NETIF_MSG_LINK, "original_signal = 0x%x, nig_status = 0x%x,"
+ "latch_status = 0x%x\n",
+ is_mi_int, is_mi_int_status, latch_status);
+ /* Handle only those with latched-signal=up.*/
+ if (latch_status & 1) {
+ /* For all latched-signal=up,Write original_signal to status */
+ if (is_mi_int)
+ bnx2x_bits_en(bp,
+ NIG_REG_STATUS_INTERRUPT_PORT0
+ + port*4,
+ NIG_STATUS_EMAC0_MI_INT);
+ else
+ bnx2x_bits_dis(bp,
+ NIG_REG_STATUS_INTERRUPT_PORT0
+ + port*4,
+ NIG_STATUS_EMAC0_MI_INT);
+ /* For all latched-signal=up : Re-Arm Latch signals */
+ REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
+ (latch_status & 0xfffe) | (latch_status & 1));
+ }
+}
/*
* link management
*/
static void bnx2x_link_int_ack(struct link_params *params,
- struct link_vars *vars, u8 is_10g)
+ struct link_vars *vars, u8 is_10g,
+ u8 is_mi_int)
{
struct bnx2x *bp = params->bp;
u8 port = params->port;
@@ -4791,6 +5364,10 @@ static void bnx2x_link_int_ack(struct link_params *params,
(NIG_STATUS_XGXS0_LINK10G |
NIG_STATUS_XGXS0_LINK_STATUS |
NIG_STATUS_SERDES0_LINK_STATUS));
+ if (XGXS_EXT_PHY_TYPE(params->ext_phy_config)
+ == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) {
+ bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
+ }
if (vars->phy_link_up) {
if (is_10g) {
/* Disable the 10G link interrupt
@@ -4810,7 +5387,8 @@ static void bnx2x_link_int_ack(struct link_params *params,
PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
- DP(NETIF_MSG_LINK, "1G XGXS phy link up\n");
+ DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
+ vars->line_speed);
bnx2x_bits_en(bp,
NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
((1 << ser_lane) <<
@@ -4916,18 +5494,20 @@ static void bnx2x_turn_off_sf(struct bnx2x *bp, u8 port)
u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
u8 *version, u16 len)
{
- struct bnx2x *bp = params->bp;
+ struct bnx2x *bp;
u32 ext_phy_type = 0;
u32 spirom_ver = 0;
- u8 status = 0 ;
+ u8 status;
if (version == NULL || params == NULL)
return -EINVAL;
+ bp = params->bp;
spirom_ver = REG_RD(bp, params->shmem_base +
offsetof(struct shmem_region,
port_mb[params->port].ext_phy_fw_version));
+ status = 0;
/* reset the returned value to zero */
ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
switch (ext_phy_type) {
@@ -4946,13 +5526,18 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
- case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+ status = bnx2x_format_ver(spirom_ver, version, len);
+ break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+ spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 |
+ (spirom_ver & 0x7F);
status = bnx2x_format_ver(spirom_ver, version, len);
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+ version[0] = '\0';
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
@@ -5035,10 +5620,8 @@ static void bnx2x_ext_phy_loopback(struct link_params *params)
if (params->switch_cfg == SWITCH_CFG_10G) {
ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+ ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
/* CL37 Autoneg Enabled */
- ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
switch (ext_phy_type) {
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
@@ -5205,6 +5788,7 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
u8 rc = 0;
u32 tmp;
u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
speed, hw_led_mode);
@@ -5269,7 +5853,7 @@ u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars)
&gp_status);
/* link is up only if both local phy and external phy are up */
if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) &&
- bnx2x_ext_phy_is_link_up(params, vars))
+ bnx2x_ext_phy_is_link_up(params, vars, 1))
return 0;
return -ESRCH;
@@ -5283,6 +5867,7 @@ static u8 bnx2x_link_initialize(struct link_params *params,
u8 rc = 0;
u8 non_ext_phy;
u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
/* Activate the external PHY */
bnx2x_ext_phy_reset(params, vars);
@@ -5334,11 +5919,10 @@ static u8 bnx2x_link_initialize(struct link_params *params,
if (non_ext_phy ||
(ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
(ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
- (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) ||
(params->loopback_mode == LOOPBACK_EXT_PHY)) {
if (params->req_line_speed == SPEED_AUTO_NEG)
bnx2x_set_parallel_detection(params, vars->phy_flags);
- bnx2x_init_internal_phy(params, vars);
+ bnx2x_init_internal_phy(params, vars, non_ext_phy);
}
if (!non_ext_phy)
@@ -5357,11 +5941,11 @@ static u8 bnx2x_link_initialize(struct link_params *params,
u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
{
struct bnx2x *bp = params->bp;
-
u32 val;
- DP(NETIF_MSG_LINK, "Phy Initialization started \n");
- DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n",
- params->req_line_speed, params->req_flow_ctrl);
+
+ DP(NETIF_MSG_LINK, "Phy Initialization started\n");
+ DP(NETIF_MSG_LINK, "req_speed %d, req_flowctrl %d\n",
+ params->req_line_speed, params->req_flow_ctrl);
vars->link_status = 0;
vars->phy_link_up = 0;
vars->link_up = 0;
@@ -5375,7 +5959,6 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
else
vars->phy_flags = PHY_XGXS_FLAG;
-
/* disable attentions */
bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
(NIG_MASK_XGXS0_LINK_STATUS |
@@ -5386,6 +5969,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
bnx2x_emac_init(params, vars);
if (CHIP_REV_IS_FPGA(bp)) {
+
vars->link_up = 1;
vars->line_speed = SPEED_10000;
vars->duplex = DUPLEX_FULL;
@@ -5394,7 +5978,8 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
/* enable on E1.5 FPGA */
if (CHIP_IS_E1H(bp)) {
vars->flow_ctrl |=
- (BNX2X_FLOW_CTRL_TX | BNX2X_FLOW_CTRL_RX);
+ (BNX2X_FLOW_CTRL_TX |
+ BNX2X_FLOW_CTRL_RX);
vars->link_status |=
(LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
@@ -5403,8 +5988,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
bnx2x_emac_enable(params, vars, 0);
bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
/* disable drain */
- REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
- + params->port*4, 0);
+ REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
/* update shared memory */
bnx2x_update_mng(params, vars->link_status);
@@ -5434,6 +6018,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
} else
if (params->loopback_mode == LOOPBACK_BMAC) {
+
vars->link_up = 1;
vars->line_speed = SPEED_10000;
vars->duplex = DUPLEX_FULL;
@@ -5448,7 +6033,9 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
params->port*4, 0);
+
} else if (params->loopback_mode == LOOPBACK_EMAC) {
+
vars->link_up = 1;
vars->line_speed = SPEED_1000;
vars->duplex = DUPLEX_FULL;
@@ -5464,8 +6051,10 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
vars->duplex);
REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
params->port*4, 0);
+
} else if ((params->loopback_mode == LOOPBACK_XGXS_10) ||
- (params->loopback_mode == LOOPBACK_EXT_PHY)) {
+ (params->loopback_mode == LOOPBACK_EXT_PHY)) {
+
vars->link_up = 1;
vars->line_speed = SPEED_10000;
vars->duplex = DUPLEX_FULL;
@@ -5494,10 +6083,14 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
}
REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
params->port*4, 0);
+
+ bnx2x_set_led(bp, params->port, LED_MODE_OPER,
+ vars->line_speed, params->hw_led_mode,
+ params->chip_id);
+
} else
/* No loopback */
{
-
bnx2x_phy_deassert(params, vars->phy_flags);
switch (params->switch_cfg) {
case SWITCH_CFG_1G:
@@ -5505,8 +6098,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
if ((params->ext_phy_config &
PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ==
PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482) {
- vars->phy_flags |=
- PHY_SGMII_FLAG;
+ vars->phy_flags |= PHY_SGMII_FLAG;
}
val = REG_RD(bp,
@@ -5527,7 +6119,6 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
default:
DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
return -EINVAL;
- break;
}
DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr);
@@ -5552,7 +6143,6 @@ static void bnx2x_8726_reset_phy(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
u8 reset_ext_phy)
{
-
struct bnx2x *bp = params->bp;
u32 ext_phy_config = params->ext_phy_config;
u16 hw_led_mode = params->hw_led_mode;
@@ -5565,7 +6155,6 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
config));
/* disable attentions */
-
vars->link_status = 0;
bnx2x_update_mng(params, vars->link_status);
bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
@@ -5603,9 +6192,8 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
{
/* Disable Transmitter */
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr =
+ XGXS_EXT_PHY_ADDR(params->ext_phy_config);
if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
bnx2x_sfp_set_transmitter(bp, port,
@@ -5623,9 +6211,8 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
{
- u8 ext_phy_addr = ((params->ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u8 ext_phy_addr =
+ XGXS_EXT_PHY_ADDR(params->ext_phy_config);
/* Set soft reset */
bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr);
break;
@@ -5663,6 +6250,7 @@ static u8 bnx2x_update_link_down(struct link_params *params,
{
struct bnx2x *bp = params->bp;
u8 port = params->port;
+
DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
bnx2x_set_led(bp, port, LED_MODE_OFF,
0, params->hw_led_mode,
@@ -5699,6 +6287,7 @@ static u8 bnx2x_update_link_up(struct link_params *params,
struct bnx2x *bp = params->bp;
u8 port = params->port;
u8 rc = 0;
+
vars->link_status |= LINK_STATUS_LINK_UP;
if (link_10g) {
bnx2x_bmac_enable(params, vars, 0);
@@ -5752,16 +6341,19 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
u8 link_10g;
u8 ext_phy_link_up, rc = 0;
u32 ext_phy_type;
+ u8 is_mi_int = 0;
DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
- port,
- (vars->phy_flags & PHY_XGXS_FLAG),
- REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
+ port, (vars->phy_flags & PHY_XGXS_FLAG),
+ REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
+ is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
+ port*0x18) > 0);
DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
- REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
- REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
- REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
+ REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
+ is_mi_int,
+ REG_RD(bp,
+ NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
@@ -5773,7 +6365,7 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
/* Check external link change only for non-direct */
- ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars);
+ ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars, is_mi_int);
/* Read gp_status */
CL45_RD_OVER_CL22(bp, port, params->phy_addr,
@@ -5781,7 +6373,8 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
MDIO_GP_STATUS_TOP_AN_STATUS1,
&gp_status);
- rc = bnx2x_link_settings_status(params, vars, gp_status);
+ rc = bnx2x_link_settings_status(params, vars, gp_status,
+ ext_phy_link_up);
if (rc != 0)
return rc;
@@ -5793,7 +6386,7 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
(vars->line_speed == SPEED_15000) ||
(vars->line_speed == SPEED_16000));
- bnx2x_link_int_ack(params, vars, link_10g);
+ bnx2x_link_int_ack(params, vars, link_10g, is_mi_int);
/* In case external phy link is up, and internal link is down
( not initialized yet probably after link initialization, it needs
@@ -5806,7 +6399,7 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
(ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
(ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
(ext_phy_link_up && !vars->phy_link_up))
- bnx2x_init_internal_phy(params, vars);
+ bnx2x_init_internal_phy(params, vars, 0);
/* link is up only if both local phy and external phy are up */
vars->link_up = (ext_phy_link_up && vars->phy_link_up);
@@ -5839,10 +6432,7 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
NIG_MASK_SERDES0_LINK_STATUS |
NIG_MASK_MI_INT));
- ext_phy_addr[port] =
- ((ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config);
/* Need to take the phy out of low power mode in order
to write to access its registers */
@@ -5940,7 +6530,7 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
{
u8 ext_phy_addr[PORT_MAX];
- s8 port;
+ s8 port, first_port, i;
u32 swap_val, swap_override;
DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n");
swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
@@ -5949,8 +6539,13 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
bnx2x_hw_reset(bp, 1 ^ (swap_val && swap_override));
msleep(5);
+ if (swap_val && swap_override)
+ first_port = PORT_0;
+ else
+ first_port = PORT_1;
+
/* PART1 - Reset both phys */
- for (port = PORT_MAX - 1; port >= PORT_0; port--) {
+ for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
/* Extract the ext phy address for the port */
u32 ext_phy_config = REG_RD(bp, shmem_base +
offsetof(struct shmem_region,
@@ -5963,9 +6558,7 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
NIG_MASK_SERDES0_LINK_STATUS |
NIG_MASK_MI_INT));
- ext_phy_addr[port] = ((ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config);
/* Reset the phy */
bnx2x_cl45_write(bp, port,
@@ -5980,7 +6573,7 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
msleep(150);
/* PART2 - Download firmware to both phys */
- for (port = PORT_MAX - 1; port >= PORT_0; port--) {
+ for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
u16 fw_ver1;
bnx2x_bcm8727_external_rom_boot(bp, port,
@@ -5992,16 +6585,13 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
MDIO_PMA_REG_ROM_VER1, &fw_ver1);
if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
DP(NETIF_MSG_LINK,
- "bnx2x_8073_common_init_phy port %x:"
+ "bnx2x_8727_common_init_phy port %x:"
"Download failed. fw version = 0x%x\n",
port, fw_ver1);
return -EINVAL;
}
-
}
-
-
return 0;
}
@@ -6011,6 +6601,7 @@ static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
u8 ext_phy_addr;
u32 val;
s8 port;
+
/* Use port1 because of the static port-swap */
/* Enable the module detection interrupt */
val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
@@ -6026,10 +6617,7 @@ static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
offsetof(struct shmem_region,
dev_info.port_hw_config[port].external_phy_config));
- ext_phy_addr =
- ((ext_phy_config &
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ ext_phy_addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
DP(NETIF_MSG_LINK, "8726_common_init : ext_phy_addr = 0x%x\n",
ext_phy_addr);
diff --git a/drivers/net/bnx2x_link.h b/drivers/net/bnx2x_link.h
index d25ef45..eb898f3 100644
--- a/drivers/net/bnx2x_link.h
+++ b/drivers/net/bnx2x_link.h
@@ -81,48 +81,59 @@ struct link_params {
#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
u16 hw_led_mode; /* part of the hw_config read from the shmem */
+
+ /* phy_addr populated by the phy_init function */
+ u8 phy_addr;
+ /*u8 reserved1;*/
+
u32 lane_config;
u32 ext_phy_config;
-#define XGXS_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
-#define SERDES_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
- PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
+#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
+ ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
+#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
+ (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
+#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
+ ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
+
/* Phy register parameter */
u32 chip_id;
- /* phy_addr populated by the CLC */
- u8 phy_addr;
u16 xgxs_config_rx[4]; /* preemphasis values for the rx side */
-
u16 xgxs_config_tx[4]; /* preemphasis values for the tx side */
+
u32 feature_config_flags;
#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
#define FEATURE_CONFIG_BCM8727_NOC (1<<3)
+
/* Device pointer passed to all callback functions */
struct bnx2x *bp;
};
/* Output parameters */
struct link_vars {
+ u8 phy_flags;
+
+ u8 mac_type;
+#define MAC_TYPE_NONE 0
+#define MAC_TYPE_EMAC 1
+#define MAC_TYPE_BMAC 2
+
u8 phy_link_up; /* internal phy link indication */
u8 link_up;
+
+ u16 line_speed;
u16 duplex;
+
u16 flow_ctrl;
- u32 ieee_fc;
- u8 mac_type;
+ u16 ieee_fc;
-#define MAC_TYPE_NONE 0
-#define MAC_TYPE_EMAC 1
-#define MAC_TYPE_BMAC 2
- u16 line_speed;
u32 autoneg;
#define AUTO_NEG_DISABLED 0x0
#define AUTO_NEG_ENABLED 0x1
#define AUTO_NEG_COMPLETE 0x2
-#define AUTO_NEG_PARALLEL_DETECTION_USED 0x3
-
- u8 phy_flags;
+#define AUTO_NEG_PARALLEL_DETECTION_USED 0x3
/* The same definitions as the shmem parameter */
u32 link_status;
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 239c1dc..ea97587 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -10,7 +10,7 @@
* Written by: Eliezer Tamir
* Based on code from Michael Chan's bnx2 driver
* UDP CSUM errata workaround by Arik Gendelman
- * Slowpath rework by Vladislav Zolotarov
+ * Slowpath and fastpath rework by Vladislav Zolotarov
* Statistics and Link management by Yitchak Gertner
*
*/
@@ -53,12 +53,19 @@
#include "bnx2x.h"
#include "bnx2x_init.h"
+#include "bnx2x_init_ops.h"
#include "bnx2x_dump.h"
-#define DRV_MODULE_VERSION "1.48.105"
-#define DRV_MODULE_RELDATE "2009/03/02"
+#define DRV_MODULE_VERSION "1.52.1"
+#define DRV_MODULE_RELDATE "2009/08/12"
#define BNX2X_BC_VER 0x040200
+#include <linux/firmware.h>
+#include "bnx2x_fw_file_hdr.h"
+/* FW files */
+#define FW_FILE_PREFIX_E1 "bnx2x-e1-"
+#define FW_FILE_PREFIX_E1H "bnx2x-e1h-"
+
/* Time in jiffies before concluding the transmitter is hung */
#define TX_TIMEOUT (5*HZ)
@@ -73,7 +80,18 @@ MODULE_VERSION(DRV_MODULE_VERSION);
static int multi_mode = 1;
module_param(multi_mode, int, 0);
-MODULE_PARM_DESC(multi_mode, " Use per-CPU queues");
+MODULE_PARM_DESC(multi_mode, " Multi queue mode "
+ "(0 Disable; 1 Enable (default))");
+
+static int num_rx_queues;
+module_param(num_rx_queues, int, 0);
+MODULE_PARM_DESC(num_rx_queues, " Number of Rx queues for multi_mode=1"
+ " (default is half number of CPUs)");
+
+static int num_tx_queues;
+module_param(num_tx_queues, int, 0);
+MODULE_PARM_DESC(num_tx_queues, " Number of Tx queues for multi_mode=1"
+ " (default is half number of CPUs)");
static int disable_tpa;
module_param(disable_tpa, int, 0);
@@ -83,6 +101,10 @@ static int int_mode;
module_param(int_mode, int, 0);
MODULE_PARM_DESC(int_mode, " Force interrupt mode (1 INT#x; 2 MSI)");
+static int dropless_fc;
+module_param(dropless_fc, int, 0);
+MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
+
static int poll;
module_param(poll, int, 0);
MODULE_PARM_DESC(poll, " Use polling (for debug)");
@@ -116,12 +138,9 @@ static struct {
static const struct pci_device_id bnx2x_pci_tbl[] = {
- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711 },
- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711E,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711E },
+ { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
+ { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
+ { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
{ 0 }
};
@@ -134,7 +153,7 @@ MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
/* used only at init
* locking is done by mcp
*/
-static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
+void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
{
pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
@@ -181,7 +200,7 @@ static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
u32 len32)
{
- struct dmae_command *dmae = &bp->init_dmae;
+ struct dmae_command dmae;
u32 *wb_comp = bnx2x_sp(bp, wb_comp);
int cnt = 200;
@@ -194,43 +213,43 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
return;
}
- mutex_lock(&bp->dmae_mutex);
-
- memset(dmae, 0, sizeof(struct dmae_command));
+ memset(&dmae, 0, sizeof(struct dmae_command));
- dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
- DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
- DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+ dmae.opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+ DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
#ifdef __BIG_ENDIAN
- DMAE_CMD_ENDIANITY_B_DW_SWAP |
+ DMAE_CMD_ENDIANITY_B_DW_SWAP |
#else
- DMAE_CMD_ENDIANITY_DW_SWAP |
+ DMAE_CMD_ENDIANITY_DW_SWAP |
#endif
- (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
- (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
- dmae->src_addr_lo = U64_LO(dma_addr);
- dmae->src_addr_hi = U64_HI(dma_addr);
- dmae->dst_addr_lo = dst_addr >> 2;
- dmae->dst_addr_hi = 0;
- dmae->len = len32;
- dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
- dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
- dmae->comp_val = DMAE_COMP_VAL;
+ (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+ (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+ dmae.src_addr_lo = U64_LO(dma_addr);
+ dmae.src_addr_hi = U64_HI(dma_addr);
+ dmae.dst_addr_lo = dst_addr >> 2;
+ dmae.dst_addr_hi = 0;
+ dmae.len = len32;
+ dmae.comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
+ dmae.comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
+ dmae.comp_val = DMAE_COMP_VAL;
DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
"dst_addr [%x:%08x (%08x)]\n"
DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
- dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
- dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
- dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
+ dmae.opcode, dmae.src_addr_hi, dmae.src_addr_lo,
+ dmae.len, dmae.dst_addr_hi, dmae.dst_addr_lo, dst_addr,
+ dmae.comp_addr_hi, dmae.comp_addr_lo, dmae.comp_val);
DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
+ mutex_lock(&bp->dmae_mutex);
+
*wb_comp = 0;
- bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
+ bnx2x_post_dmae(bp, &dmae, INIT_DMAE_C(bp));
udelay(5);
@@ -254,7 +273,7 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
{
- struct dmae_command *dmae = &bp->init_dmae;
+ struct dmae_command dmae;
u32 *wb_comp = bnx2x_sp(bp, wb_comp);
int cnt = 200;
@@ -269,41 +288,41 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
return;
}
- mutex_lock(&bp->dmae_mutex);
-
- memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
- memset(dmae, 0, sizeof(struct dmae_command));
+ memset(&dmae, 0, sizeof(struct dmae_command));
- dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
- DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
- DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+ dmae.opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+ DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
#ifdef __BIG_ENDIAN
- DMAE_CMD_ENDIANITY_B_DW_SWAP |
+ DMAE_CMD_ENDIANITY_B_DW_SWAP |
#else
- DMAE_CMD_ENDIANITY_DW_SWAP |
+ DMAE_CMD_ENDIANITY_DW_SWAP |
#endif
- (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
- (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
- dmae->src_addr_lo = src_addr >> 2;
- dmae->src_addr_hi = 0;
- dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
- dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
- dmae->len = len32;
- dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
- dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
- dmae->comp_val = DMAE_COMP_VAL;
+ (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+ (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+ dmae.src_addr_lo = src_addr >> 2;
+ dmae.src_addr_hi = 0;
+ dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
+ dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
+ dmae.len = len32;
+ dmae.comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
+ dmae.comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
+ dmae.comp_val = DMAE_COMP_VAL;
DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
"dst_addr [%x:%08x (%08x)]\n"
DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
- dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
- dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
- dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
+ dmae.opcode, dmae.src_addr_hi, dmae.src_addr_lo,
+ dmae.len, dmae.dst_addr_hi, dmae.dst_addr_lo, src_addr,
+ dmae.comp_addr_hi, dmae.comp_addr_lo, dmae.comp_val);
+ mutex_lock(&bp->dmae_mutex);
+
+ memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
*wb_comp = 0;
- bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
+ bnx2x_post_dmae(bp, &dmae, INIT_DMAE_C(bp));
udelay(5);
@@ -327,6 +346,21 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
mutex_unlock(&bp->dmae_mutex);
}
+void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
+ u32 addr, u32 len)
+{
+ int offset = 0;
+
+ while (len > DMAE_LEN32_WR_MAX) {
+ bnx2x_write_dmae(bp, phys_addr + offset,
+ addr + offset, DMAE_LEN32_WR_MAX);
+ offset += DMAE_LEN32_WR_MAX * 4;
+ len -= DMAE_LEN32_WR_MAX;
+ }
+
+ bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
+}
+
/* used only for slowpath so not inlined */
static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
{
@@ -477,21 +511,21 @@ static void bnx2x_fw_dump(struct bnx2x *bp)
mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
mark = ((mark + 0x3) & ~0x3);
- printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
+ printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n", mark);
for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
for (word = 0; word < 8; word++)
data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
offset + 4*word));
data[8] = 0x0;
- printk(KERN_ERR "%s", (char *)data);
+ printk(KERN_CONT "%s", (char *)data);
}
for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
for (word = 0; word < 8; word++)
data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
offset + 4*word));
data[8] = 0x0;
- printk(KERN_ERR "%s", (char *)data);
+ printk(KERN_CONT "%s", (char *)data);
}
printk("\n" KERN_ERR PFX "end of fw dump\n");
}
@@ -534,16 +568,15 @@ static void bnx2x_panic_dump(struct bnx2x *bp)
/* Tx */
for_each_tx_queue(bp, i) {
struct bnx2x_fastpath *fp = &bp->fp[i];
- struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
BNX2X_ERR("queue[%d]: tx_pkt_prod(%x) tx_pkt_cons(%x)"
" tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n",
i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
BNX2X_ERR(" fp_c_idx(%x) *sb_c_idx(%x)"
- " bd data(%x,%x)\n", le16_to_cpu(fp->fp_c_idx),
+ " tx_db_prod(%x)\n", le16_to_cpu(fp->fp_c_idx),
fp->status_blk->c_status_block.status_block_index,
- hw_prods->packets_prod, hw_prods->bds_prod);
+ fp->tx_db.data.prod);
}
/* Rings */
@@ -645,6 +678,11 @@ static void bnx2x_int_enable(struct bnx2x *bp)
val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
REG_WR(bp, addr, val);
+ /*
+ * Ensure that HC_CONFIG is written before leading/trailing edge config
+ */
+ mmiowb();
+ barrier();
if (CHIP_IS_E1H(bp)) {
/* init leading/trailing edge */
@@ -659,6 +697,9 @@ static void bnx2x_int_enable(struct bnx2x *bp)
REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
}
+
+ /* Make sure that interrupts are indeed enabled from here on */
+ mmiowb();
}
static void bnx2x_int_disable(struct bnx2x *bp)
@@ -681,7 +722,6 @@ static void bnx2x_int_disable(struct bnx2x *bp)
REG_WR(bp, addr, val);
if (REG_RD(bp, addr) != val)
BNX2X_ERR("BUG! proper val not read from IGU!\n");
-
}
static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
@@ -691,6 +731,8 @@ static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
/* disable interrupt handling */
atomic_inc(&bp->intr_sem);
+ smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
+
if (disable_hw)
/* prevent the HW from sending interrupts */
bnx2x_int_disable(bp);
@@ -732,6 +774,10 @@ static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
(*(u32 *)&igu_ack), hc_addr);
REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
+
+ /* Make sure that ACK is written */
+ mmiowb();
+ barrier();
}
static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
@@ -768,16 +814,6 @@ static u16 bnx2x_ack_int(struct bnx2x *bp)
* fast path service functions
*/
-static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
-{
- u16 tx_cons_sb;
-
- /* Tell compiler that status block fields can change */
- barrier();
- tx_cons_sb = le16_to_cpu(*fp->tx_cons_sb);
- return (fp->tx_pkt_cons != tx_cons_sb);
-}
-
static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
{
/* Tell compiler that consumer and producer can change */
@@ -792,7 +828,8 @@ static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
u16 idx)
{
struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
- struct eth_tx_bd *tx_bd;
+ struct eth_tx_start_bd *tx_start_bd;
+ struct eth_tx_bd *tx_data_bd;
struct sk_buff *skb = tx_buf->skb;
u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
int nbd;
@@ -802,51 +839,46 @@ static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
/* unmap first bd */
DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
- tx_bd = &fp->tx_desc_ring[bd_idx];
- pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
- BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
+ tx_start_bd = &fp->tx_desc_ring[bd_idx].start_bd;
+ pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_start_bd),
+ BD_UNMAP_LEN(tx_start_bd), PCI_DMA_TODEVICE);
- nbd = le16_to_cpu(tx_bd->nbd) - 1;
- new_cons = nbd + tx_buf->first_bd;
+ nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
#ifdef BNX2X_STOP_ON_ERROR
- if (nbd > (MAX_SKB_FRAGS + 2)) {
+ if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
BNX2X_ERR("BAD nbd!\n");
bnx2x_panic();
}
#endif
+ new_cons = nbd + tx_buf->first_bd;
- /* Skip a parse bd and the TSO split header bd
- since they have no mapping */
- if (nbd)
- bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
+ /* Get the next bd */
+ bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
- if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
- ETH_TX_BD_FLAGS_TCP_CSUM |
- ETH_TX_BD_FLAGS_SW_LSO)) {
- if (--nbd)
- bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
- tx_bd = &fp->tx_desc_ring[bd_idx];
- /* is this a TSO split header bd? */
- if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
- if (--nbd)
- bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
- }
+ /* Skip a parse bd... */
+ --nbd;
+ bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
+
+ /* ...and the TSO split header bd since they have no mapping */
+ if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
+ --nbd;
+ bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
}
/* now free frags */
while (nbd > 0) {
DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
- tx_bd = &fp->tx_desc_ring[bd_idx];
- pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
- BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
+ tx_data_bd = &fp->tx_desc_ring[bd_idx].reg_bd;
+ pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_data_bd),
+ BD_UNMAP_LEN(tx_data_bd), PCI_DMA_TODEVICE);
if (--nbd)
bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
}
/* release skb */
WARN_ON(!skb);
- dev_kfree_skb(skb);
+ dev_kfree_skb_any(skb);
tx_buf->first_bd = 0;
tx_buf->skb = NULL;
@@ -891,7 +923,7 @@ static void bnx2x_tx_int(struct bnx2x_fastpath *fp)
#endif
#if 0 /* not in RHEL */
- txq = netdev_get_tx_queue(bp->dev, fp->index);
+ txq = netdev_get_tx_queue(bp->dev, fp->index - bp->num_rx_queues);
#endif
hw_cons = le16_to_cpu(*fp->tx_cons_sb);
sw_cons = fp->tx_pkt_cons;
@@ -1005,6 +1037,7 @@ static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
break;
case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
+ case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DISABLED):
DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
break;
@@ -1488,6 +1521,13 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
bd_prod = RX_BD(bd_prod);
bd_cons = RX_BD(bd_cons);
+ /* Prefetch the page containing the BD descriptor
+ at producer's index. It will be needed when new skb is
+ allocated */
+ prefetch((void *)(PAGE_ALIGN((unsigned long)
+ (&fp->rx_desc_ring[bd_prod])) -
+ PAGE_SIZE + 1));
+
cqe = &fp->rx_comp_ring[comp_ring_cons];
cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
@@ -1596,7 +1636,8 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
skb = new_skb;
- } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
+ } else
+ if (likely(bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0)) {
pci_unmap_single(bp->pdev,
pci_unmap_addr(rx_buf, mapping),
bp->rx_buf_size,
@@ -1672,7 +1713,6 @@ static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie, struct pt_regs *r
struct bnx2x_fastpath *fp = fp_cookie;
struct bnx2x *bp = fp->bp;
struct net_device *poll_dev = &fp->dummy_netdev;
- int index = fp->index;
/* Return here if interrupt is disabled */
if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
@@ -1681,7 +1721,7 @@ static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie, struct pt_regs *r
}
DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
- index, fp->sb_id);
+ fp->index, fp->sb_id);
bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
#ifdef BNX2X_STOP_ON_ERROR
@@ -1689,12 +1729,27 @@ static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie, struct pt_regs *r
return IRQ_HANDLED;
#endif
- prefetch(fp->rx_cons_sb);
- prefetch(fp->tx_cons_sb);
- prefetch(&fp->status_blk->c_status_block.status_block_index);
- prefetch(&fp->status_blk->u_status_block.status_block_index);
+ /* Handle Rx or Tx according to MSI-X vector */
+ if (fp->is_rx_queue) {
+ prefetch(fp->rx_cons_sb);
+ prefetch(&fp->status_blk->u_status_block.status_block_index);
+
+ netif_rx_schedule(poll_dev);
+
+ } else {
+ prefetch(fp->tx_cons_sb);
+ prefetch(&fp->status_blk->c_status_block.status_block_index);
- netif_rx_schedule(poll_dev);
+ bnx2x_update_fpsb_idx(fp);
+ rmb();
+ bnx2x_tx_int(fp);
+
+ /* Re-enable interrupts */
+ bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID,
+ le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1);
+ bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID,
+ le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1);
+ }
return IRQ_HANDLED;
}
@@ -1704,6 +1759,7 @@ static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance, struct pt_regs *
struct bnx2x *bp = netdev_priv(dev_instance);
u16 status = bnx2x_ack_int(bp);
u16 mask;
+ int i;
/* Return here if interrupt is shared and it's not for us */
if (unlikely(status == 0)) {
@@ -1723,18 +1779,38 @@ static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance, struct pt_regs *
return IRQ_HANDLED;
#endif
- mask = 0x2 << bp->fp[0].sb_id;
- if (status & mask) {
- struct bnx2x_fastpath *fp = &bp->fp[0];
+ for (i = 0; i < BNX2X_NUM_QUEUES(bp); i++) {
+ struct bnx2x_fastpath *fp = &bp->fp[i];
- prefetch(fp->rx_cons_sb);
- prefetch(fp->tx_cons_sb);
- prefetch(&fp->status_blk->c_status_block.status_block_index);
- prefetch(&fp->status_blk->u_status_block.status_block_index);
+ mask = 0x2 << fp->sb_id;
+ if (status & mask) {
+ /* Handle Rx or Tx according to SB id */
+ if (fp->is_rx_queue) {
+ prefetch(fp->rx_cons_sb);
+ prefetch(&fp->status_blk->u_status_block.
+ status_block_index);
- netif_rx_schedule(&bnx2x_fp(bp, 0, dummy_netdev));
+ netif_rx_schedule(&fp->dummy_netdev);
- status &= ~mask;
+ } else {
+ prefetch(fp->tx_cons_sb);
+ prefetch(&fp->status_blk->c_status_block.
+ status_block_index);
+
+ bnx2x_update_fpsb_idx(fp);
+ rmb();
+ bnx2x_tx_int(fp);
+
+ /* Re-enable interrupts */
+ bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID,
+ le16_to_cpu(fp->fp_u_idx),
+ IGU_INT_NOP, 1);
+ bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID,
+ le16_to_cpu(fp->fp_c_idx),
+ IGU_INT_ENABLE, 1);
+ }
+ status &= ~mask;
+ }
}
@@ -2061,6 +2137,12 @@ static void bnx2x_calc_fc_adv(struct bnx2x *bp)
static void bnx2x_link_report(struct bnx2x *bp)
{
+ if (bp->state == BNX2X_STATE_DISABLED) {
+ netif_carrier_off(bp->dev);
+ printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
+ return;
+ }
+
if (bp->link_vars.link_up) {
if (bp->state == BNX2X_STATE_OPEN)
netif_carrier_on(bp->dev);
@@ -2100,9 +2182,7 @@ static u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
/* Initialize link parameters structure variables */
/* It is recommended to turn off RX FC for jumbo frames
for better performance */
- if (IS_E1HMF(bp))
- bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
- else if (bp->dev->mtu > 5000)
+ if (bp->dev->mtu > 5000)
bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
else
bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
@@ -2197,6 +2277,46 @@ static void bnx2x_init_port_minmax(struct bnx2x *bp)
bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
}
+/* Calculates the sum of vn_min_rates.
+ It's needed for further normalizing of the min_rates.
+ Returns:
+ sum of vn_min_rates.
+ or
+ 0 - if all the min_rates are 0.
+ In the later case fainess algorithm should be deactivated.
+ If not all min_rates are zero then those that are zeroes will be set to 1.
+ */
+static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
+{
+ int all_zero = 1;
+ int port = BP_PORT(bp);
+ int vn;
+
+ bp->vn_weight_sum = 0;
+ for (vn = VN_0; vn < E1HVN_MAX; vn++) {
+ int func = 2*vn + port;
+ u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
+ u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
+ FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
+
+ /* Skip hidden vns */
+ if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
+ continue;
+
+ /* If min rate is zero - set it to 1 */
+ if (!vn_min_rate)
+ vn_min_rate = DEF_MIN_RATE;
+ else
+ all_zero = 0;
+
+ bp->vn_weight_sum += vn_min_rate;
+ }
+
+ /* ... only if all min rates are zeros - disable fairness */
+ if (all_zero)
+ bp->vn_weight_sum = 0;
+}
+
static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
{
struct rate_shaping_vars_per_vn m_rs_vn;
@@ -2274,7 +2394,7 @@ static void bnx2x_link_attn(struct bnx2x *bp)
if (bp->link_vars.link_up) {
/* dropless flow control */
- if (CHIP_IS_E1H(bp)) {
+ if (CHIP_IS_E1H(bp) && bp->dropless_fc) {
int port = BP_PORT(bp);
u32 pause_enabled = 0;
@@ -2282,7 +2402,7 @@ static void bnx2x_link_attn(struct bnx2x *bp)
pause_enabled = 1;
REG_WR(bp, BAR_USTRORM_INTMEM +
- USTORM_PAUSE_ENABLED_OFFSET(port),
+ USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
pause_enabled);
}
@@ -2307,14 +2427,12 @@ static void bnx2x_link_attn(struct bnx2x *bp)
int func;
int vn;
+ /* Set the attention towards other drivers on the same port */
for (vn = VN_0; vn < E1HVN_MAX; vn++) {
if (vn == BP_E1HVN(bp))
continue;
func = ((vn << 1) | port);
-
- /* Set the attention towards other drivers
- on the same port */
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
(LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
}
@@ -2340,6 +2458,8 @@ static void bnx2x_link_attn(struct bnx2x *bp)
static void bnx2x__link_status_update(struct bnx2x *bp)
{
+ int func = BP_FUNC(bp);
+
if (bp->state != BNX2X_STATE_OPEN)
return;
@@ -2350,6 +2470,9 @@ static void bnx2x__link_status_update(struct bnx2x *bp)
else
bnx2x_stats_handle(bp, STATS_EVENT_STOP);
+ bp->mf_config = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
+ bnx2x_calc_vn_weight_sum(bp);
+
/* indicate link status */
bnx2x_link_report(bp);
}
@@ -2378,6 +2501,152 @@ static void bnx2x_pmf_update(struct bnx2x *bp)
* General service functions
*/
+/* send the MCP a request, block until there is a reply */
+u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
+{
+ int func = BP_FUNC(bp);
+ u32 seq = ++bp->fw_seq;
+ u32 rc = 0;
+ u32 cnt = 1;
+ u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
+
+ SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
+ DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
+
+ do {
+ /* let the FW do it's magic ... */
+ msleep(delay);
+
+ rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
+
+ /* Give the FW up to 2 second (200*10ms) */
+ } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));
+
+ DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
+ cnt*delay, rc, seq);
+
+ /* is this a reply to our command? */
+ if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
+ rc &= FW_MSG_CODE_MASK;
+ else {
+ /* FW BUG! */
+ BNX2X_ERR("FW failed to respond!\n");
+ bnx2x_fw_dump(bp);
+ rc = 0;
+ }
+
+ return rc;
+}
+
+static void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
+static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set);
+static void bnx2x_set_rx_mode(struct net_device *dev);
+
+static void bnx2x_e1h_disable(struct bnx2x *bp)
+{
+ int port = BP_PORT(bp);
+ int i;
+
+ bp->rx_mode = BNX2X_RX_MODE_NONE;
+ bnx2x_set_storm_rx_mode(bp);
+
+ netif_tx_disable(bp->dev);
+ bp->dev->trans_start = jiffies; /* prevent tx timeout */
+
+ REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
+
+ bnx2x_set_mac_addr_e1h(bp, 0);
+
+ for (i = 0; i < MC_HASH_SIZE; i++)
+ REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
+
+ netif_carrier_off(bp->dev);
+}
+
+static void bnx2x_e1h_enable(struct bnx2x *bp)
+{
+ int port = BP_PORT(bp);
+
+ REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
+
+ bnx2x_set_mac_addr_e1h(bp, 1);
+
+ /* Tx queue should be only reenabled */
+ netif_wake_queue(bp->dev);
+
+ /* Initialize the receive filter. */
+ bnx2x_set_rx_mode(bp->dev);
+}
+
+static void bnx2x_update_min_max(struct bnx2x *bp)
+{
+ int port = BP_PORT(bp);
+ int vn, i;
+
+ /* Init rate shaping and fairness contexts */
+ bnx2x_init_port_minmax(bp);
+
+ bnx2x_calc_vn_weight_sum(bp);
+
+ for (vn = VN_0; vn < E1HVN_MAX; vn++)
+ bnx2x_init_vn_minmax(bp, 2*vn + port);
+
+ if (bp->port.pmf) {
+ int func;
+
+ /* Set the attention towards other drivers on the same port */
+ for (vn = VN_0; vn < E1HVN_MAX; vn++) {
+ if (vn == BP_E1HVN(bp))
+ continue;
+
+ func = ((vn << 1) | port);
+ REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
+ (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
+ }
+
+ /* Store it to internal memory */
+ for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
+ REG_WR(bp, BAR_XSTRORM_INTMEM +
+ XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
+ ((u32 *)(&bp->cmng))[i]);
+ }
+}
+
+static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
+{
+ int func = BP_FUNC(bp);
+
+ DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
+ bp->mf_config = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
+
+ if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
+
+ if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
+ DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
+ bp->state = BNX2X_STATE_DISABLED;
+
+ bnx2x_e1h_disable(bp);
+ } else {
+ DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
+ bp->state = BNX2X_STATE_OPEN;
+
+ bnx2x_e1h_enable(bp);
+ }
+ dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
+ }
+ if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
+
+ bnx2x_update_min_max(bp);
+ dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
+ }
+
+ /* Report results to MCP */
+ if (dcc_event)
+ bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE);
+ else
+ bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK);
+}
+
/* the slow path queue is odd since completions arrive on the fastpath ring */
static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
u32 data_hi, u32 data_lo, int common)
@@ -2428,9 +2697,14 @@ static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
bp->spq_prod_idx++;
}
+ /* Make sure that BD data is updated before writing the producer */
+ wmb();
+
REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
bp->spq_prod_idx);
+ mmiowb();
+
spin_unlock_bh(&bp->spq_lock);
return 0;
}
@@ -2597,6 +2871,23 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
}
}
+static inline void bnx2x_fan_failure(struct bnx2x *bp)
+{
+ int port = BP_PORT(bp);
+
+ /* mark the failure */
+ bp->link_params.ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
+ bp->link_params.ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
+ SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
+ bp->link_params.ext_phy_config);
+
+ /* log the failure */
+ printk(KERN_ERR PFX "Fan Failure on Network Controller %s has caused"
+ " the driver to shutdown the card to prevent permanent"
+ " damage. Please contact Dell Support for assistance\n",
+ bp->dev->name);
+}
+
static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
{
int port = BP_PORT(bp);
@@ -2614,31 +2905,15 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
BNX2X_ERR("SPIO5 hw attention\n");
+ /* Fan failure attention */
switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
- /* Fan failure attention */
-
- /* The PHY reset is controlled by GPIO 1 */
- bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
/* Low power mode is controlled by GPIO 2 */
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
- /* mark the failure */
- bp->link_params.ext_phy_config &=
- ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
- bp->link_params.ext_phy_config |=
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
- SHMEM_WR(bp,
- dev_info.port_hw_config[port].
- external_phy_config,
- bp->link_params.ext_phy_config);
- /* log the failure */
- printk(KERN_ERR PFX "Fan Failure on Network"
- " Controller %s has caused the driver to"
- " shutdown the card to prevent permanent"
- " damage. Please contact Dell Support for"
- " assistance\n", bp->dev->name);
+ /* The PHY reset is controlled by GPIO 1 */
+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
@@ -2655,6 +2930,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
default:
break;
}
+ bnx2x_fan_failure(bp);
}
if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
@@ -2671,7 +2947,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
REG_WR(bp, reg_offset, val);
BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
- (attn & HW_INTERRUT_ASSERT_SET_0));
+ (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
bnx2x_panic();
}
}
@@ -2702,7 +2978,7 @@ static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
REG_WR(bp, reg_offset, val);
BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
- (attn & HW_INTERRUT_ASSERT_SET_1));
+ (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
bnx2x_panic();
}
}
@@ -2742,7 +3018,7 @@ static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
REG_WR(bp, reg_offset, val);
BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
- (attn & HW_INTERRUT_ASSERT_SET_2));
+ (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
bnx2x_panic();
}
}
@@ -2757,9 +3033,12 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
int func = BP_FUNC(bp);
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
+ val = SHMEM_RD(bp, func_mb[func].drv_status);
+ if (val & DRV_STATUS_DCC_EVENT_MASK)
+ bnx2x_dcc_event(bp,
+ (val & DRV_STATUS_DCC_EVENT_MASK));
bnx2x__link_status_update(bp);
- if (SHMEM_RD(bp, func_mb[func].drv_status) &
- DRV_STATUS_PMF)
+ if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
bnx2x_pmf_update(bp);
} else if (attn & BNX2X_MC_ASSERT_BITS) {
@@ -3117,53 +3396,6 @@ static void bnx2x_storm_stats_post(struct bnx2x *bp)
}
}
-static void bnx2x_stats_init(struct bnx2x *bp)
-{
- int port = BP_PORT(bp);
- int i;
-
- bp->stats_pending = 0;
- bp->executer_idx = 0;
- bp->stats_counter = 0;
-
- /* port stats */
- if (!BP_NOMCP(bp))
- bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
- else
- bp->port.port_stx = 0;
- DP(BNX2X_MSG_STATS, "port_stx 0x%x\n", bp->port.port_stx);
-
- memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
- bp->port.old_nig_stats.brb_discard =
- REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
- bp->port.old_nig_stats.brb_truncate =
- REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
- REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
- &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
- REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
- &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
-
- /* function stats */
- for_each_queue(bp, i) {
- struct bnx2x_fastpath *fp = &bp->fp[i];
-
- memset(&fp->old_tclient, 0,
- sizeof(struct tstorm_per_client_stats));
- memset(&fp->old_uclient, 0,
- sizeof(struct ustorm_per_client_stats));
- memset(&fp->old_xclient, 0,
- sizeof(struct xstorm_per_client_stats));
- memset(&fp->eth_q_stats, 0, sizeof(struct bnx2x_eth_q_stats));
- }
-
- memset(&bp->net_stats, 0, sizeof(struct net_device_stats));
- memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
-
- bp->stats_state = STATS_STATE_DISABLED;
- if (IS_E1HMF(bp) && bp->port.pmf && bp->port.port_stx)
- bnx2x_stats_handle(bp, STATS_EVENT_PMF);
-}
-
static void bnx2x_hw_stats_post(struct bnx2x *bp)
{
struct dmae_command *dmae = &bp->stats_dmae;
@@ -3724,7 +3956,8 @@ static int bnx2x_storm_stats_update(struct bnx2x *bp)
struct bnx2x_eth_stats *estats = &bp->eth_stats;
int i;
- memset(&(fstats->total_bytes_received_hi), 0,
+ memcpy(&(fstats->total_bytes_received_hi),
+ &(bnx2x_sp(bp, func_stats_base)->total_bytes_received_hi),
sizeof(struct host_func_stats) - 2*sizeof(u32));
estats->error_bytes_received_hi = 0;
estats->error_bytes_received_lo = 0;
@@ -3733,7 +3966,7 @@ static int bnx2x_storm_stats_update(struct bnx2x *bp)
estats->no_buff_discard_hi = 0;
estats->no_buff_discard_lo = 0;
- for_each_queue(bp, i) {
+ for_each_rx_queue(bp, i) {
struct bnx2x_fastpath *fp = &bp->fp[i];
int cl_id = fp->cl_id;
struct tstorm_per_client_stats *tclient =
@@ -3772,11 +4005,24 @@ static int bnx2x_storm_stats_update(struct bnx2x *bp)
}
qstats->total_bytes_received_hi =
- qstats->valid_bytes_received_hi =
- le32_to_cpu(tclient->total_rcv_bytes.hi);
+ le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
qstats->total_bytes_received_lo =
+ le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
+
+ ADD_64(qstats->total_bytes_received_hi,
+ le32_to_cpu(tclient->rcv_multicast_bytes.hi),
+ qstats->total_bytes_received_lo,
+ le32_to_cpu(tclient->rcv_multicast_bytes.lo));
+
+ ADD_64(qstats->total_bytes_received_hi,
+ le32_to_cpu(tclient->rcv_unicast_bytes.hi),
+ qstats->total_bytes_received_lo,
+ le32_to_cpu(tclient->rcv_unicast_bytes.lo));
+
+ qstats->valid_bytes_received_hi =
+ qstats->total_bytes_received_hi;
qstats->valid_bytes_received_lo =
- le32_to_cpu(tclient->total_rcv_bytes.lo);
+ qstats->total_bytes_received_lo;
qstats->error_bytes_received_hi =
le32_to_cpu(tclient->rcv_error_bytes.hi);
@@ -3809,9 +4055,19 @@ static int bnx2x_storm_stats_update(struct bnx2x *bp)
UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
qstats->total_bytes_transmitted_hi =
- le32_to_cpu(xclient->total_sent_bytes.hi);
+ le32_to_cpu(xclient->unicast_bytes_sent.hi);
qstats->total_bytes_transmitted_lo =
- le32_to_cpu(xclient->total_sent_bytes.lo);
+ le32_to_cpu(xclient->unicast_bytes_sent.lo);
+
+ ADD_64(qstats->total_bytes_transmitted_hi,
+ le32_to_cpu(xclient->multicast_bytes_sent.hi),
+ qstats->total_bytes_transmitted_lo,
+ le32_to_cpu(xclient->multicast_bytes_sent.lo));
+
+ ADD_64(qstats->total_bytes_transmitted_hi,
+ le32_to_cpu(xclient->broadcast_bytes_sent.hi),
+ qstats->total_bytes_transmitted_lo,
+ le32_to_cpu(xclient->broadcast_bytes_sent.lo));
UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
total_unicast_packets_transmitted);
@@ -3927,7 +4183,7 @@ static void bnx2x_net_stats_update(struct bnx2x *bp)
nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
nstats->rx_dropped = estats->mac_discard;
- for_each_queue(bp, i)
+ for_each_rx_queue(bp, i)
nstats->rx_dropped +=
le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
@@ -3981,7 +4237,7 @@ static void bnx2x_drv_stats_update(struct bnx2x *bp)
estats->rx_err_discard_pkt = 0;
estats->rx_skb_alloc_failed = 0;
estats->hw_csum_err = 0;
- for_each_queue(bp, i) {
+ for_each_rx_queue(bp, i) {
struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
estats->driver_xoff += qstats->driver_xoff;
@@ -4011,6 +4267,8 @@ static void bnx2x_stats_update(struct bnx2x *bp)
bnx2x_drv_stats_update(bp);
if (bp->msglevel & NETIF_MSG_TIMER) {
+ struct bnx2x_fastpath *fp0_rx = bp->fp;
+ struct bnx2x_fastpath *fp0_tx = &(bp->fp[bp->num_rx_queues]);
struct tstorm_per_client_stats *old_tclient =
&bp->fp->old_tclient;
struct bnx2x_eth_q_stats *qstats = &bp->fp->eth_q_stats;
@@ -4021,13 +4279,13 @@ static void bnx2x_stats_update(struct bnx2x *bp)
printk(KERN_DEBUG "%s:\n", bp->dev->name);
printk(KERN_DEBUG " tx avail (%4x) tx hc idx (%x)"
" tx pkt (%lx)\n",
- bnx2x_tx_avail(bp->fp),
- le16_to_cpu(*bp->fp->tx_cons_sb), nstats->tx_packets);
+ bnx2x_tx_avail(fp0_tx),
+ le16_to_cpu(*fp0_tx->tx_cons_sb), nstats->tx_packets);
printk(KERN_DEBUG " rx usage (%4x) rx hc idx (%x)"
" rx pkt (%lx)\n",
- (u16)(le16_to_cpu(*bp->fp->rx_cons_sb) -
- bp->fp->rx_comp_cons),
- le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets);
+ (u16)(le16_to_cpu(*fp0_rx->rx_cons_sb) -
+ fp0_rx->rx_comp_cons),
+ le16_to_cpu(*fp0_rx->rx_cons_sb), nstats->rx_packets);
printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u "
"brb truncate %u\n",
(netif_queue_stopped(bp->dev) ? "Xoff" : "Xon"),
@@ -4173,11 +4431,181 @@ static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
bnx2x_stats_stm[state][event].action(bp);
bp->stats_state = bnx2x_stats_stm[state][event].next_state;
+ /* Make sure the state has been "changed" */
+ smp_wmb();
+
if ((event != STATS_EVENT_UPDATE) || (bp->msglevel & NETIF_MSG_TIMER))
DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
state, event, bp->stats_state);
}
+static void bnx2x_port_stats_base_init(struct bnx2x *bp)
+{
+ struct dmae_command *dmae;
+ u32 *stats_comp = bnx2x_sp(bp, stats_comp);
+
+ /* sanity */
+ if (!bp->port.pmf || !bp->port.port_stx) {
+ BNX2X_ERR("BUG!\n");
+ return;
+ }
+
+ bp->executer_idx = 0;
+
+ dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+ dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+ DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+ DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+ DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+ (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+ (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+ dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
+ dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
+ dmae->dst_addr_lo = bp->port.port_stx >> 2;
+ dmae->dst_addr_hi = 0;
+ dmae->len = sizeof(struct host_port_stats) >> 2;
+ dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
+ dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
+ dmae->comp_val = DMAE_COMP_VAL;
+
+ *stats_comp = 0;
+ bnx2x_hw_stats_post(bp);
+ bnx2x_stats_comp(bp);
+}
+
+static void bnx2x_func_stats_base_init(struct bnx2x *bp)
+{
+ int vn, vn_max = IS_E1HMF(bp) ? E1HVN_MAX : E1VN_MAX;
+ int port = BP_PORT(bp);
+ int func;
+ u32 func_stx;
+
+ /* sanity */
+ if (!bp->port.pmf || !bp->func_stx) {
+ BNX2X_ERR("BUG!\n");
+ return;
+ }
+
+ /* save our func_stx */
+ func_stx = bp->func_stx;
+
+ for (vn = VN_0; vn < vn_max; vn++) {
+ func = 2*vn + port;
+
+ bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
+ bnx2x_func_stats_init(bp);
+ bnx2x_hw_stats_post(bp);
+ bnx2x_stats_comp(bp);
+ }
+
+ /* restore our func_stx */
+ bp->func_stx = func_stx;
+}
+
+static void bnx2x_func_stats_base_update(struct bnx2x *bp)
+{
+ struct dmae_command *dmae = &bp->stats_dmae;
+ u32 *stats_comp = bnx2x_sp(bp, stats_comp);
+
+ /* sanity */
+ if (!bp->func_stx) {
+ BNX2X_ERR("BUG!\n");
+ return;
+ }
+
+ bp->executer_idx = 0;
+ memset(dmae, 0, sizeof(struct dmae_command));
+
+ dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+ DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+ DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+ DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+ (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+ (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+ dmae->src_addr_lo = bp->func_stx >> 2;
+ dmae->src_addr_hi = 0;
+ dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base));
+ dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats_base));
+ dmae->len = sizeof(struct host_func_stats) >> 2;
+ dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
+ dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
+ dmae->comp_val = DMAE_COMP_VAL;
+
+ *stats_comp = 0;
+ bnx2x_hw_stats_post(bp);
+ bnx2x_stats_comp(bp);
+}
+
+static void bnx2x_stats_init(struct bnx2x *bp)
+{
+ int port = BP_PORT(bp);
+ int func = BP_FUNC(bp);
+ int i;
+
+ bp->stats_pending = 0;
+ bp->executer_idx = 0;
+ bp->stats_counter = 0;
+
+ /* port and func stats for management */
+ if (!BP_NOMCP(bp)) {
+ bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
+ bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
+
+ } else {
+ bp->port.port_stx = 0;
+ bp->func_stx = 0;
+ }
+ DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n",
+ bp->port.port_stx, bp->func_stx);
+
+ /* port stats */
+ memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
+ bp->port.old_nig_stats.brb_discard =
+ REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
+ bp->port.old_nig_stats.brb_truncate =
+ REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
+ REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
+ &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
+ REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
+ &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
+
+ /* function stats */
+ for_each_queue(bp, i) {
+ struct bnx2x_fastpath *fp = &bp->fp[i];
+
+ memset(&fp->old_tclient, 0,
+ sizeof(struct tstorm_per_client_stats));
+ memset(&fp->old_uclient, 0,
+ sizeof(struct ustorm_per_client_stats));
+ memset(&fp->old_xclient, 0,
+ sizeof(struct xstorm_per_client_stats));
+ memset(&fp->eth_q_stats, 0, sizeof(struct bnx2x_eth_q_stats));
+ }
+
+ memset(&bp->net_stats, 0, sizeof(struct net_device_stats));
+ memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
+
+ bp->stats_state = STATS_STATE_DISABLED;
+
+ if (bp->port.pmf) {
+ if (bp->port.port_stx)
+ bnx2x_port_stats_base_init(bp);
+
+ if (bp->func_stx)
+ bnx2x_func_stats_base_init(bp);
+
+ } else if (bp->func_stx)
+ bnx2x_func_stats_base_update(bp);
+}
+
static void bnx2x_timer(unsigned long data)
{
struct bnx2x *bp = (struct bnx2x *) data;
@@ -4240,12 +4668,13 @@ static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
{
int port = BP_PORT(bp);
- bnx2x_init_fill(bp, USTORM_INTMEM_ADDR +
- USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
- sizeof(struct ustorm_status_block)/4);
- bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR +
- CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
- sizeof(struct cstorm_status_block)/4);
+ /* "CSTORM" */
+ bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
+ CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), 0,
+ CSTORM_SB_STATUS_BLOCK_U_SIZE / 4);
+ bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
+ CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), 0,
+ CSTORM_SB_STATUS_BLOCK_C_SIZE / 4);
}
static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
@@ -4261,17 +4690,17 @@ static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
u_status_block);
sb->u_status_block.status_block_id = sb_id;
- REG_WR(bp, BAR_USTRORM_INTMEM +
- USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
- REG_WR(bp, BAR_USTRORM_INTMEM +
- ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
+ REG_WR(bp, BAR_CSTRORM_INTMEM +
+ CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id), U64_LO(section));
+ REG_WR(bp, BAR_CSTRORM_INTMEM +
+ ((CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id)) + 4),
U64_HI(section));
- REG_WR8(bp, BAR_USTRORM_INTMEM + FP_USB_FUNC_OFF +
- USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
+ REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_USB_FUNC_OFF +
+ CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), func);
for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
- REG_WR16(bp, BAR_USTRORM_INTMEM +
- USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
+ REG_WR16(bp, BAR_CSTRORM_INTMEM +
+ CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id, index), 1);
/* CSTORM */
section = ((u64)mapping) + offsetof(struct host_status_block,
@@ -4279,16 +4708,16 @@ static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
sb->c_status_block.status_block_id = sb_id;
REG_WR(bp, BAR_CSTRORM_INTMEM +
- CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
+ CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id), U64_LO(section));
REG_WR(bp, BAR_CSTRORM_INTMEM +
- ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
+ ((CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id)) + 4),
U64_HI(section));
REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
- CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
+ CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), func);
for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
REG_WR16(bp, BAR_CSTRORM_INTMEM +
- CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
+ CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id, index), 1);
bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
}
@@ -4297,16 +4726,16 @@ static void bnx2x_zero_def_sb(struct bnx2x *bp)
{
int func = BP_FUNC(bp);
- bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR +
+ bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY +
TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
sizeof(struct tstorm_def_status_block)/4);
- bnx2x_init_fill(bp, USTORM_INTMEM_ADDR +
- USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
- sizeof(struct ustorm_def_status_block)/4);
- bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR +
- CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
- sizeof(struct cstorm_def_status_block)/4);
- bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR +
+ bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
+ CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), 0,
+ sizeof(struct cstorm_def_status_block_u)/4);
+ bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
+ CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), 0,
+ sizeof(struct cstorm_def_status_block_c)/4);
+ bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY +
XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
sizeof(struct xstorm_def_status_block)/4);
}
@@ -4358,17 +4787,17 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
u_def_status_block);
def_sb->u_def_status_block.status_block_id = sb_id;
- REG_WR(bp, BAR_USTRORM_INTMEM +
- USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
- REG_WR(bp, BAR_USTRORM_INTMEM +
- ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
+ REG_WR(bp, BAR_CSTRORM_INTMEM +
+ CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func), U64_LO(section));
+ REG_WR(bp, BAR_CSTRORM_INTMEM +
+ ((CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func)) + 4),
U64_HI(section));
- REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
- USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
+ REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_USB_FUNC_OFF +
+ CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), func);
for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
- REG_WR16(bp, BAR_USTRORM_INTMEM +
- USTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
+ REG_WR16(bp, BAR_CSTRORM_INTMEM +
+ CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(func, index), 1);
/* CSTORM */
section = ((u64)mapping) + offsetof(struct host_def_status_block,
@@ -4376,16 +4805,16 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
def_sb->c_def_status_block.status_block_id = sb_id;
REG_WR(bp, BAR_CSTRORM_INTMEM +
- CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
+ CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func), U64_LO(section));
REG_WR(bp, BAR_CSTRORM_INTMEM +
- ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
+ ((CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func)) + 4),
U64_HI(section));
REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
- CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
+ CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), func);
for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
REG_WR16(bp, BAR_CSTRORM_INTMEM +
- CSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
+ CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(func, index), 1);
/* TSTORM */
section = ((u64)mapping) + offsetof(struct host_def_status_block,
@@ -4436,24 +4865,24 @@ static void bnx2x_update_coalesce(struct bnx2x *bp)
int sb_id = bp->fp[i].sb_id;
/* HC_INDEX_U_ETH_RX_CQ_CONS */
- REG_WR8(bp, BAR_USTRORM_INTMEM +
- USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
- U_SB_ETH_RX_CQ_INDEX),
+ REG_WR8(bp, BAR_CSTRORM_INTMEM +
+ CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, sb_id,
+ U_SB_ETH_RX_CQ_INDEX),
bp->rx_ticks/12);
- REG_WR16(bp, BAR_USTRORM_INTMEM +
- USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
- U_SB_ETH_RX_CQ_INDEX),
- bp->rx_ticks ? 0 : 1);
+ REG_WR16(bp, BAR_CSTRORM_INTMEM +
+ CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id,
+ U_SB_ETH_RX_CQ_INDEX),
+ (bp->rx_ticks/12) ? 0 : 1);
/* HC_INDEX_C_ETH_TX_CQ_CONS */
REG_WR8(bp, BAR_CSTRORM_INTMEM +
- CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
- C_SB_ETH_TX_CQ_INDEX),
+ CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
+ C_SB_ETH_TX_CQ_INDEX),
bp->tx_ticks/12);
REG_WR16(bp, BAR_CSTRORM_INTMEM +
- CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
- C_SB_ETH_TX_CQ_INDEX),
- bp->tx_ticks ? 0 : 1);
+ CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
+ C_SB_ETH_TX_CQ_INDEX),
+ (bp->tx_ticks/12) ? 0 : 1);
}
}
@@ -4525,6 +4954,9 @@ static void bnx2x_init_rx_rings(struct bnx2x *bp)
fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;
+ /* Mark queue as Rx */
+ fp->is_rx_queue = 1;
+
/* "next page" elements initialization */
/* SGE ring */
for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
@@ -4634,17 +5066,21 @@ static void bnx2x_init_tx_ring(struct bnx2x *bp)
struct bnx2x_fastpath *fp = &bp->fp[j];
for (i = 1; i <= NUM_TX_RINGS; i++) {
- struct eth_tx_bd *tx_bd =
- &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
+ struct eth_tx_next_bd *tx_next_bd =
+ &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
- tx_bd->addr_hi =
+ tx_next_bd->addr_hi =
cpu_to_le32(U64_HI(fp->tx_desc_mapping +
BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
- tx_bd->addr_lo =
+ tx_next_bd->addr_lo =
cpu_to_le32(U64_LO(fp->tx_desc_mapping +
BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
}
+ fp->tx_db.data.header.header = DOORBELL_HDR_DB_TYPE;
+ fp->tx_db.data.zero_fill1 = 0;
+ fp->tx_db.data.prod = 0;
+
fp->tx_pkt_prod = 0;
fp->tx_pkt_cons = 0;
fp->tx_bd_prod = 0;
@@ -4652,6 +5088,10 @@ static void bnx2x_init_tx_ring(struct bnx2x *bp)
fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
fp->tx_pkt = 0;
}
+
+ /* clean tx statistics */
+ for_each_rx_queue(bp, i)
+ bnx2x_fp(bp, i, tx_pkt) = 0;
}
static void bnx2x_init_sp_ring(struct bnx2x *bp)
@@ -4680,16 +5120,15 @@ static void bnx2x_init_context(struct bnx2x *bp)
{
int i;
- for_each_queue(bp, i) {
+ for_each_rx_queue(bp, i) {
struct eth_context *context = bnx2x_sp(bp, context[i].eth);
struct bnx2x_fastpath *fp = &bp->fp[i];
u8 cl_id = fp->cl_id;
- u8 sb_id = fp->sb_id;
context->ustorm_st_context.common.sb_index_numbers =
BNX2X_RX_SB_INDEX_NUM;
context->ustorm_st_context.common.clientId = cl_id;
- context->ustorm_st_context.common.status_block_id = sb_id;
+ context->ustorm_st_context.common.status_block_id = fp->sb_id;
context->ustorm_st_context.common.flags =
(USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT |
USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS);
@@ -4705,8 +5144,7 @@ static void bnx2x_init_context(struct bnx2x *bp)
U64_LO(fp->rx_desc_mapping);
if (!fp->disable_tpa) {
context->ustorm_st_context.common.flags |=
- (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |
- USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);
+ USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA;
context->ustorm_st_context.common.sge_buff_size =
(u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE,
(u32)0xffff);
@@ -4714,6 +5152,13 @@ static void bnx2x_init_context(struct bnx2x *bp)
U64_HI(fp->rx_sge_mapping);
context->ustorm_st_context.common.sge_page_base_lo =
U64_LO(fp->rx_sge_mapping);
+
+ context->ustorm_st_context.common.max_sges_for_packet =
+ SGE_PAGE_ALIGN(bp->dev->mtu) >> SGE_PAGE_SHIFT;
+ context->ustorm_st_context.common.max_sges_for_packet =
+ ((context->ustorm_st_context.common.
+ max_sges_for_packet + PAGES_PER_SGE - 1) &
+ (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
}
context->ustorm_ag_context.cdu_usage =
@@ -4721,24 +5166,27 @@ static void bnx2x_init_context(struct bnx2x *bp)
CDU_REGION_NUMBER_UCM_AG,
ETH_CONNECTION_TYPE);
+ context->xstorm_ag_context.cdu_reserved =
+ CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
+ CDU_REGION_NUMBER_XCM_AG,
+ ETH_CONNECTION_TYPE);
+ }
+
+ for_each_tx_queue(bp, i) {
+ struct bnx2x_fastpath *fp = &bp->fp[i];
+ struct eth_context *context =
+ bnx2x_sp(bp, context[i - bp->num_rx_queues].eth);
+
+ context->cstorm_st_context.sb_index_number =
+ C_SB_ETH_TX_CQ_INDEX;
+ context->cstorm_st_context.status_block_id = fp->sb_id;
+
context->xstorm_st_context.tx_bd_page_base_hi =
U64_HI(fp->tx_desc_mapping);
context->xstorm_st_context.tx_bd_page_base_lo =
U64_LO(fp->tx_desc_mapping);
- context->xstorm_st_context.db_data_addr_hi =
- U64_HI(fp->tx_prods_mapping);
- context->xstorm_st_context.db_data_addr_lo =
- U64_LO(fp->tx_prods_mapping);
- context->xstorm_st_context.statistics_data = (cl_id |
+ context->xstorm_st_context.statistics_data = (fp->cl_id |
XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
- context->cstorm_st_context.sb_index_number =
- C_SB_ETH_TX_CQ_INDEX;
- context->cstorm_st_context.status_block_id = sb_id;
-
- context->xstorm_ag_context.cdu_reserved =
- CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
- CDU_REGION_NUMBER_XCM_AG,
- ETH_CONNECTION_TYPE);
}
}
@@ -4776,18 +5224,6 @@ static void bnx2x_set_client_config(struct bnx2x *bp)
}
#endif
- if (bp->flags & TPA_ENABLE_FLAG) {
- tstorm_client.max_sges_for_packet =
- SGE_PAGE_ALIGN(tstorm_client.mtu) >> SGE_PAGE_SHIFT;
- tstorm_client.max_sges_for_packet =
- ((tstorm_client.max_sges_for_packet +
- PAGES_PER_SGE - 1) & (~(PAGES_PER_SGE - 1))) >>
- PAGES_PER_SGE_SHIFT;
-
- tstorm_client.config_flags |=
- TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING;
- }
-
for_each_queue(bp, i) {
tstorm_client.statistics_counter_id = bp->fp[i].cl_id;
@@ -4809,7 +5245,14 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
int mode = bp->rx_mode;
int mask = (1 << BP_L_ID(bp));
int func = BP_FUNC(bp);
+ int port = BP_PORT(bp);
int i;
+ /* All but management unicast packets should pass to the host as well */
+ u32 llh_mask =
+ NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
+ NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
+ NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
+ NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
DP(NETIF_MSG_IFUP, "rx mode %d mask 0x%x\n", mode, mask);
@@ -4833,6 +5276,8 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
tstorm_mac_filter.ucast_accept_all = mask;
tstorm_mac_filter.mcast_accept_all = mask;
tstorm_mac_filter.bcast_accept_all = mask;
+ /* pass management unicast packets as well */
+ llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
break;
default:
@@ -4840,6 +5285,10 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
break;
}
+ REG_WR(bp,
+ (port ? NIG_REG_LLH1_BRB1_DRV_MASK : NIG_REG_LLH0_BRB1_DRV_MASK),
+ llh_mask);
+
for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
REG_WR(bp, BAR_TSTRORM_INTMEM +
TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
@@ -4857,17 +5306,6 @@ static void bnx2x_init_internal_common(struct bnx2x *bp)
{
int i;
- if (bp->flags & TPA_ENABLE_FLAG) {
- struct tstorm_eth_tpa_exist tpa = {0};
-
- tpa.tpa_exist = 1;
-
- REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET,
- ((u32 *)&tpa)[0]);
- REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4,
- ((u32 *)&tpa)[1]);
- }
-
/* Zero this manually as its initialization is
currently missing in the initTool */
for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
@@ -4879,53 +5317,14 @@ static void bnx2x_init_internal_port(struct bnx2x *bp)
{
int port = BP_PORT(bp);
- REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
- REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
+ REG_WR(bp,
+ BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_U_OFFSET(port), BNX2X_BTR);
+ REG_WR(bp,
+ BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_C_OFFSET(port), BNX2X_BTR);
REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
}
-/* Calculates the sum of vn_min_rates.
- It's needed for further normalizing of the min_rates.
- Returns:
- sum of vn_min_rates.
- or
- 0 - if all the min_rates are 0.
- In the later case fainess algorithm should be deactivated.
- If not all min_rates are zero then those that are zeroes will be set to 1.
- */
-static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
-{
- int all_zero = 1;
- int port = BP_PORT(bp);
- int vn;
-
- bp->vn_weight_sum = 0;
- for (vn = VN_0; vn < E1HVN_MAX; vn++) {
- int func = 2*vn + port;
- u32 vn_cfg =
- SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
- u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
- FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
-
- /* Skip hidden vns */
- if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
- continue;
-
- /* If min rate is zero - set it to 1 */
- if (!vn_min_rate)
- vn_min_rate = DEF_MIN_RATE;
- else
- all_zero = 0;
-
- bp->vn_weight_sum += vn_min_rate;
- }
-
- /* ... only if all min rates are zeros - disable fairness */
- if (all_zero)
- bp->vn_weight_sum = 0;
-}
-
static void bnx2x_init_internal_func(struct bnx2x *bp)
{
struct tstorm_eth_function_common_config tstorm_config = {0};
@@ -4940,6 +5339,12 @@ static void bnx2x_init_internal_func(struct bnx2x *bp)
tstorm_config.config_flags = MULTI_FLAGS(bp);
tstorm_config.rss_result_mask = MULTI_MASK;
}
+
+ /* Enable TPA if needed */
+ if (bp->flags & TPA_ENABLE_FLAG)
+ tstorm_config.config_flags |=
+ TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
+
if (IS_E1HMF(bp))
tstorm_config.config_flags |=
TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
@@ -5051,6 +5456,14 @@ static void bnx2x_init_internal_func(struct bnx2x *bp)
USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id) + 4,
U64_HI(fp->rx_comp_mapping));
+ /* Next page */
+ REG_WR(bp, BAR_USTRORM_INTMEM +
+ USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id),
+ U64_LO(fp->rx_comp_mapping + BCM_PAGE_SIZE));
+ REG_WR(bp, BAR_USTRORM_INTMEM +
+ USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id) + 4,
+ U64_HI(fp->rx_comp_mapping + BCM_PAGE_SIZE));
+
REG_WR16(bp, BAR_USTRORM_INTMEM +
USTORM_MAX_AGG_SIZE_OFFSET(port, fp->cl_id),
max_agg_size);
@@ -5161,6 +5574,9 @@ static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
fp->index = i;
fp->cl_id = BP_L_ID(bp) + i;
fp->sb_id = fp->cl_id;
+ /* Suitable Rx and Tx SBs are served by the same client */
+ if (i >= bp->num_rx_queues)
+ fp->cl_id -= bp->num_rx_queues;
DP(NETIF_MSG_IFUP,
"queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d sb %d\n",
i, bp, fp->status_blk, fp->cl_id, fp->sb_id);
@@ -5193,6 +5609,11 @@ static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
mmiowb();
bnx2x_int_enable(bp);
+
+ /* Check for SPIO5 */
+ bnx2x_attn_int_deasserted0(bp,
+ REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
+ AEU_INPUTS_ATTN_BITS_SPIO5);
}
/* end of nic init */
@@ -5248,13 +5669,15 @@ static void bnx2x_gunzip_end(struct bnx2x *bp)
}
}
-static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
+static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
{
int n, rc;
/* check gzip header */
- if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
+ if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
+ BNX2X_ERR("Bad gzip header\n");
return -EINVAL;
+ }
n = 10;
@@ -5263,7 +5686,7 @@ static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
if (zbuf[3] & FNAME)
while ((zbuf[n++] != 0) && (n < len));
- bp->strm->next_in = zbuf + n;
+ bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
bp->strm->avail_in = len - n;
bp->strm->next_out = bp->gunzip_buf;
bp->strm->avail_out = FW_BUF_SIZE;
@@ -5385,8 +5808,8 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
msleep(50);
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
msleep(50);
- bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
- bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
+ bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
DP(NETIF_MSG_HW, "part2\n");
@@ -5450,8 +5873,8 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
msleep(50);
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
msleep(50);
- bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
- bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
+ bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
#ifndef BCM_ISCSI
/* set NIC mode */
REG_WR(bp, PRS_REG_NIC_MODE, 1);
@@ -5516,6 +5939,78 @@ static void bnx2x_reset_common(struct bnx2x *bp)
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
}
+static void bnx2x_init_pxp(struct bnx2x *bp)
+{
+ u16 devctl;
+ int r_order, w_order;
+
+ pci_read_config_word(bp->pdev,
+ bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
+ DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
+ w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
+ if (bp->mrrs == -1)
+ r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
+ else {
+ DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
+ r_order = bp->mrrs;
+ }
+
+ bnx2x_init_pxp_arb(bp, r_order, w_order);
+}
+
+static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
+{
+ u32 val;
+ u8 port;
+ u8 is_required = 0;
+
+ val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
+ SHARED_HW_CFG_FAN_FAILURE_MASK;
+
+ if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
+ is_required = 1;
+
+ /*
+ * The fan failure mechanism is usually related to the PHY type since
+ * the power consumption of the board is affected by the PHY. Currently,
+ * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
+ */
+ else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
+ for (port = PORT_0; port < PORT_MAX; port++) {
+ u32 phy_type =
+ SHMEM_RD(bp, dev_info.port_hw_config[port].
+ external_phy_config) &
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
+ is_required |=
+ ((phy_type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) ||
+ (phy_type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
+ (phy_type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481));
+ }
+
+ DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
+
+ if (is_required == 0)
+ return;
+
+ /* Fan failure is indicated by SPIO 5 */
+ bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
+ MISC_REGISTERS_SPIO_INPUT_HI_Z);
+
+ /* set to active low mode */
+ val = REG_RD(bp, MISC_REG_SPIO_INT);
+ val |= ((1 << MISC_REGISTERS_SPIO_5) <<
+ MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
+ REG_WR(bp, MISC_REG_SPIO_INT, val);
+
+ /* enable interrupt to signal the IGU */
+ val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
+ val |= (1 << MISC_REGISTERS_SPIO_5);
+ REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
+}
+
static int bnx2x_init_common(struct bnx2x *bp)
{
u32 val, i;
@@ -5526,7 +6021,7 @@ static int bnx2x_init_common(struct bnx2x *bp)
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
- bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END);
+ bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
if (CHIP_IS_E1H(bp))
REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
@@ -5534,14 +6029,14 @@ static int bnx2x_init_common(struct bnx2x *bp)
msleep(30);
REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
- bnx2x_init_block(bp, PXP_COMMON_START, PXP_COMMON_END);
+ bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
if (CHIP_IS_E1(bp)) {
/* enable HW interrupt from PXP on USDM overflow
bit 16 on INT_MASK_0 */
REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
}
- bnx2x_init_block(bp, PXP2_COMMON_START, PXP2_COMMON_END);
+ bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
bnx2x_init_pxp(bp);
#ifdef __BIG_ENDIAN
@@ -5587,60 +6082,60 @@ static int bnx2x_init_common(struct bnx2x *bp)
REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
- bnx2x_init_block(bp, DMAE_COMMON_START, DMAE_COMMON_END);
+ bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
/* clean the DMAE memory */
bp->dmae_ready = 1;
bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
- bnx2x_init_block(bp, TCM_COMMON_START, TCM_COMMON_END);
- bnx2x_init_block(bp, UCM_COMMON_START, UCM_COMMON_END);
- bnx2x_init_block(bp, CCM_COMMON_START, CCM_COMMON_END);
- bnx2x_init_block(bp, XCM_COMMON_START, XCM_COMMON_END);
+ bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
- bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END);
+ bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
/* soft reset pulse */
REG_WR(bp, QM_REG_SOFT_RESET, 1);
REG_WR(bp, QM_REG_SOFT_RESET, 0);
#ifdef BCM_ISCSI
- bnx2x_init_block(bp, TIMERS_COMMON_START, TIMERS_COMMON_END);
+ bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
#endif
- bnx2x_init_block(bp, DQ_COMMON_START, DQ_COMMON_END);
+ bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
if (!CHIP_REV_IS_SLOW(bp)) {
/* enable hw interrupt from doorbell Q */
REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
}
- bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
- bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
+ bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
/* set NIC mode */
REG_WR(bp, PRS_REG_NIC_MODE, 1);
if (CHIP_IS_E1H(bp))
REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
- bnx2x_init_block(bp, TSDM_COMMON_START, TSDM_COMMON_END);
- bnx2x_init_block(bp, CSDM_COMMON_START, CSDM_COMMON_END);
- bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
- bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
+ bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
- bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
- bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
- bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
- bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
+ bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
+ bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
+ bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
+ bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
- bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
- bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
- bnx2x_init_block(bp, CSEM_COMMON_START, CSEM_COMMON_END);
- bnx2x_init_block(bp, XSEM_COMMON_START, XSEM_COMMON_END);
+ bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
/* sync semi rtc */
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
@@ -5648,16 +6143,16 @@ static int bnx2x_init_common(struct bnx2x *bp)
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
0x80000000);
- bnx2x_init_block(bp, UPB_COMMON_START, UPB_COMMON_END);
- bnx2x_init_block(bp, XPB_COMMON_START, XPB_COMMON_END);
- bnx2x_init_block(bp, PBF_COMMON_START, PBF_COMMON_END);
+ bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
REG_WR(bp, SRC_REG_SOFT_RST, 1);
for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
REG_WR(bp, i, 0xc0cac01a);
/* TODO: replace with something meaningful */
}
- bnx2x_init_block(bp, SRCH_COMMON_START, SRCH_COMMON_END);
+ bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
REG_WR(bp, SRC_REG_SOFT_RST, 0);
if (sizeof(union cdu_context) != 1024)
@@ -5665,16 +6160,11 @@ static int bnx2x_init_common(struct bnx2x *bp)
printk(KERN_ALERT PFX "please adjust the size of"
" cdu_context(%ld)\n", (long)sizeof(union cdu_context));
- bnx2x_init_block(bp, CDU_COMMON_START, CDU_COMMON_END);
+ bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
val = (4 << 24) + (0 << 12) + 1024;
REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
- if (CHIP_IS_E1(bp)) {
- /* !!! fix pxp client crdit until excel update */
- REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264);
- REG_WR(bp, CDU_REG_CDU_DEBUG, 0);
- }
- bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);
+ bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
/* enable context validation interrupt from CFC */
REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
@@ -5682,20 +6172,20 @@ static int bnx2x_init_common(struct bnx2x *bp)
/* set the thresholds to prevent CFC/CDU race */
REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
- bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);
- bnx2x_init_block(bp, MISC_AEU_COMMON_START, MISC_AEU_COMMON_END);
+ bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
- /* PXPCS COMMON comes here */
+ bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
/* Reset PCIE errors for debug */
REG_WR(bp, 0x2814, 0xffffffff);
REG_WR(bp, 0x3820, 0xffffffff);
- /* EMAC0 COMMON comes here */
- /* EMAC1 COMMON comes here */
- /* DBU COMMON comes here */
- /* DBG COMMON comes here */
+ bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
- bnx2x_init_block(bp, NIG_COMMON_START, NIG_COMMON_END);
+ bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
if (CHIP_IS_E1H(bp)) {
REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
@@ -5741,27 +6231,12 @@ static int bnx2x_init_common(struct bnx2x *bp)
bp->port.need_hw_lock = 1;
break;
- case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
- /* Fan failure is indicated by SPIO 5 */
- bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
- MISC_REGISTERS_SPIO_INPUT_HI_Z);
-
- /* set to active low mode */
- val = REG_RD(bp, MISC_REG_SPIO_INT);
- val |= ((1 << MISC_REGISTERS_SPIO_5) <<
- MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
- REG_WR(bp, MISC_REG_SPIO_INT, val);
-
- /* enable interrupt to signal the IGU */
- val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
- val |= (1 << MISC_REGISTERS_SPIO_5);
- REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
- break;
-
default:
break;
}
+ bnx2x_setup_fan_failure_detection(bp);
+
/* clear PXP2 attentions */
REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
@@ -5781,6 +6256,7 @@ static int bnx2x_init_common(struct bnx2x *bp)
static int bnx2x_init_port(struct bnx2x *bp)
{
int port = BP_PORT(bp);
+ int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
u32 low, high;
u32 val;
@@ -5788,8 +6264,12 @@ static int bnx2x_init_port(struct bnx2x *bp)
REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
- /* Port PXP comes here */
- /* Port PXP2 comes here */
+ bnx2x_init_block(bp, PXP_BLOCK, init_stage);
+ bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
+
+ bnx2x_init_block(bp, TCM_BLOCK, init_stage);
+ bnx2x_init_block(bp, UCM_BLOCK, init_stage);
+ bnx2x_init_block(bp, CCM_BLOCK, init_stage);
#ifdef BCM_ISCSI
/* Port0 1
* Port1 385 */
@@ -5815,22 +6295,17 @@ static int bnx2x_init_port(struct bnx2x *bp)
REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
#endif
- /* Port CMs come here */
- bnx2x_init_block(bp, (port ? XCM_PORT1_START : XCM_PORT0_START),
- (port ? XCM_PORT1_END : XCM_PORT0_END));
+ bnx2x_init_block(bp, XCM_BLOCK, init_stage);
- /* Port QM comes here */
#ifdef BCM_ISCSI
REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);
- bnx2x_init_block(bp, func ? TIMERS_PORT1_START : TIMERS_PORT0_START,
- func ? TIMERS_PORT1_END : TIMERS_PORT0_END);
+ bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
#endif
- /* Port DQ comes here */
+ bnx2x_init_block(bp, DQ_BLOCK, init_stage);
- bnx2x_init_block(bp, (port ? BRB1_PORT1_START : BRB1_PORT0_START),
- (port ? BRB1_PORT1_END : BRB1_PORT0_END));
+ bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
if (CHIP_REV_IS_SLOW(bp) && !CHIP_IS_E1H(bp)) {
/* no pause for emulation and FPGA */
low = 0;
@@ -5854,26 +6329,22 @@ static int bnx2x_init_port(struct bnx2x *bp)
REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
- /* Port PRS comes here */
- /* Port TSDM comes here */
- /* Port CSDM comes here */
- /* Port USDM comes here */
- /* Port XSDM comes here */
+ bnx2x_init_block(bp, PRS_BLOCK, init_stage);
- bnx2x_init_block(bp, port ? TSEM_PORT1_START : TSEM_PORT0_START,
- port ? TSEM_PORT1_END : TSEM_PORT0_END);
- bnx2x_init_block(bp, port ? USEM_PORT1_START : USEM_PORT0_START,
- port ? USEM_PORT1_END : USEM_PORT0_END);
- bnx2x_init_block(bp, port ? CSEM_PORT1_START : CSEM_PORT0_START,
- port ? CSEM_PORT1_END : CSEM_PORT0_END);
- bnx2x_init_block(bp, port ? XSEM_PORT1_START : XSEM_PORT0_START,
- port ? XSEM_PORT1_END : XSEM_PORT0_END);
+ bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
+ bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
+ bnx2x_init_block(bp, USDM_BLOCK, init_stage);
+ bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
- /* Port UPB comes here */
- /* Port XPB comes here */
+ bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
+ bnx2x_init_block(bp, USEM_BLOCK, init_stage);
+ bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
+ bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
- bnx2x_init_block(bp, port ? PBF_PORT1_START : PBF_PORT0_START,
- port ? PBF_PORT1_END : PBF_PORT0_END);
+ bnx2x_init_block(bp, UPB_BLOCK, init_stage);
+ bnx2x_init_block(bp, XPB_BLOCK, init_stage);
+
+ bnx2x_init_block(bp, PBF_BLOCK, init_stage);
/* configure PBF to work without PAUSE mtu 9000 */
REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
@@ -5900,21 +6371,17 @@ static int bnx2x_init_port(struct bnx2x *bp)
REG_WR_DMAE(bp, SRC_REG_LASTFREE0 + func*4, wb_write, 2);
REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + func*4, 10);
- /* Port SRCH comes here */
#endif
- /* Port CDU comes here */
- /* Port CFC comes here */
+ bnx2x_init_block(bp, CDU_BLOCK, init_stage);
+ bnx2x_init_block(bp, CFC_BLOCK, init_stage);
if (CHIP_IS_E1(bp)) {
REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
}
- bnx2x_init_block(bp, port ? HC_PORT1_START : HC_PORT0_START,
- port ? HC_PORT1_END : HC_PORT0_END);
+ bnx2x_init_block(bp, HC_BLOCK, init_stage);
- bnx2x_init_block(bp, port ? MISC_AEU_PORT1_START :
- MISC_AEU_PORT0_START,
- port ? MISC_AEU_PORT1_END : MISC_AEU_PORT0_END);
+ bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
/* init aeu_mask_attn_func_0/1:
* - SF mode: bits 3-7 are masked. only bits 0-2 are in use
* - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
@@ -5922,14 +6389,13 @@ static int bnx2x_init_port(struct bnx2x *bp)
REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
(IS_E1HMF(bp) ? 0xF7 : 0x7));
- /* Port PXPCS comes here */
- /* Port EMAC0 comes here */
- /* Port EMAC1 comes here */
- /* Port DBU comes here */
- /* Port DBG comes here */
+ bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
+ bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
+ bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
+ bnx2x_init_block(bp, DBU_BLOCK, init_stage);
+ bnx2x_init_block(bp, DBG_BLOCK, init_stage);
- bnx2x_init_block(bp, port ? NIG_PORT1_START : NIG_PORT0_START,
- port ? NIG_PORT1_END : NIG_PORT0_END);
+ bnx2x_init_block(bp, NIG_BLOCK, init_stage);
REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
@@ -5938,9 +6404,6 @@ static int bnx2x_init_port(struct bnx2x *bp)
REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
(IS_E1HMF(bp) ? 0x1 : 0x2));
- /* support pause requests from USDM, TSDM and BRB */
- REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 + port*4, 0x7);
-
{
REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
@@ -5948,8 +6411,8 @@ static int bnx2x_init_port(struct bnx2x *bp)
}
}
- /* Port MCP comes here */
- /* Port DMAE comes here */
+ bnx2x_init_block(bp, MCP_BLOCK, init_stage);
+ bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
@@ -6057,9 +6520,15 @@ static int bnx2x_init_func(struct bnx2x *bp)
if (CHIP_IS_E1H(bp)) {
- for (i = 0; i < 9; i++)
- bnx2x_init_block(bp,
- cm_start[func][i], cm_end[func][i]);
+ bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
+ bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
+ bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
+ bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
+ bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
+ bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
+ bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
+ bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
+ bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
@@ -6072,7 +6541,7 @@ static int bnx2x_init_func(struct bnx2x *bp)
REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
}
- bnx2x_init_block(bp, hc_limits[func][0], hc_limits[func][1]);
+ bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
/* Reset PCIE errors for debug */
REG_WR(bp, 0x2114, 0xffffffff);
@@ -6090,7 +6559,9 @@ static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
bp->dmae_ready = 0;
mutex_init(&bp->dmae_mutex);
- bnx2x_gunzip_init(bp);
+ rc = bnx2x_gunzip_init(bp);
+ if (rc)
+ return rc;
switch (load_code) {
case FW_MSG_CODE_DRV_LOAD_COMMON:
@@ -6124,11 +6595,8 @@ static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
bp->fw_drv_pulse_wr_seq =
(SHMEM_RD(bp, func_mb[func].drv_pulse_mb) &
DRV_PULSE_SEQ_MASK);
- bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
- DP(BNX2X_MSG_MCP, "drv_pulse 0x%x func_stx 0x%x\n",
- bp->fw_drv_pulse_wr_seq, bp->func_stx);
- } else
- bp->func_stx = 0;
+ DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
+ }
/* this needs to be done before gunzip end */
bnx2x_zero_def_sb(bp);
@@ -6141,44 +6609,6 @@ init_hw_err:
return rc;
}
-/* send the MCP a request, block until there is a reply */
-u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
-{
- int func = BP_FUNC(bp);
- u32 seq = ++bp->fw_seq;
- u32 rc = 0;
- u32 cnt = 1;
- u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
-
- SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
- DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
-
- do {
- /* let the FW do it's magic ... */
- msleep(delay);
-
- rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
-
- /* Give the FW up to 2 second (200*10ms) */
- } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));
-
- DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
- cnt*delay, rc, seq);
-
- /* is this a reply to our command? */
- if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
- rc &= FW_MSG_CODE_MASK;
-
- } else {
- /* FW BUG! */
- BNX2X_ERR("FW failed to respond!\n");
- bnx2x_fw_dump(bp);
- rc = 0;
- }
-
- return rc;
-}
-
static void bnx2x_free_mem(struct bnx2x *bp)
{
@@ -6208,8 +6638,7 @@ static void bnx2x_free_mem(struct bnx2x *bp)
/* status blocks */
BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
bnx2x_fp(bp, i, status_blk_mapping),
- sizeof(struct host_status_block) +
- sizeof(struct eth_tx_db_data));
+ sizeof(struct host_status_block));
}
/* Rx */
for_each_rx_queue(bp, i) {
@@ -6238,7 +6667,7 @@ static void bnx2x_free_mem(struct bnx2x *bp)
BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
bnx2x_fp(bp, i, tx_desc_mapping),
- sizeof(struct eth_tx_bd) * NUM_TX_BD);
+ sizeof(union eth_tx_bd_types) * NUM_TX_BD);
}
/* end of fastpath */
@@ -6289,8 +6718,7 @@ static int bnx2x_alloc_mem(struct bnx2x *bp)
/* status blocks */
BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk),
&bnx2x_fp(bp, i, status_blk_mapping),
- sizeof(struct host_status_block) +
- sizeof(struct eth_tx_db_data));
+ sizeof(struct host_status_block));
}
/* Rx */
for_each_rx_queue(bp, i) {
@@ -6317,19 +6745,12 @@ static int bnx2x_alloc_mem(struct bnx2x *bp)
/* Tx */
for_each_tx_queue(bp, i) {
- bnx2x_fp(bp, i, hw_tx_prods) =
- (void *)(bnx2x_fp(bp, i, status_blk) + 1);
-
- bnx2x_fp(bp, i, tx_prods_mapping) =
- bnx2x_fp(bp, i, status_blk_mapping) +
- sizeof(struct host_status_block);
-
/* fastpath tx rings: tx_buf tx_desc */
BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
sizeof(struct sw_tx_bd) * NUM_TX_BD);
BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
&bnx2x_fp(bp, i, tx_desc_mapping),
- sizeof(struct eth_tx_bd) * NUM_TX_BD);
+ sizeof(union eth_tx_bd_types) * NUM_TX_BD);
}
/* end of fastpath */
@@ -6506,7 +6927,12 @@ static int bnx2x_req_msix_irqs(struct bnx2x *bp)
for_each_queue(bp, i) {
struct bnx2x_fastpath *fp = &bp->fp[i];
- sprintf(fp->name, "%s.fp%d", bp->dev->name, i);
+ if (i < bp->num_rx_queues)
+ sprintf(fp->name, "%s-rx-%d", bp->dev->name, i);
+ else
+ sprintf(fp->name, "%s-tx-%d",
+ bp->dev->name, i - bp->num_rx_queues);
+
rc = request_irq(bp->msix_table[i + offset].vector,
bnx2x_msix_fp_int, 0, fp->name, fp);
if (rc) {
@@ -6519,16 +6945,11 @@ static int bnx2x_req_msix_irqs(struct bnx2x *bp)
}
i = BNX2X_NUM_QUEUES(bp);
- if (is_multi(bp))
- printk(KERN_INFO PFX
- "%s: using MSI-X IRQs: sp %d fp %d - %d\n",
- bp->dev->name, bp->msix_table[0].vector,
- bp->msix_table[offset].vector,
- bp->msix_table[offset + i - 1].vector);
- else
- printk(KERN_INFO PFX "%s: using MSI-X IRQs: sp %d fp %d\n",
- bp->dev->name, bp->msix_table[0].vector,
- bp->msix_table[offset + i - 1].vector);
+ printk(KERN_INFO PFX "%s: using MSI-X IRQs: sp %d fp[%d] %d"
+ " ... fp[%d] %d\n",
+ bp->dev->name, bp->msix_table[0].vector,
+ 0, bp->msix_table[offset].vector,
+ i - 1, bp->msix_table[offset + i - 1].vector);
return 0;
}
@@ -6583,7 +7004,12 @@ static void bnx2x_napi_disable(struct bnx2x *bp)
static void bnx2x_netif_start(struct bnx2x *bp)
{
- if (atomic_dec_and_test(&bp->intr_sem)) {
+ int intr_sem;
+
+ intr_sem = atomic_dec_and_test(&bp->intr_sem);
+ smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
+
+ if (intr_sem) {
if (netif_running(bp->dev)) {
bnx2x_napi_enable(bp);
bnx2x_int_enable(bp);
@@ -6631,7 +7057,8 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set)
config->config_table[0].target_table_entry.flags = 0;
else
CAM_INVALIDATE(config->config_table[0]);
- config->config_table[0].target_table_entry.client_id = 0;
+ config->config_table[0].target_table_entry.clients_bit_vector =
+ cpu_to_le32(1 << BP_L_ID(bp));
config->config_table[0].target_table_entry.vlan_id = 0;
DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n",
@@ -6650,7 +7077,8 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set)
TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
else
CAM_INVALIDATE(config->config_table[1]);
- config->config_table[1].target_table_entry.client_id = 0;
+ config->config_table[1].target_table_entry.clients_bit_vector =
+ cpu_to_le32(1 << BP_L_ID(bp));
config->config_table[1].target_table_entry.vlan_id = 0;
bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
@@ -6663,11 +7091,6 @@ static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set)
struct mac_configuration_cmd_e1h *config =
(struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
- if (set && (bp->state != BNX2X_STATE_OPEN)) {
- DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
- return;
- }
-
/* CAM allocation for E1H
* unicasts: by func number
* multicast: 20+FUNC*20, 20 each
@@ -6684,7 +7107,8 @@ static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set)
swab16(*(u16 *)&bp->dev->dev_addr[2]);
config->config_table[0].lsb_mac_addr =
swab16(*(u16 *)&bp->dev->dev_addr[4]);
- config->config_table[0].client_id = BP_L_ID(bp);
+ config->config_table[0].clients_bit_vector =
+ cpu_to_le32(1 << BP_L_ID(bp));
config->config_table[0].vlan_id = 0;
config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
if (set)
@@ -6734,6 +7158,9 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
}
msleep(1);
+
+ if (bp->panic)
+ return -EIO;
}
/* timeout! */
@@ -6797,69 +7224,112 @@ static void bnx2x_alloc_napi(struct bnx2x *bp)
static int bnx2x_poll(struct net_device *dev, int *budget);
-static void bnx2x_set_int_mode(struct bnx2x *bp)
+static void bnx2x_set_int_mode_msix(struct bnx2x *bp, int *num_rx_queues_out,
+ int *num_tx_queues_out)
+{
+ int _num_rx_queues = 0, _num_tx_queues = 0;
+
+ switch (bp->multi_mode) {
+ case ETH_RSS_MODE_DISABLED:
+ _num_rx_queues = 1;
+ _num_tx_queues = 1;
+ break;
+
+ case ETH_RSS_MODE_REGULAR:
+ if (num_rx_queues)
+ _num_rx_queues = min_t(u32, num_rx_queues,
+ BNX2X_MAX_QUEUES(bp));
+ else
+ _num_rx_queues = min_t(u32, num_online_cpus(),
+ BNX2X_MAX_QUEUES(bp));
+
+ if (num_tx_queues)
+ _num_tx_queues = min_t(u32, num_tx_queues,
+ BNX2X_MAX_QUEUES(bp));
+ else
+ _num_tx_queues = min_t(u32, num_online_cpus(),
+ BNX2X_MAX_QUEUES(bp));
+
+ /* There must be not more Tx queues than Rx queues */
+ if (_num_tx_queues > _num_rx_queues) {
+ BNX2X_ERR("number of tx queues (%d) > "
+ "number of rx queues (%d)"
+ " defaulting to %d\n",
+ _num_tx_queues, _num_rx_queues,
+ _num_rx_queues);
+ _num_tx_queues = _num_rx_queues;
+ }
+ break;
+
+
+ default:
+ _num_rx_queues = 1;
+ _num_tx_queues = 1;
+ break;
+ }
+
+ *num_rx_queues_out = _num_rx_queues;
+ *num_tx_queues_out = _num_tx_queues;
+}
+
+static int bnx2x_set_int_mode(struct bnx2x *bp)
{
- int num_queues;
+ int rc = 0;
switch (int_mode) {
case INT_MODE_INTx:
case INT_MODE_MSI:
- num_queues = 1;
- bp->num_rx_queues = num_queues;
- bp->num_tx_queues = num_queues;
- DP(NETIF_MSG_IFUP,
- "set number of queues to %d\n", num_queues);
+ bp->num_rx_queues = 1;
+ bp->num_tx_queues = 1;
+ DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
break;
case INT_MODE_MSIX:
default:
- if (bp->multi_mode == ETH_RSS_MODE_REGULAR)
- num_queues = min_t(u32, num_online_cpus(),
- BNX2X_MAX_QUEUES(bp));
- else
- num_queues = 1;
- bp->num_rx_queues = num_queues;
- bp->num_tx_queues = num_queues;
- DP(NETIF_MSG_IFUP, "set number of rx queues to %d"
- " number of tx queues to %d\n",
+ /* Set interrupt mode according to bp->multi_mode value */
+ bnx2x_set_int_mode_msix(bp, &bp->num_rx_queues,
+ &bp->num_tx_queues);
+
+ DP(NETIF_MSG_IFUP, "set number of queues to: rx %d tx %d\n",
bp->num_rx_queues, bp->num_tx_queues);
/* if we can't use MSI-X we only need one fp,
* so try to enable MSI-X with the requested number of fp's
* and fallback to MSI or legacy INTx with one fp
*/
- if (bnx2x_enable_msix(bp)) {
+ rc = bnx2x_enable_msix(bp);
+ if (rc) {
/* failed to enable MSI-X */
- num_queues = 1;
- bp->num_rx_queues = num_queues;
- bp->num_tx_queues = num_queues;
if (bp->multi_mode)
BNX2X_ERR("Multi requested but failed to "
- "enable MSI-X set number of "
- "queues to %d\n", num_queues);
+ "enable msi-x (rx %d tx %d), "
+ "set number of queues to 1\n",
+ bp->num_rx_queues, bp->num_tx_queues);
+ bp->num_rx_queues = 1;
+ bp->num_tx_queues = 1;
}
break;
}
#if 0 /* not in RHEL */
bp->dev->real_num_tx_queues = bp->num_tx_queues;
#endif
+ return rc;
}
-static void bnx2x_set_rx_mode(struct net_device *dev);
/* must be called with rtnl_lock */
static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
{
u32 load_code;
- int i, rc = 0;
+ int i, rc;
+
#ifdef BNX2X_STOP_ON_ERROR
- DP(NETIF_MSG_IFUP, "enter load_mode %d\n", load_mode);
if (unlikely(bp->panic))
return -EPERM;
#endif
bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
- bnx2x_set_int_mode(bp);
+ rc = bnx2x_set_int_mode(bp);
if (bnx2x_alloc_mem(bp))
return -ENOMEM;
@@ -6870,17 +7340,6 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
bnx2x_alloc_napi(bp);
-#ifdef BNX2X_STOP_ON_ERROR
- for_each_rx_queue(bp, i) {
- struct bnx2x_fastpath *fp = &bp->fp[i];
-
- fp->poll_no_work = 0;
- fp->poll_calls = 0;
- fp->poll_max_calls = 0;
- fp->poll_complete = 0;
- fp->poll_exit = 0;
- }
-#endif
bnx2x_napi_enable(bp);
if (bp->flags & USING_MSIX_FLAG) {
@@ -6890,6 +7349,8 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
goto load_error1;
}
} else {
+ /* Fall to INTx if failed to enable MSI-X due to lack of
+ memory (in bnx2x_set_int_mode()) */
if ((rc != -ENOMEM) && (int_mode != INT_MODE_INTx))
bnx2x_enable_msi(bp);
bnx2x_ack_int(bp);
@@ -6958,6 +7419,12 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
/* Setup NIC internals and enable interrupts */
bnx2x_nic_init(bp, load_code);
+ if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) &&
+ (bp->common.shmem2_base))
+ SHMEM2_WR(bp, dcc_support,
+ (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
+ SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
+
/* Send LOAD_DONE command to MCP */
if (!BP_NOMCP(bp)) {
load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
@@ -6973,7 +7440,12 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
rc = bnx2x_setup_leading(bp);
if (rc) {
BNX2X_ERR("Setup leading failed!\n");
+#ifndef BNX2X_STOP_ON_ERROR
goto load_error3;
+#else
+ bp->panic = 1;
+ return -EBUSY;
+#endif
}
if (CHIP_IS_E1H(bp))
@@ -6982,17 +7454,18 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
bp->state = BNX2X_STATE_DISABLED;
}
- if (bp->state == BNX2X_STATE_OPEN)
+ if (bp->state == BNX2X_STATE_OPEN) {
for_each_nondefault_queue(bp, i) {
rc = bnx2x_setup_multi(bp, i);
if (rc)
goto load_error3;
}
- if (CHIP_IS_E1(bp))
- bnx2x_set_mac_addr_e1(bp, 1);
- else
- bnx2x_set_mac_addr_e1h(bp, 1);
+ if (CHIP_IS_E1(bp))
+ bnx2x_set_mac_addr_e1(bp, 1);
+ else
+ bnx2x_set_mac_addr_e1h(bp, 1);
+ }
if (bp->port.pmf)
bnx2x_initial_phy_init(bp, load_mode);
@@ -7000,14 +7473,19 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
/* Start fast path */
switch (load_mode) {
case LOAD_NORMAL:
- /* Tx queue should be only reenabled */
- netif_wake_queue(bp->dev);
+ if (bp->state == BNX2X_STATE_OPEN) {
+ /* Tx queue should be only reenabled */
+ netif_wake_queue(bp->dev);
+ }
/* Initialize the receive filter. */
bnx2x_set_rx_mode(bp->dev);
break;
case LOAD_OPEN:
netif_start_queue(bp->dev);
+ if (bp->state != BNX2X_STATE_OPEN)
+ netif_tx_disable(bp->dev);
+
/* Initialize the receive filter. */
bnx2x_set_rx_mode(bp->dev);
break;
@@ -7204,9 +7682,11 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
+ /* Set "drop all" */
bp->rx_mode = BNX2X_RX_MODE_NONE;
bnx2x_set_storm_rx_mode(bp);
+ /* Disable HW interrupts, NAPI and Tx */
bnx2x_netif_stop(bp, 1);
del_timer_sync(&bp->timer);
@@ -7270,17 +7750,17 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
for (i = 0; i < MC_HASH_SIZE; i++)
REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
+
+ REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
}
if (unload_mode == UNLOAD_NORMAL)
reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
- else if (bp->flags & NO_WOL_FLAG) {
+ else if (bp->flags & NO_WOL_FLAG)
reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
- if (CHIP_IS_E1H(bp))
- REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
- } else if (bp->wol) {
+ else if (bp->wol) {
u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
u8 *mac_addr = bp->dev->dev_addr;
u32 val;
@@ -7581,8 +8061,10 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
bp->common.flash_size, bp->common.flash_size);
bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
+ bp->common.shmem2_base = REG_RD(bp, MISC_REG_GENERIC_CR_0);
bp->link_params.shmem_base = bp->common.shmem_base;
- BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
+ BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
+ bp->common.shmem_base, bp->common.shmem2_base);
if (!bp->common.shmem_base ||
(bp->common.shmem_base < 0xA0000) ||
@@ -8136,22 +8618,33 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
bp->mf_config =
SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
- val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) &
+ val = (SHMEM_RD(bp, mf_cfg.func_mf_config[FUNC_0].e1hov_tag) &
FUNC_MF_CFG_E1HOV_TAG_MASK);
- if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
-
- bp->e1hov = val;
+ if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
bp->e1hmf = 1;
- BNX2X_DEV_INFO("MF mode E1HOV for func %d is %d "
- "(0x%04x)\n",
- func, bp->e1hov, bp->e1hov);
- } else {
- BNX2X_DEV_INFO("single function mode\n");
- if (BP_E1HVN(bp)) {
+ BNX2X_DEV_INFO("%s function mode\n",
+ IS_E1HMF(bp) ? "multi" : "single");
+
+ if (IS_E1HMF(bp)) {
+ val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].
+ e1hov_tag) &
+ FUNC_MF_CFG_E1HOV_TAG_MASK);
+ if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
+ bp->e1hov = val;
+ BNX2X_DEV_INFO("E1HOV for func %d is %d "
+ "(0x%04x)\n",
+ func, bp->e1hov, bp->e1hov);
+ } else {
BNX2X_ERR("!!! No valid E1HOV for func %d,"
" aborting\n", func);
rc = -EPERM;
}
+ } else {
+ if (BP_E1HVN(bp)) {
+ BNX2X_ERR("!!! VN %d in single function mode,"
+ " aborting\n", BP_E1HVN(bp));
+ rc = -EPERM;
+ }
}
}
@@ -8201,6 +8694,7 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
/* Disable interrupt handling until HW is initialized */
atomic_set(&bp->intr_sem, 1);
+ smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
mutex_init(&bp->port.phy_mutex);
@@ -8243,6 +8737,11 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
#endif
}
+ if (CHIP_IS_E1(bp))
+ bp->dropless_fc = 0;
+ else
+ bp->dropless_fc = dropless_fc;
+
bp->mrrs = mrrs;
bp->tx_ring_size = MAX_TX_AVAIL;
@@ -8499,50 +8998,15 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
return 0;
}
-#define PHY_FW_VER_LEN 10
-
-static void bnx2x_get_drvinfo(struct net_device *dev,
- struct ethtool_drvinfo *info)
-{
- struct bnx2x *bp = netdev_priv(dev);
- u8 phy_fw_ver[PHY_FW_VER_LEN];
-
- strcpy(info->driver, DRV_MODULE_NAME);
- strcpy(info->version, DRV_MODULE_VERSION);
-
- phy_fw_ver[0] = '\0';
- if (bp->port.pmf) {
- bnx2x_acquire_phy_lock(bp);
- bnx2x_get_ext_phy_fw_version(&bp->link_params,
- (bp->state != BNX2X_STATE_CLOSED),
- phy_fw_ver, PHY_FW_VER_LEN);
- bnx2x_release_phy_lock(bp);
- }
-
- snprintf(info->fw_version, 32, "BC:%d.%d.%d%s%s",
- (bp->common.bc_ver & 0xff0000) >> 16,
- (bp->common.bc_ver & 0xff00) >> 8,
- (bp->common.bc_ver & 0xff),
- ((phy_fw_ver[0] != '\0') ? " PHY:" : ""), phy_fw_ver);
- strcpy(info->bus_info, pci_name(bp->pdev));
- info->n_stats = BNX2X_NUM_STATS;
- info->testinfo_len = BNX2X_NUM_TESTS;
- info->eedump_len = bp->common.flash_size;
- info->regdump_len = 0;
-}
-
#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
static int bnx2x_get_regs_len(struct net_device *dev)
{
- static u32 regdump_len;
struct bnx2x *bp = netdev_priv(dev);
+ int regdump_len = 0;
int i;
- if (regdump_len)
- return regdump_len;
-
if (CHIP_IS_E1(bp)) {
for (i = 0; i < REGS_COUNT; i++)
if (IS_E1_ONLINE(reg_addrs[i].info))
@@ -8609,6 +9073,38 @@ static void bnx2x_get_regs(struct net_device *dev,
}
}
+#define PHY_FW_VER_LEN 10
+
+static void bnx2x_get_drvinfo(struct net_device *dev,
+ struct ethtool_drvinfo *info)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+ u8 phy_fw_ver[PHY_FW_VER_LEN];
+
+ strcpy(info->driver, DRV_MODULE_NAME);
+ strcpy(info->version, DRV_MODULE_VERSION);
+
+ phy_fw_ver[0] = '\0';
+ if (bp->port.pmf) {
+ bnx2x_acquire_phy_lock(bp);
+ bnx2x_get_ext_phy_fw_version(&bp->link_params,
+ (bp->state != BNX2X_STATE_CLOSED),
+ phy_fw_ver, PHY_FW_VER_LEN);
+ bnx2x_release_phy_lock(bp);
+ }
+
+ snprintf(info->fw_version, 32, "BC:%d.%d.%d%s%s",
+ (bp->common.bc_ver & 0xff0000) >> 16,
+ (bp->common.bc_ver & 0xff00) >> 8,
+ (bp->common.bc_ver & 0xff),
+ ((phy_fw_ver[0] != '\0') ? " PHY:" : ""), phy_fw_ver);
+ strcpy(info->bus_info, pci_name(bp->pdev));
+ info->n_stats = BNX2X_NUM_STATS;
+ info->testinfo_len = BNX2X_NUM_TESTS;
+ info->eedump_len = bp->common.flash_size;
+ info->regdump_len = bnx2x_get_regs_len(dev);
+}
+
static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
struct bnx2x *bp = netdev_priv(dev);
@@ -8674,6 +9170,13 @@ static int bnx2x_nway_reset(struct net_device *dev)
return 0;
}
+static u32 bnx2x_get_link(struct net_device *dev)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ return bp->link_vars.link_up;
+}
+
static int bnx2x_get_eeprom_len(struct net_device *dev)
{
struct bnx2x *bp = netdev_priv(dev);
@@ -9092,18 +9595,19 @@ static int bnx2x_get_coalesce(struct net_device *dev,
return 0;
}
+#define BNX2X_MAX_COALES_TOUT (0xf0*12) /* Maximal coalescing timeout in us */
static int bnx2x_set_coalesce(struct net_device *dev,
struct ethtool_coalesce *coal)
{
struct bnx2x *bp = netdev_priv(dev);
bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
- if (bp->rx_ticks > 3000)
- bp->rx_ticks = 3000;
+ if (bp->rx_ticks > BNX2X_MAX_COALES_TOUT)
+ bp->rx_ticks = BNX2X_MAX_COALES_TOUT;
bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
- if (bp->tx_ticks > 0x3000)
- bp->tx_ticks = 0x3000;
+ if (bp->tx_ticks > BNX2X_MAX_COALES_TOUT)
+ bp->tx_ticks = BNX2X_MAX_COALES_TOUT;
if (netif_running(dev))
bnx2x_update_coalesce(bp);
@@ -9326,10 +9830,9 @@ static int bnx2x_test_registers(struct bnx2x *bp)
{ XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
{ XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
{ XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
- { NIG_REG_EGRESS_MNG0_FIFO, 20, 0xffffffff },
{ NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
-/* 20 */ { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
- { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
+ { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
+/* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
{ NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
{ NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
{ NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
@@ -9338,8 +9841,8 @@ static int bnx2x_test_registers(struct bnx2x *bp)
{ NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
{ NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
{ NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
-/* 30 */ { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
- { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
+ { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
+/* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
{ NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
{ NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
{ NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
@@ -9465,12 +9968,14 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
unsigned int pkt_size, num_pkts, i;
struct sk_buff *skb;
unsigned char *packet;
- struct bnx2x_fastpath *fp = &bp->fp[0];
+ struct bnx2x_fastpath *fp_rx = &bp->fp[0];
+ struct bnx2x_fastpath *fp_tx = &bp->fp[bp->num_rx_queues];
u16 tx_start_idx, tx_idx;
u16 rx_start_idx, rx_idx;
- u16 pkt_prod;
+ u16 pkt_prod, bd_prod;
struct sw_tx_bd *tx_buf;
- struct eth_tx_bd *tx_bd;
+ struct eth_tx_start_bd *tx_start_bd;
+ struct eth_tx_parse_bd *pbd = NULL;
dma_addr_t mapping;
union eth_rx_cqe *cqe;
u8 cqe_fp_flags;
@@ -9502,57 +10007,64 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
}
packet = skb_put(skb, pkt_size);
memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
- memset(packet + ETH_ALEN, 0, (ETH_HLEN - ETH_ALEN));
+ memset(packet + ETH_ALEN, 0, ETH_ALEN);
+ memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
for (i = ETH_HLEN; i < pkt_size; i++)
packet[i] = (unsigned char) (i & 0xff);
/* send the loopback packet */
num_pkts = 0;
- tx_start_idx = le16_to_cpu(*fp->tx_cons_sb);
- rx_start_idx = le16_to_cpu(*fp->rx_cons_sb);
+ tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
+ rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
- pkt_prod = fp->tx_pkt_prod++;
- tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
- tx_buf->first_bd = fp->tx_bd_prod;
+ pkt_prod = fp_tx->tx_pkt_prod++;
+ tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
+ tx_buf->first_bd = fp_tx->tx_bd_prod;
tx_buf->skb = skb;
+ tx_buf->flags = 0;
- tx_bd = &fp->tx_desc_ring[TX_BD(fp->tx_bd_prod)];
+ bd_prod = TX_BD(fp_tx->tx_bd_prod);
+ tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
mapping = pci_map_single(bp->pdev, skb->data,
skb_headlen(skb), PCI_DMA_TODEVICE);
- tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
- tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
- tx_bd->nbd = cpu_to_le16(1);
- tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
- tx_bd->vlan = cpu_to_le16(pkt_prod);
- tx_bd->bd_flags.as_bitfield = (ETH_TX_BD_FLAGS_START_BD |
- ETH_TX_BD_FLAGS_END_BD);
- tx_bd->general_data = ((UNICAST_ADDRESS <<
- ETH_TX_BD_ETH_ADDR_TYPE_SHIFT) | 1);
+ tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
+ tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
+ tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
+ tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
+ tx_start_bd->vlan = cpu_to_le16(pkt_prod);
+ tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
+ tx_start_bd->general_data = ((UNICAST_ADDRESS <<
+ ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT) | 1);
+
+ /* turn on parsing and get a BD */
+ bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
+ pbd = &fp_tx->tx_desc_ring[bd_prod].parse_bd;
+
+ memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
wmb();
- le16_add_cpu(&fp->hw_tx_prods->bds_prod, 1);
- mb(); /* FW restriction: must not reorder writing nbd and packets */
- le32_add_cpu(&fp->hw_tx_prods->packets_prod, 1);
- DOORBELL(bp, fp->index, 0);
+ fp_tx->tx_db.data.prod += 2;
+ barrier();
+ DOORBELL(bp, fp_tx->index - bp->num_rx_queues, fp_tx->tx_db.raw);
mmiowb();
num_pkts++;
- fp->tx_bd_prod++;
+ fp_tx->tx_bd_prod += 2; /* start + pbd */
bp->dev->trans_start = jiffies;
udelay(100);
- tx_idx = le16_to_cpu(*fp->tx_cons_sb);
+ tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
if (tx_idx != tx_start_idx + num_pkts)
goto test_loopback_exit;
- rx_idx = le16_to_cpu(*fp->rx_cons_sb);
+ rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
if (rx_idx != rx_start_idx + num_pkts)
goto test_loopback_exit;
- cqe = &fp->rx_comp_ring[RCQ_BD(fp->rx_comp_cons)];
+ cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
goto test_loopback_rx_exit;
@@ -9561,7 +10073,7 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
if (len != pkt_size)
goto test_loopback_rx_exit;
- rx_buf = &fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)];
+ rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
skb = rx_buf->skb;
skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
for (i = ETH_HLEN; i < pkt_size; i++)
@@ -9573,14 +10085,14 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
test_loopback_rx_exit:
bp->dev->last_rx = jiffies;
- fp->rx_bd_cons = NEXT_RX_IDX(fp->rx_bd_cons);
- fp->rx_bd_prod = NEXT_RX_IDX(fp->rx_bd_prod);
- fp->rx_comp_cons = NEXT_RCQ_IDX(fp->rx_comp_cons);
- fp->rx_comp_prod = NEXT_RCQ_IDX(fp->rx_comp_prod);
+ fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
+ fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
+ fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
+ fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
/* Update producers */
- bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
- fp->rx_sge_prod);
+ bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
+ fp_rx->rx_sge_prod);
test_loopback_exit:
bp->link_params.loopback_mode = LOOPBACK_NONE;
@@ -9637,7 +10149,7 @@ static int bnx2x_test_nvram(struct bnx2x *bp)
__be32 buf[0x350 / 4];
u8 *data = (u8 *)buf;
int i, rc;
- u32 magic, csum;
+ u32 magic, crc;
rc = bnx2x_nvram_read(bp, 0, data, 4);
if (rc) {
@@ -9662,10 +10174,10 @@ static int bnx2x_test_nvram(struct bnx2x *bp)
goto test_nvram_exit;
}
- csum = ether_crc_le(nvram_tbl[i].size, data);
- if (csum != CRC32_RESIDUAL) {
+ crc = ether_crc_le(nvram_tbl[i].size, data);
+ if (crc != CRC32_RESIDUAL) {
DP(NETIF_MSG_PROBE,
- "nvram_tbl[%d] csum value (0x%08x)\n", i, csum);
+ "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
rc = -ENODEV;
goto test_nvram_exit;
}
@@ -9723,8 +10235,15 @@ static void bnx2x_self_test(struct net_device *dev,
etest->flags &= ~ETH_TEST_FL_OFFLINE;
if (etest->flags & ETH_TEST_FL_OFFLINE) {
+ int port = BP_PORT(bp);
+ u32 val;
u8 link_up;
+ /* save current value of input enable for TX port IF */
+ val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
+ /* disable input for TX port IF */
+ REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
+
link_up = bp->link_vars.link_up;
bnx2x_nic_unload(bp, UNLOAD_NORMAL);
bnx2x_nic_load(bp, LOAD_DIAG);
@@ -9744,6 +10263,10 @@ static void bnx2x_self_test(struct net_device *dev,
etest->flags |= ETH_TEST_FL_FAILED;
bnx2x_nic_unload(bp, UNLOAD_NORMAL);
+
+ /* restore input for TX port IF */
+ REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
+
bnx2x_nic_load(bp, LOAD_NORMAL);
/* wait until link state is restored */
bnx2x_wait_for_link(bp, link_up);
@@ -9902,7 +10425,7 @@ static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
case ETH_SS_STATS:
if (is_multi(bp)) {
k = 0;
- for_each_queue(bp, i) {
+ for_each_rx_queue(bp, i) {
for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
sprintf(buf + (k + j)*ETH_GSTRING_LEN,
bnx2x_q_stats_arr[j].string, i);
@@ -9936,7 +10459,7 @@ static int bnx2x_get_stats_count(struct net_device *dev)
int i, num_stats;
if (is_multi(bp)) {
- num_stats = BNX2X_NUM_Q_STATS * BNX2X_NUM_QUEUES(bp);
+ num_stats = BNX2X_NUM_Q_STATS * bp->num_rx_queues;
if (!IS_E1HMF_MODE_STAT(bp))
num_stats += BNX2X_NUM_STATS;
} else {
@@ -9961,7 +10484,7 @@ static void bnx2x_get_ethtool_stats(struct net_device *dev,
if (is_multi(bp)) {
k = 0;
- for_each_queue(bp, i) {
+ for_each_rx_queue(bp, i) {
hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
if (bnx2x_q_stats_arr[j].size == 0) {
@@ -10074,7 +10597,7 @@ static struct ethtool_ops bnx2x_ethtool_ops = {
.get_msglevel = bnx2x_get_msglevel,
.set_msglevel = bnx2x_set_msglevel,
.nway_reset = bnx2x_nway_reset,
- .get_link = ethtool_op_get_link,
+ .get_link = bnx2x_get_link,
.get_eeprom_len = bnx2x_get_eeprom_len,
.get_eeprom = bnx2x_get_eeprom,
.set_eeprom = bnx2x_set_eeprom,
@@ -10177,15 +10700,11 @@ static int bnx2x_poll(struct net_device *dev, int *budget)
goto poll_panic;
#endif
- prefetch(fp->tx_buf_ring[TX_BD(fp->tx_pkt_cons)].skb);
prefetch(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb);
prefetch((char *)(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb) + 256);
bnx2x_update_fpsb_idx(fp);
- if (bnx2x_has_tx_work(fp))
- bnx2x_tx_int(fp);
-
if (bnx2x_has_rx_work(fp)) {
work_done = bnx2x_rx_int(fp, work_to_do);
@@ -10193,11 +10712,11 @@ static int bnx2x_poll(struct net_device *dev, int *budget)
dev->quota -= work_done;
}
- /* BNX2X_HAS_WORK() reads the status block, thus we need to
+ /* bnx2x_has_rx_work() reads the status block, thus we need to
* ensure that status block indices have been actually read
- * (bnx2x_update_fpsb_idx) prior to this check (BNX2X_HAS_WORK)
+ * (bnx2x_update_fpsb_idx) prior to this check (bnx2x_has_rx_work)
* so that we won't write the "newer" value of the status block to IGU
- * (if there was a DMA right after BNX2X_HAS_WORK and
+ * (if there was a DMA right after bnx2x_has_rx_work and
* if there is no rmb, the memory reading (bnx2x_update_fpsb_idx)
* may be postponed to right before bnx2x_ack_sb). In this case
* there will never be another interrupt until there is another update
@@ -10205,7 +10724,7 @@ static int bnx2x_poll(struct net_device *dev, int *budget)
*/
rmb();
- if (!BNX2X_HAS_WORK(fp)) {
+ if (!bnx2x_has_rx_work(fp)) {
#ifdef BNX2X_STOP_ON_ERROR
poll_panic:
#endif
@@ -10229,10 +10748,11 @@ poll_panic:
*/
static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
struct bnx2x_fastpath *fp,
- struct eth_tx_bd **tx_bd, u16 hlen,
+ struct sw_tx_bd *tx_buf,
+ struct eth_tx_start_bd **tx_bd, u16 hlen,
u16 bd_prod, int nbd)
{
- struct eth_tx_bd *h_tx_bd = *tx_bd;
+ struct eth_tx_start_bd *h_tx_bd = *tx_bd;
struct eth_tx_bd *d_tx_bd;
dma_addr_t mapping;
int old_len = le16_to_cpu(h_tx_bd->nbytes);
@@ -10248,7 +10768,7 @@ static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
/* now get a new data BD
* (after the pbd) and fill it */
bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
- d_tx_bd = &fp->tx_desc_ring[bd_prod];
+ d_tx_bd = &fp->tx_desc_ring[bd_prod].reg_bd;
mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
le32_to_cpu(h_tx_bd->addr_lo)) + hlen;
@@ -10256,17 +10776,16 @@ static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
- d_tx_bd->vlan = 0;
- /* this marks the BD as one that has no individual mapping
- * the FW ignores this flag in a BD not marked start
- */
- d_tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO;
+
+ /* this marks the BD as one that has no individual mapping */
+ tx_buf->flags |= BNX2X_TSO_SPLIT_BD;
+
DP(NETIF_MSG_TX_QUEUED,
"TSO split data size is %d (%x:%x)\n",
d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);
- /* update tx_bd for marking the last BD flag */
- *tx_bd = d_tx_bd;
+ /* update tx_bd */
+ *tx_bd = (struct eth_tx_start_bd *)d_tx_bd;
return bd_prod;
}
@@ -10401,20 +10920,21 @@ exit_lbl:
static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct bnx2x *bp = netdev_priv(dev);
- struct bnx2x_fastpath *fp;
+ struct bnx2x_fastpath *fp, *fp_stat;
#if 0 /* not in RHEL */
struct netdev_queue *txq;
#endif
struct sw_tx_bd *tx_buf;
- struct eth_tx_bd *tx_bd;
+ struct eth_tx_start_bd *tx_start_bd;
+ struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL;
struct eth_tx_parse_bd *pbd = NULL;
u16 pkt_prod, bd_prod;
int nbd, fp_index;
dma_addr_t mapping;
u32 xmit_type = bnx2x_xmit_type(bp, skb);
- int vlan_off = (bp->e1hov ? 4 : 0);
int i;
u8 hlen = 0;
+ __le16 pkt_size = 0;
#ifdef BNX2X_STOP_ON_ERROR
if (unlikely(bp->panic))
@@ -10426,10 +10946,12 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
txq = netdev_get_tx_queue(dev, fp_index);
#endif
fp_index = (smp_processor_id() % bp->num_tx_queues);
- fp = &bp->fp[fp_index];
+
+ fp = &bp->fp[fp_index + bp->num_rx_queues];
+ fp_stat = &bp->fp[fp_index];
if (unlikely(bnx2x_tx_avail(fp) < (skb_shinfo(skb)->nr_frags + 3))) {
- fp->eth_q_stats.driver_xoff++,
+ fp_stat->eth_q_stats.driver_xoff++;
netif_stop_queue(dev);
BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
return NETDEV_TX_BUSY;
@@ -10458,7 +10980,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
/*
Please read carefully. First we use one BD which we mark as start,
- then for TSO or xsum we have a parsing info BD,
+ then we have a parsing info BD (used for TSO or xsum),
and only then we have the rest of the TSO BDs.
(don't forget to mark the last one as last,
and to unmap only AFTER you write to the BD ...)
@@ -10470,42 +10992,40 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
/* get a tx_buf and first BD */
tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
- tx_bd = &fp->tx_desc_ring[bd_prod];
+ tx_start_bd = &fp->tx_desc_ring[bd_prod].start_bd;
- tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
- tx_bd->general_data = (UNICAST_ADDRESS <<
- ETH_TX_BD_ETH_ADDR_TYPE_SHIFT);
+ tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
+ tx_start_bd->general_data = (UNICAST_ADDRESS <<
+ ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
/* header nbd */
- tx_bd->general_data |= (1 << ETH_TX_BD_HDR_NBDS_SHIFT);
+ tx_start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
/* remember the first BD of the packet */
tx_buf->first_bd = fp->tx_bd_prod;
tx_buf->skb = skb;
+ tx_buf->flags = 0;
DP(NETIF_MSG_TX_QUEUED,
"sending pkt %u @%p next_idx %u bd %u @%p\n",
- pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_bd);
+ pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd);
#ifdef BCM_VLAN
if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb) &&
(bp->flags & HW_VLAN_TX_FLAG)) {
- tx_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb));
- tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
- vlan_off += 4;
+ tx_start_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb));
+ tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
} else
#endif
- tx_bd->vlan = cpu_to_le16(pkt_prod);
+ tx_start_bd->vlan = cpu_to_le16(pkt_prod);
- if (xmit_type) {
- /* turn on parsing and get a BD */
- bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
- pbd = (void *)&fp->tx_desc_ring[bd_prod];
+ /* turn on parsing and get a BD */
+ bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
+ pbd = &fp->tx_desc_ring[bd_prod].parse_bd;
- memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
- }
+ memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
if (xmit_type & XMIT_CSUM) {
- hlen = (skb_network_header(skb) - skb->data + vlan_off) / 2;
+ hlen = (skb_network_header(skb) - skb->data) / 2;
/* for now NS flag is not used in Linux */
pbd->global_data =
@@ -10518,15 +11038,16 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
hlen += pbd->ip_hlen + tcp_hdrlen(skb) / 2;
pbd->total_hlen = cpu_to_le16(hlen);
- hlen = hlen*2 - vlan_off;
+ hlen = hlen*2;
- tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_TCP_CSUM;
+ tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
if (xmit_type & XMIT_CSUM_V4)
- tx_bd->bd_flags.as_bitfield |=
+ tx_start_bd->bd_flags.as_bitfield |=
ETH_TX_BD_FLAGS_IP_CSUM;
else
- tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IPV6;
+ tx_start_bd->bd_flags.as_bitfield |=
+ ETH_TX_BD_FLAGS_IPV6;
if (xmit_type & XMIT_CSUM_TCP) {
pbd->tcp_pseudo_csum = swab16(tcp_hdr(skb)->check);
@@ -10534,13 +11055,11 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
} else {
s8 fix = SKB_CS_OFF(skb); /* signed! */
- pbd->global_data |= ETH_TX_PARSE_BD_CS_ANY_FLG;
- pbd->cs_offset = fix / 2;
+ pbd->global_data |= ETH_TX_PARSE_BD_UDP_CS_FLG;
DP(NETIF_MSG_TX_QUEUED,
- "hlen %d offset %d fix %d csum before fix %x\n",
- le16_to_cpu(pbd->total_hlen), pbd->cs_offset, fix,
- SKB_CS(skb));
+ "hlen %d fix %d csum before fix %x\n",
+ le16_to_cpu(pbd->total_hlen), fix, SKB_CS(skb));
/* HW bug: fixup the CSUM */
pbd->tcp_pseudo_csum =
@@ -10555,17 +11074,18 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
mapping = pci_map_single(bp->pdev, skb->data,
skb_headlen(skb), PCI_DMA_TODEVICE);
- tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
- tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
- nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL) ? 1 : 2);
- tx_bd->nbd = cpu_to_le16(nbd);
- tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
+ tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
+ tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
+ nbd = skb_shinfo(skb)->nr_frags + 2; /* start_bd + pbd + frags */
+ tx_start_bd->nbd = cpu_to_le16(nbd);
+ tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
+ pkt_size = tx_start_bd->nbytes;
DP(NETIF_MSG_TX_QUEUED, "first bd @%p addr (%x:%x) nbd %d"
" nbytes %d flags %x vlan %x\n",
- tx_bd, tx_bd->addr_hi, tx_bd->addr_lo, le16_to_cpu(tx_bd->nbd),
- le16_to_cpu(tx_bd->nbytes), tx_bd->bd_flags.as_bitfield,
- le16_to_cpu(tx_bd->vlan));
+ tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo,
+ le16_to_cpu(tx_start_bd->nbd), le16_to_cpu(tx_start_bd->nbytes),
+ tx_start_bd->bd_flags.as_bitfield, le16_to_cpu(tx_start_bd->vlan));
if (xmit_type & XMIT_GSO) {
@@ -10574,11 +11094,11 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
skb->len, hlen, skb_headlen(skb),
skb_shinfo(skb)->gso_size);
- tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
+ tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
if (unlikely(skb_headlen(skb) > hlen))
- bd_prod = bnx2x_tx_split(bp, fp, &tx_bd, hlen,
- bd_prod, ++nbd);
+ bd_prod = bnx2x_tx_split(bp, fp, tx_buf, &tx_start_bd,
+ hlen, bd_prod, ++nbd);
pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
pbd->tcp_send_seq = swab32(tcp_hdr(skb)->seq);
@@ -10599,33 +11119,31 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
}
+ tx_data_bd = (struct eth_tx_bd *)tx_start_bd;
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
- tx_bd = &fp->tx_desc_ring[bd_prod];
+ tx_data_bd = &fp->tx_desc_ring[bd_prod].reg_bd;
+ if (total_pkt_bd == NULL)
+ total_pkt_bd = &fp->tx_desc_ring[bd_prod].reg_bd;
mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
frag->size, PCI_DMA_TODEVICE);
- tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
- tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
- tx_bd->nbytes = cpu_to_le16(frag->size);
- tx_bd->vlan = cpu_to_le16(pkt_prod);
- tx_bd->bd_flags.as_bitfield = 0;
+ tx_data_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
+ tx_data_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
+ tx_data_bd->nbytes = cpu_to_le16(frag->size);
+ le16_add_cpu(&pkt_size, frag->size);
DP(NETIF_MSG_TX_QUEUED,
- "frag %d bd @%p addr (%x:%x) nbytes %d flags %x\n",
- i, tx_bd, tx_bd->addr_hi, tx_bd->addr_lo,
- le16_to_cpu(tx_bd->nbytes), tx_bd->bd_flags.as_bitfield);
+ "frag %d bd @%p addr (%x:%x) nbytes %d\n",
+ i, tx_data_bd, tx_data_bd->addr_hi, tx_data_bd->addr_lo,
+ le16_to_cpu(tx_data_bd->nbytes));
}
- /* now at last mark the BD as the last BD */
- tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_END_BD;
-
- DP(NETIF_MSG_TX_QUEUED, "last bd @%p flags %x\n",
- tx_bd, tx_bd->bd_flags.as_bitfield);
+ DP(NETIF_MSG_TX_QUEUED, "last bd @%p\n", tx_data_bd);
bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
@@ -10635,6 +11153,9 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
if (TX_BD_POFF(bd_prod) < nbd)
nbd++;
+ if (total_pkt_bd != NULL)
+ total_pkt_bd->total_pkt_bytes = pkt_size;
+
if (pbd)
DP(NETIF_MSG_TX_QUEUED,
"PBD @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u"
@@ -10654,10 +11175,9 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
*/
wmb();
- le16_add_cpu(&fp->hw_tx_prods->bds_prod, nbd);
- mb(); /* FW restriction: must not reorder writing nbd and packets */
- le32_add_cpu(&fp->hw_tx_prods->packets_prod, 1);
- DOORBELL(bp, fp->index, 0);
+ fp->tx_db.data.prod += nbd;
+ barrier();
+ DOORBELL(bp, fp->index - bp->num_rx_queues, fp->tx_db.raw);
mmiowb();
@@ -10665,15 +11185,15 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
dev->trans_start = jiffies;
if (unlikely(bnx2x_tx_avail(fp) < MAX_SKB_FRAGS + 3)) {
+ netif_stop_queue(dev);
/* We want bnx2x_tx_int to "see" the updated tx_bd_prod
if we put Tx into XOFF state. */
smp_mb();
- netif_stop_queue(dev);
- fp->eth_q_stats.driver_xoff++;
+ fp_stat->eth_q_stats.driver_xoff++;
if (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)
netif_wake_queue(dev);
}
- fp->tx_pkt++;
+ fp_stat->tx_pkt++;
return NETDEV_TX_OK;
}
@@ -10753,8 +11273,9 @@ static void bnx2x_set_rx_mode(struct net_device *dev)
cpu_to_le16(port);
config->config_table[i].
target_table_entry.flags = 0;
- config->config_table[i].
- target_table_entry.client_id = 0;
+ config->config_table[i].target_table_entry.
+ clients_bit_vector =
+ cpu_to_le32(1 << BP_L_ID(bp));
config->config_table[i].
target_table_entry.vlan_id = 0;
@@ -11145,34 +11666,214 @@ err_out:
return rc;
}
-static int __devinit bnx2x_get_pcie_width(struct bnx2x *bp)
+static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
+ int *width, int *speed)
{
u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
- val = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
- return val;
+ *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
+
+ /* return value of 1=2.5GHz 2=5GHz */
+ *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
}
-/* return value of 1=2.5GHz 2=5GHz */
-static int __devinit bnx2x_get_pcie_speed(struct bnx2x *bp)
+static int __devinit bnx2x_check_firmware(struct bnx2x *bp)
{
- u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
+ const struct firmware *firmware = bp->firmware;
+ struct bnx2x_fw_file_hdr *fw_hdr;
+ struct bnx2x_fw_file_section *sections;
+ u32 offset, len, num_ops;
+ u16 *ops_offsets;
+ int i;
+ const u8 *fw_ver;
- val = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
- return val;
+ if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
+ return -EINVAL;
+
+ fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
+ sections = (struct bnx2x_fw_file_section *)fw_hdr;
+
+ /* Make sure none of the offsets and sizes make us read beyond
+ * the end of the firmware data */
+ for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
+ offset = be32_to_cpu(sections[i].offset);
+ len = be32_to_cpu(sections[i].len);
+ if (offset + len > firmware->size) {
+ printk(KERN_ERR PFX "Section %d length is out of "
+ "bounds\n", i);
+ return -EINVAL;
+ }
+ }
+
+ /* Likewise for the init_ops offsets */
+ offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
+ ops_offsets = (u16 *)(firmware->data + offset);
+ num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
+
+ for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
+ if (be16_to_cpu(ops_offsets[i]) > num_ops) {
+ printk(KERN_ERR PFX "Section offset %d is out of "
+ "bounds\n", i);
+ return -EINVAL;
+ }
+ }
+
+ /* Check FW version */
+ offset = be32_to_cpu(fw_hdr->fw_version.offset);
+ fw_ver = firmware->data + offset;
+ if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
+ (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
+ (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
+ (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
+ printk(KERN_ERR PFX "Bad FW version:%d.%d.%d.%d."
+ " Should be %d.%d.%d.%d\n",
+ fw_ver[0], fw_ver[1], fw_ver[2],
+ fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
+ BCM_5710_FW_MINOR_VERSION,
+ BCM_5710_FW_REVISION_VERSION,
+ BCM_5710_FW_ENGINEERING_VERSION);
+ return -EINVAL;
+ }
+
+ return 0;
}
+static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
+{
+ const __be32 *source = (const __be32 *)_source;
+ u32 *target = (u32 *)_target;
+ u32 i;
+
+ for (i = 0; i < n/4; i++)
+ target[i] = be32_to_cpu(source[i]);
+}
+
+/*
+ Ops array is stored in the following format:
+ {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
+ */
+static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
+{
+ const __be32 *source = (const __be32 *)_source;
+ struct raw_op *target = (struct raw_op *)_target;
+ u32 i, j, tmp;
+
+ for (i = 0, j = 0; i < n/8; i++, j += 2) {
+ tmp = be32_to_cpu(source[j]);
+ target[i].op = (tmp >> 24) & 0xff;
+ target[i].offset = tmp & 0xffffff;
+ target[i].raw_data = be32_to_cpu(source[j+1]);
+ }
+}
+
+static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
+{
+ const __be16 *source = (const __be16 *)_source;
+ u16 *target = (u16 *)_target;
+ u32 i;
+
+ for (i = 0; i < n/2; i++)
+ target[i] = be16_to_cpu(source[i]);
+}
+
+#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
+ do { \
+ u32 len = be32_to_cpu(fw_hdr->arr.len); \
+ bp->arr = kmalloc(len, GFP_KERNEL); \
+ if (!bp->arr) { \
+ printk(KERN_ERR PFX "Failed to allocate %d bytes " \
+ "for "#arr"\n", len); \
+ goto lbl; \
+ } \
+ func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
+ (u8 *)bp->arr, len); \
+ } while (0)
+
+static int __devinit bnx2x_init_firmware(struct bnx2x *bp, struct device *dev)
+{
+ char fw_file_name[40] = {0};
+ struct bnx2x_fw_file_hdr *fw_hdr;
+ int rc, offset;
+
+ /* Create a FW file name */
+ if (CHIP_IS_E1(bp))
+ offset = sprintf(fw_file_name, FW_FILE_PREFIX_E1);
+ else
+ offset = sprintf(fw_file_name, FW_FILE_PREFIX_E1H);
+
+ sprintf(fw_file_name + offset, "%d.%d.%d.%d.fw",
+ BCM_5710_FW_MAJOR_VERSION,
+ BCM_5710_FW_MINOR_VERSION,
+ BCM_5710_FW_REVISION_VERSION,
+ BCM_5710_FW_ENGINEERING_VERSION);
+
+ printk(KERN_INFO PFX "Loading %s\n", fw_file_name);
+
+ rc = request_firmware(&bp->firmware, fw_file_name, dev);
+ if (rc) {
+ printk(KERN_ERR PFX "Can't load firmware file %s\n",
+ fw_file_name);
+ goto request_firmware_exit;
+ }
+
+ rc = bnx2x_check_firmware(bp);
+ if (rc) {
+ printk(KERN_ERR PFX "Corrupt firmware file %s\n", fw_file_name);
+ goto request_firmware_exit;
+ }
+
+ fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
+
+ /* Initialize the pointers to the init arrays */
+ /* Blob */
+ BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
+
+ /* Opcodes */
+ BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
+
+ /* Offsets */
+ BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
+ be16_to_cpu_n);
+
+ /* STORMs firmware */
+ INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
+ be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
+ INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
+ be32_to_cpu(fw_hdr->tsem_pram_data.offset);
+ INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
+ be32_to_cpu(fw_hdr->usem_int_table_data.offset);
+ INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
+ be32_to_cpu(fw_hdr->usem_pram_data.offset);
+ INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
+ be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
+ INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
+ be32_to_cpu(fw_hdr->xsem_pram_data.offset);
+ INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
+ be32_to_cpu(fw_hdr->csem_int_table_data.offset);
+ INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
+ be32_to_cpu(fw_hdr->csem_pram_data.offset);
+
+ return 0;
+
+init_offsets_alloc_err:
+ kfree(bp->init_ops);
+init_ops_alloc_err:
+ kfree(bp->init_data);
+request_firmware_exit:
+ release_firmware(bp->firmware);
+
+ return rc;
+}
+
+
static int __devinit bnx2x_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
- static int version_printed;
struct net_device *dev = NULL;
struct bnx2x *bp;
+ int pcie_width, pcie_speed;
int rc, i;
- if (version_printed++ == 0)
- printk(KERN_INFO "%s", version);
-
/* dev zeroed in init_etherdev */
dev = alloc_etherdev(sizeof(*bp));
if (!dev) {
@@ -11183,6 +11884,8 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
bp = netdev_priv(dev);
bp->msglevel = debug;
+ pci_set_drvdata(pdev, dev);
+
rc = bnx2x_init_dev(pdev, dev);
if (rc < 0) {
free_netdev(dev);
@@ -11192,23 +11895,28 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
dev->poll = bnx2x_poll;
dev->weight = 128*4;
- pci_set_drvdata(pdev, dev);
-
rc = bnx2x_init_bp(bp);
if (rc)
goto init_one_exit;
+ /* Set init arrays */
+ rc = bnx2x_init_firmware(bp, &pdev->dev);
+ if (rc) {
+ printk(KERN_ERR PFX "Error loading firmware\n");
+ goto init_one_exit;
+ }
+
rc = register_netdev(dev);
if (rc) {
dev_err(&pdev->dev, "Cannot register net device\n");
goto init_one_exit;
}
+ bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx,"
" IRQ %d, ", dev->name, board_info[ent->driver_data].name,
(CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
- bnx2x_get_pcie_width(bp),
- (bnx2x_get_pcie_speed(bp) == 2) ? "5GHz (Gen2)" : "2.5GHz",
+ pcie_width, (pcie_speed == 2) ? "5GHz (Gen2)" : "2.5GHz",
dev->base_addr, bp->pdev->irq);
printk("node addr ");
@@ -11248,6 +11956,11 @@ static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
unregister_netdev(dev);
+ kfree(bp->init_ops_offsets);
+ kfree(bp->init_ops);
+ kfree(bp->init_data);
+ release_firmware(bp->firmware);
+
if (bp->regview)
iounmap(bp->regview);
@@ -11410,6 +12123,11 @@ static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
netif_device_detach(dev);
+ if (state == pci_channel_io_perm_failure) {
+ rtnl_unlock();
+ return PCI_ERS_RESULT_DISCONNECT;
+ }
+
if (netif_running(dev))
bnx2x_eeh_nic_unload(bp);
@@ -11494,12 +12212,22 @@ static struct pci_driver bnx2x_pci_driver = {
static int __init bnx2x_init(void)
{
+ int ret;
+
+ printk(KERN_INFO "%s", version);
+
bnx2x_wq = create_singlethread_workqueue("bnx2x");
if (bnx2x_wq == NULL) {
printk(KERN_ERR PFX "Cannot create workqueue\n");
return -ENOMEM;
}
- return pci_register_driver(&bnx2x_pci_driver);
+
+ ret = pci_register_driver(&bnx2x_pci_driver);
+ if (ret) {
+ printk(KERN_ERR PFX "Cannot register driver\n");
+ destroy_workqueue(bnx2x_wq);
+ }
+ return ret;
}
static void __exit bnx2x_cleanup(void)
@@ -11512,3 +12240,4 @@ static void __exit bnx2x_cleanup(void)
module_init(bnx2x_init);
module_exit(bnx2x_cleanup);
+
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index 6314dd1..0695be1 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -190,12 +190,6 @@
_(0..15) stands for the connection type (one of 16). */
#define CCM_REG_N_SM_CTX_LD_0 0xd004c
#define CCM_REG_N_SM_CTX_LD_1 0xd0050
-#define CCM_REG_N_SM_CTX_LD_10 0xd0074
-#define CCM_REG_N_SM_CTX_LD_11 0xd0078
-#define CCM_REG_N_SM_CTX_LD_12 0xd007c
-#define CCM_REG_N_SM_CTX_LD_13 0xd0080
-#define CCM_REG_N_SM_CTX_LD_14 0xd0084
-#define CCM_REG_N_SM_CTX_LD_15 0xd0088
#define CCM_REG_N_SM_CTX_LD_2 0xd0054
#define CCM_REG_N_SM_CTX_LD_3 0xd0058
#define CCM_REG_N_SM_CTX_LD_4 0xd005c
@@ -370,7 +364,6 @@
#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
/* [RW 8] The event id for aggregated interrupt 0 */
#define CSDM_REG_AGG_INT_EVENT_0 0xc2038
-#define CSDM_REG_AGG_INT_EVENT_1 0xc203c
#define CSDM_REG_AGG_INT_EVENT_10 0xc2060
#define CSDM_REG_AGG_INT_EVENT_11 0xc2064
#define CSDM_REG_AGG_INT_EVENT_12 0xc2068
@@ -378,37 +371,27 @@
#define CSDM_REG_AGG_INT_EVENT_14 0xc2070
#define CSDM_REG_AGG_INT_EVENT_15 0xc2074
#define CSDM_REG_AGG_INT_EVENT_16 0xc2078
-#define CSDM_REG_AGG_INT_EVENT_17 0xc207c
-#define CSDM_REG_AGG_INT_EVENT_18 0xc2080
-#define CSDM_REG_AGG_INT_EVENT_19 0xc2084
#define CSDM_REG_AGG_INT_EVENT_2 0xc2040
-#define CSDM_REG_AGG_INT_EVENT_20 0xc2088
-#define CSDM_REG_AGG_INT_EVENT_21 0xc208c
-#define CSDM_REG_AGG_INT_EVENT_22 0xc2090
-#define CSDM_REG_AGG_INT_EVENT_23 0xc2094
-#define CSDM_REG_AGG_INT_EVENT_24 0xc2098
-#define CSDM_REG_AGG_INT_EVENT_25 0xc209c
-#define CSDM_REG_AGG_INT_EVENT_26 0xc20a0
-#define CSDM_REG_AGG_INT_EVENT_27 0xc20a4
-#define CSDM_REG_AGG_INT_EVENT_28 0xc20a8
-#define CSDM_REG_AGG_INT_EVENT_29 0xc20ac
#define CSDM_REG_AGG_INT_EVENT_3 0xc2044
-#define CSDM_REG_AGG_INT_EVENT_30 0xc20b0
-#define CSDM_REG_AGG_INT_EVENT_31 0xc20b4
#define CSDM_REG_AGG_INT_EVENT_4 0xc2048
-/* [RW 1] The T bit for aggregated interrupt 0 */
-#define CSDM_REG_AGG_INT_T_0 0xc20b8
-#define CSDM_REG_AGG_INT_T_1 0xc20bc
-#define CSDM_REG_AGG_INT_T_10 0xc20e0
-#define CSDM_REG_AGG_INT_T_11 0xc20e4
-#define CSDM_REG_AGG_INT_T_12 0xc20e8
-#define CSDM_REG_AGG_INT_T_13 0xc20ec
-#define CSDM_REG_AGG_INT_T_14 0xc20f0
-#define CSDM_REG_AGG_INT_T_15 0xc20f4
-#define CSDM_REG_AGG_INT_T_16 0xc20f8
-#define CSDM_REG_AGG_INT_T_17 0xc20fc
-#define CSDM_REG_AGG_INT_T_18 0xc2100
-#define CSDM_REG_AGG_INT_T_19 0xc2104
+#define CSDM_REG_AGG_INT_EVENT_5 0xc204c
+#define CSDM_REG_AGG_INT_EVENT_6 0xc2050
+#define CSDM_REG_AGG_INT_EVENT_7 0xc2054
+#define CSDM_REG_AGG_INT_EVENT_8 0xc2058
+#define CSDM_REG_AGG_INT_EVENT_9 0xc205c
+/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
+ or auto-mask-mode (1) */
+#define CSDM_REG_AGG_INT_MODE_10 0xc21e0
+#define CSDM_REG_AGG_INT_MODE_11 0xc21e4
+#define CSDM_REG_AGG_INT_MODE_12 0xc21e8
+#define CSDM_REG_AGG_INT_MODE_13 0xc21ec
+#define CSDM_REG_AGG_INT_MODE_14 0xc21f0
+#define CSDM_REG_AGG_INT_MODE_15 0xc21f4
+#define CSDM_REG_AGG_INT_MODE_16 0xc21f8
+#define CSDM_REG_AGG_INT_MODE_6 0xc21d0
+#define CSDM_REG_AGG_INT_MODE_7 0xc21d4
+#define CSDM_REG_AGG_INT_MODE_8 0xc21d8
+#define CSDM_REG_AGG_INT_MODE_9 0xc21dc
/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
/* [RW 16] The maximum value of the competion counter #0 */
@@ -633,24 +616,6 @@
#define DMAE_REG_GO_C1 0x102084
/* [RW 1] Command 10 go. */
#define DMAE_REG_GO_C10 0x102088
-#define DMAE_REG_GO_C10_SIZE 1
-/* [RW 1] Command 11 go. */
-#define DMAE_REG_GO_C11 0x10208c
-#define DMAE_REG_GO_C11_SIZE 1
-/* [RW 1] Command 12 go. */
-#define DMAE_REG_GO_C12 0x102090
-#define DMAE_REG_GO_C12_SIZE 1
-/* [RW 1] Command 13 go. */
-#define DMAE_REG_GO_C13 0x102094
-#define DMAE_REG_GO_C13_SIZE 1
-/* [RW 1] Command 14 go. */
-#define DMAE_REG_GO_C14 0x102098
-#define DMAE_REG_GO_C14_SIZE 1
-/* [RW 1] Command 15 go. */
-#define DMAE_REG_GO_C15 0x10209c
-#define DMAE_REG_GO_C15_SIZE 1
-/* [RW 1] Command 10 go. */
-#define DMAE_REG_GO_C10 0x102088
/* [RW 1] Command 11 go. */
#define DMAE_REG_GO_C11 0x10208c
/* [RW 1] Command 12 go. */
@@ -800,7 +765,6 @@
#define MCP_REG_MCPR_NVM_READ 0x86410
#define MCP_REG_MCPR_NVM_SW_ARB 0x86420
#define MCP_REG_MCPR_NVM_WRITE 0x86408
-#define MCP_REG_MCPR_NVM_WRITE1 0x86428
#define MCP_REG_MCPR_SCRATCH 0xa0000
/* [R 32] read first 32 bit after inversion of function 0. mapped as
follows: [0] NIG attention for function0; [1] NIG attention for
@@ -1186,19 +1150,7 @@
#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
-#define MISC_REG_AEU_GENERAL_ATTN_13 0xa034
-#define MISC_REG_AEU_GENERAL_ATTN_14 0xa038
-#define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c
-#define MISC_REG_AEU_GENERAL_ATTN_16 0xa040
-#define MISC_REG_AEU_GENERAL_ATTN_17 0xa044
-#define MISC_REG_AEU_GENERAL_ATTN_18 0xa048
-#define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
-#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
-#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
-#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
-#define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
-#define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
@@ -1290,137 +1242,13 @@
set. if the appropriate bit is clear (the driver request to free a client
it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
be asserted). */
-#define MISC_REG_DRIVER_CONTROL_10 0xa3e0
-#define MISC_REG_DRIVER_CONTROL_10_SIZE 2
-/* [RW 32] The following driver registers(1...16) represent 16 drivers and
- 32 clients. Each client can be controlled by one driver only. One in each
- bit represent that this driver control the appropriate client (Ex: bit 5
- is set means this driver control client number 5). addr1 = set; addr0 =
- clear; read from both addresses will give the same result = status. write
- to address 1 will set a request to control all the clients that their
- appropriate bit (in the write command) is set. if the client is free (the
- appropriate bit in all the other drivers is clear) one will be written to
- that driver register; if the client isn't free the bit will remain zero.
- if the appropriate bit is set (the driver request to gain control on a
- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
- interrupt will be asserted). write to address 0 will set a request to
- free all the clients that their appropriate bit (in the write command) is
- set. if the appropriate bit is clear (the driver request to free a client
- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
- be asserted). */
-#define MISC_REG_DRIVER_CONTROL_11 0xa3e8
-#define MISC_REG_DRIVER_CONTROL_11_SIZE 2
-/* [RW 32] The following driver registers(1...16) represent 16 drivers and
- 32 clients. Each client can be controlled by one driver only. One in each
- bit represent that this driver control the appropriate client (Ex: bit 5
- is set means this driver control client number 5). addr1 = set; addr0 =
- clear; read from both addresses will give the same result = status. write
- to address 1 will set a request to control all the clients that their
- appropriate bit (in the write command) is set. if the client is free (the
- appropriate bit in all the other drivers is clear) one will be written to
- that driver register; if the client isn't free the bit will remain zero.
- if the appropriate bit is set (the driver request to gain control on a
- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
- interrupt will be asserted). write to address 0 will set a request to
- free all the clients that their appropriate bit (in the write command) is
- set. if the appropriate bit is clear (the driver request to free a client
- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
- be asserted). */
-#define MISC_REG_DRIVER_CONTROL_12 0xa3f0
-#define MISC_REG_DRIVER_CONTROL_12_SIZE 2
-/* [RW 32] The following driver registers(1...16) represent 16 drivers and
- 32 clients. Each client can be controlled by one driver only. One in each
- bit represent that this driver control the appropriate client (Ex: bit 5
- is set means this driver control client number 5). addr1 = set; addr0 =
- clear; read from both addresses will give the same result = status. write
- to address 1 will set a request to control all the clients that their
- appropriate bit (in the write command) is set. if the client is free (the
- appropriate bit in all the other drivers is clear) one will be written to
- that driver register; if the client isn't free the bit will remain zero.
- if the appropriate bit is set (the driver request to gain control on a
- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
- interrupt will be asserted). write to address 0 will set a request to
- free all the clients that their appropriate bit (in the write command) is
- set. if the appropriate bit is clear (the driver request to free a client
- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
- be asserted). */
-#define MISC_REG_DRIVER_CONTROL_13 0xa3f8
-#define MISC_REG_DRIVER_CONTROL_13_SIZE 2
-/* [RW 32] The following driver registers(1...16) represent 16 drivers and
- 32 clients. Each client can be controlled by one driver only. One in each
- bit represent that this driver control the appropriate client (Ex: bit 5
- is set means this driver control client number 5). addr1 = set; addr0 =
- clear; read from both addresses will give the same result = status. write
- to address 1 will set a request to control all the clients that their
- appropriate bit (in the write command) is set. if the client is free (the
- appropriate bit in all the other drivers is clear) one will be written to
- that driver register; if the client isn't free the bit will remain zero.
- if the appropriate bit is set (the driver request to gain control on a
- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
- interrupt will be asserted). write to address 0 will set a request to
- free all the clients that their appropriate bit (in the write command) is
- set. if the appropriate bit is clear (the driver request to free a client
- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
- be asserted). */
#define MISC_REG_DRIVER_CONTROL_1 0xa510
-#define MISC_REG_DRIVER_CONTROL_14 0xa5e0
-#define MISC_REG_DRIVER_CONTROL_14_SIZE 2
-/* [RW 32] The following driver registers(1...16) represent 16 drivers and
- 32 clients. Each client can be controlled by one driver only. One in each
- bit represent that this driver control the appropriate client (Ex: bit 5
- is set means this driver control client number 5). addr1 = set; addr0 =
- clear; read from both addresses will give the same result = status. write
- to address 1 will set a request to control all the clients that their
- appropriate bit (in the write command) is set. if the client is free (the
- appropriate bit in all the other drivers is clear) one will be written to
- that driver register; if the client isn't free the bit will remain zero.
- if the appropriate bit is set (the driver request to gain control on a
- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
- interrupt will be asserted). write to address 0 will set a request to
- free all the clients that their appropriate bit (in the write command) is
- set. if the appropriate bit is clear (the driver request to free a client
- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
- be asserted). */
-#define MISC_REG_DRIVER_CONTROL_15 0xa5e8
-#define MISC_REG_DRIVER_CONTROL_15_SIZE 2
-/* [RW 32] The following driver registers(1...16) represent 16 drivers and
- 32 clients. Each client can be controlled by one driver only. One in each
- bit represent that this driver control the appropriate client (Ex: bit 5
- is set means this driver control client number 5). addr1 = set; addr0 =
- clear; read from both addresses will give the same result = status. write
- to address 1 will set a request to control all the clients that their
- appropriate bit (in the write command) is set. if the client is free (the
- appropriate bit in all the other drivers is clear) one will be written to
- that driver register; if the client isn't free the bit will remain zero.
- if the appropriate bit is set (the driver request to gain control on a
- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
- interrupt will be asserted). write to address 0 will set a request to
- free all the clients that their appropriate bit (in the write command) is
- set. if the appropriate bit is clear (the driver request to free a client
- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
- be asserted). */
-#define MISC_REG_DRIVER_CONTROL_16 0xa5f0
-#define MISC_REG_DRIVER_CONTROL_16_SIZE 2
-/* [RW 32] The following driver registers(1...16) represent 16 drivers and
- 32 clients. Each client can be controlled by one driver only. One in each
- bit represent that this driver control the appropriate client (Ex: bit 5
- is set means this driver control client number 5). addr1 = set; addr0 =
- clear; read from both addresses will give the same result = status. write
- to address 1 will set a request to control all the clients that their
- appropriate bit (in the write command) is set. if the client is free (the
- appropriate bit in all the other drivers is clear) one will be written to
- that driver register; if the client isn't free the bit will remain zero.
- if the appropriate bit is set (the driver request to gain control on a
- client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
- interrupt will be asserted). write to address 0 will set a request to
- free all the clients that their appropriate bit (in the write command) is
- set. if the appropriate bit is clear (the driver request to free a client
- it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
- be asserted). */
#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
only. */
#define MISC_REG_E1HMF_MODE 0xa5f8
+/* [RW 32] Debug only: spare RW register reset by core reset */
+#define MISC_REG_GENERIC_CR_0 0xa460
/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
these bits is written as a '1'; the corresponding SPIO bit will turn off
it's drivers and become an input. This is the reset state of all GPIO
@@ -1616,6 +1444,11 @@
/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
loaded; 0-prepare; -unprepare */
#define MISC_REG_UNPREPARED 0xa424
+#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
+#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
+#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
+#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
+#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
@@ -1654,12 +1487,12 @@
/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
to emac for port0; other way to bmac for port0 */
#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
-/* [RW 32] TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order. */
-#define NIG_REG_EGRESS_MNG0_FIFO 0x1045c
/* [RW 1] Input enable for TX PBF user packet port0 IF */
#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
/* [RW 1] Input enable for TX PBF user packet port1 IF */
#define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
+/* [RW 1] Input enable for TX UMP management packet port0 IF */
+#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
/* [RW 1] Input enable for RX_EMAC0 IF */
#define NIG_REG_EMAC0_IN_EN 0x100a4
/* [RW 1] output enable for TX EMAC pause port 0 IF */
@@ -1683,6 +1516,24 @@
/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
+/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
+ logic for interrupts must be used. Enable per bit of interrupt of
+ ~latch_status.latch_status */
+#define NIG_REG_LATCH_BC_0 0x16210
+/* [RW 27] Latch for each interrupt from Unicore.b[0]
+ status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
+ b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
+ b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
+ b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
+ b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
+ b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
+ b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
+ b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
+ b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
+ b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
+ b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
+ b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
+#define NIG_REG_LATCH_STATUS_0 0x18000
/* [RW 1] led 10g for port 0 */
#define NIG_REG_LED_10G_P0 0x10320
/* [RW 1] led 10g for port 1 */
@@ -1722,6 +1573,7 @@
/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
tsdm enable; b2- usdm enable */
#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
+#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
/* [RW 1] SAFC enable for port0. This register may get 1 only when
~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
port */
@@ -1872,6 +1724,7 @@
#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
@@ -2072,6 +1925,7 @@
#define PXP2_REG_PGL_ADDR_94_F0 0x120540
#define PXP2_REG_PGL_CONTROL0 0x120490
#define PXP2_REG_PGL_CONTROL1 0x120514
+#define PXP2_REG_PGL_DEBUG 0x120520
/* [RW 32] third dword data of expansion rom request. this register is
special. reading from it provides a vector outstanding read requests. if
a bit is zero it means that a read request on the corresponding tag did
@@ -2142,11 +1996,8 @@
#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
-#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
-#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
-#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
@@ -2156,11 +2007,8 @@
#define PXP2_REG_PSWRQ_BW_L1 0x1202b0
#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
-#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
-#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
#define PXP2_REG_PSWRQ_BW_L2 0x1202b4
#define PXP2_REG_PSWRQ_BW_L28 0x120318
-#define PXP2_REG_PSWRQ_BW_L28 0x120318
#define PXP2_REG_PSWRQ_BW_L3 0x1202b8
#define PXP2_REG_PSWRQ_BW_L6 0x1202c4
#define PXP2_REG_PSWRQ_BW_L7 0x1202c8
@@ -2170,11 +2018,8 @@
#define PXP2_REG_PSWRQ_BW_UB1 0x120238
#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
#define PXP2_REG_PSWRQ_BW_UB11 0x120260
-#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
-#define PXP2_REG_PSWRQ_BW_UB11 0x120260
#define PXP2_REG_PSWRQ_BW_UB2 0x12023c
#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
-#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
#define PXP2_REG_PSWRQ_BW_UB3 0x120240
#define PXP2_REG_PSWRQ_BW_UB6 0x12024c
#define PXP2_REG_PSWRQ_BW_UB7 0x120250
@@ -2232,6 +2077,9 @@
allocated for vq22 */
#define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
+ allocated for vq25 */
+#define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
+/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
allocated for vq6 */
#define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
@@ -2762,16 +2610,6 @@
#define QM_REG_QVOQIDX_107 0x16e4b8
#define QM_REG_QVOQIDX_108 0x16e4bc
#define QM_REG_QVOQIDX_109 0x16e4c0
-#define QM_REG_QVOQIDX_100 0x16e49c
-#define QM_REG_QVOQIDX_101 0x16e4a0
-#define QM_REG_QVOQIDX_102 0x16e4a4
-#define QM_REG_QVOQIDX_103 0x16e4a8
-#define QM_REG_QVOQIDX_104 0x16e4ac
-#define QM_REG_QVOQIDX_105 0x16e4b0
-#define QM_REG_QVOQIDX_106 0x16e4b4
-#define QM_REG_QVOQIDX_107 0x16e4b8
-#define QM_REG_QVOQIDX_108 0x16e4bc
-#define QM_REG_QVOQIDX_109 0x16e4c0
#define QM_REG_QVOQIDX_11 0x168120
#define QM_REG_QVOQIDX_110 0x16e4c4
#define QM_REG_QVOQIDX_111 0x16e4c8
@@ -2783,16 +2621,6 @@
#define QM_REG_QVOQIDX_117 0x16e4e0
#define QM_REG_QVOQIDX_118 0x16e4e4
#define QM_REG_QVOQIDX_119 0x16e4e8
-#define QM_REG_QVOQIDX_110 0x16e4c4
-#define QM_REG_QVOQIDX_111 0x16e4c8
-#define QM_REG_QVOQIDX_112 0x16e4cc
-#define QM_REG_QVOQIDX_113 0x16e4d0
-#define QM_REG_QVOQIDX_114 0x16e4d4
-#define QM_REG_QVOQIDX_115 0x16e4d8
-#define QM_REG_QVOQIDX_116 0x16e4dc
-#define QM_REG_QVOQIDX_117 0x16e4e0
-#define QM_REG_QVOQIDX_118 0x16e4e4
-#define QM_REG_QVOQIDX_119 0x16e4e8
#define QM_REG_QVOQIDX_12 0x168124
#define QM_REG_QVOQIDX_120 0x16e4ec
#define QM_REG_QVOQIDX_121 0x16e4f0
@@ -2802,14 +2630,6 @@
#define QM_REG_QVOQIDX_125 0x16e500
#define QM_REG_QVOQIDX_126 0x16e504
#define QM_REG_QVOQIDX_127 0x16e508
-#define QM_REG_QVOQIDX_120 0x16e4ec
-#define QM_REG_QVOQIDX_121 0x16e4f0
-#define QM_REG_QVOQIDX_122 0x16e4f4
-#define QM_REG_QVOQIDX_123 0x16e4f8
-#define QM_REG_QVOQIDX_124 0x16e4fc
-#define QM_REG_QVOQIDX_125 0x16e500
-#define QM_REG_QVOQIDX_126 0x16e504
-#define QM_REG_QVOQIDX_127 0x16e508
#define QM_REG_QVOQIDX_13 0x168128
#define QM_REG_QVOQIDX_14 0x16812c
#define QM_REG_QVOQIDX_15 0x168130
@@ -2855,16 +2675,6 @@
#define QM_REG_QVOQIDX_57 0x1681d8
#define QM_REG_QVOQIDX_58 0x1681dc
#define QM_REG_QVOQIDX_59 0x1681e0
-#define QM_REG_QVOQIDX_50 0x1681bc
-#define QM_REG_QVOQIDX_51 0x1681c0
-#define QM_REG_QVOQIDX_52 0x1681c4
-#define QM_REG_QVOQIDX_53 0x1681c8
-#define QM_REG_QVOQIDX_54 0x1681cc
-#define QM_REG_QVOQIDX_55 0x1681d0
-#define QM_REG_QVOQIDX_56 0x1681d4
-#define QM_REG_QVOQIDX_57 0x1681d8
-#define QM_REG_QVOQIDX_58 0x1681dc
-#define QM_REG_QVOQIDX_59 0x1681e0
#define QM_REG_QVOQIDX_6 0x16810c
#define QM_REG_QVOQIDX_60 0x1681e4
#define QM_REG_QVOQIDX_61 0x1681e8
@@ -2872,16 +2682,6 @@
#define QM_REG_QVOQIDX_63 0x1681f0
#define QM_REG_QVOQIDX_64 0x16e40c
#define QM_REG_QVOQIDX_65 0x16e410
-#define QM_REG_QVOQIDX_66 0x16e414
-#define QM_REG_QVOQIDX_67 0x16e418
-#define QM_REG_QVOQIDX_68 0x16e41c
-#define QM_REG_QVOQIDX_69 0x16e420
-#define QM_REG_QVOQIDX_60 0x1681e4
-#define QM_REG_QVOQIDX_61 0x1681e8
-#define QM_REG_QVOQIDX_62 0x1681ec
-#define QM_REG_QVOQIDX_63 0x1681f0
-#define QM_REG_QVOQIDX_64 0x16e40c
-#define QM_REG_QVOQIDX_65 0x16e410
#define QM_REG_QVOQIDX_69 0x16e420
#define QM_REG_QVOQIDX_7 0x168110
#define QM_REG_QVOQIDX_70 0x16e424
@@ -2894,29 +2694,9 @@
#define QM_REG_QVOQIDX_77 0x16e440
#define QM_REG_QVOQIDX_78 0x16e444
#define QM_REG_QVOQIDX_79 0x16e448
-#define QM_REG_QVOQIDX_70 0x16e424
-#define QM_REG_QVOQIDX_71 0x16e428
-#define QM_REG_QVOQIDX_72 0x16e42c
-#define QM_REG_QVOQIDX_73 0x16e430
-#define QM_REG_QVOQIDX_74 0x16e434
-#define QM_REG_QVOQIDX_75 0x16e438
-#define QM_REG_QVOQIDX_76 0x16e43c
-#define QM_REG_QVOQIDX_77 0x16e440
-#define QM_REG_QVOQIDX_78 0x16e444
-#define QM_REG_QVOQIDX_79 0x16e448
#define QM_REG_QVOQIDX_8 0x168114
#define QM_REG_QVOQIDX_80 0x16e44c
#define QM_REG_QVOQIDX_81 0x16e450
-#define QM_REG_QVOQIDX_82 0x16e454
-#define QM_REG_QVOQIDX_83 0x16e458
-#define QM_REG_QVOQIDX_84 0x16e45c
-#define QM_REG_QVOQIDX_85 0x16e460
-#define QM_REG_QVOQIDX_86 0x16e464
-#define QM_REG_QVOQIDX_87 0x16e468
-#define QM_REG_QVOQIDX_88 0x16e46c
-#define QM_REG_QVOQIDX_89 0x16e470
-#define QM_REG_QVOQIDX_80 0x16e44c
-#define QM_REG_QVOQIDX_81 0x16e450
#define QM_REG_QVOQIDX_85 0x16e460
#define QM_REG_QVOQIDX_86 0x16e464
#define QM_REG_QVOQIDX_87 0x16e468
@@ -2933,23 +2713,11 @@
#define QM_REG_QVOQIDX_97 0x16e490
#define QM_REG_QVOQIDX_98 0x16e494
#define QM_REG_QVOQIDX_99 0x16e498
-#define QM_REG_QVOQIDX_90 0x16e474
-#define QM_REG_QVOQIDX_91 0x16e478
-#define QM_REG_QVOQIDX_92 0x16e47c
-#define QM_REG_QVOQIDX_93 0x16e480
-#define QM_REG_QVOQIDX_94 0x16e484
-#define QM_REG_QVOQIDX_95 0x16e488
-#define QM_REG_QVOQIDX_96 0x16e48c
-#define QM_REG_QVOQIDX_97 0x16e490
-#define QM_REG_QVOQIDX_98 0x16e494
-#define QM_REG_QVOQIDX_99 0x16e498
/* [RW 1] Initialization bit command */
#define QM_REG_SOFT_RESET 0x168428
/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
#define QM_REG_TASKCRDCOST_0 0x16809c
#define QM_REG_TASKCRDCOST_1 0x1680a0
-#define QM_REG_TASKCRDCOST_10 0x1680c4
-#define QM_REG_TASKCRDCOST_11 0x1680c8
#define QM_REG_TASKCRDCOST_2 0x1680a4
#define QM_REG_TASKCRDCOST_4 0x1680ac
#define QM_REG_TASKCRDCOST_5 0x1680b0
@@ -2962,24 +2730,18 @@
/* [R 16] The credit value for each VOQ */
#define QM_REG_VOQCREDIT_0 0x1682d0
#define QM_REG_VOQCREDIT_1 0x1682d4
-#define QM_REG_VOQCREDIT_10 0x1682f8
-#define QM_REG_VOQCREDIT_11 0x1682fc
#define QM_REG_VOQCREDIT_4 0x1682e0
/* [RW 16] The credit value that if above the QM is considered almost full */
#define QM_REG_VOQCREDITAFULLTHR 0x168090
/* [RW 16] The init and maximum credit for each VoQ */
#define QM_REG_VOQINITCREDIT_0 0x168060
#define QM_REG_VOQINITCREDIT_1 0x168064
-#define QM_REG_VOQINITCREDIT_10 0x168088
-#define QM_REG_VOQINITCREDIT_11 0x16808c
#define QM_REG_VOQINITCREDIT_2 0x168068
#define QM_REG_VOQINITCREDIT_4 0x168070
#define QM_REG_VOQINITCREDIT_5 0x168074
/* [RW 1] The port of which VOQ belongs */
#define QM_REG_VOQPORT_0 0x1682a0
#define QM_REG_VOQPORT_1 0x1682a4
-#define QM_REG_VOQPORT_10 0x1682c8
-#define QM_REG_VOQPORT_11 0x1682cc
#define QM_REG_VOQPORT_2 0x1682a8
/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
#define QM_REG_VOQQMASK_0_LSB 0x168240
@@ -3077,36 +2839,6 @@
#define QM_REG_WRRWEIGHTS_0 0x16880c
#define QM_REG_WRRWEIGHTS_1 0x168810
#define QM_REG_WRRWEIGHTS_10 0x168814
-#define QM_REG_WRRWEIGHTS_10_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_11 0x168818
-#define QM_REG_WRRWEIGHTS_11_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_12 0x16881c
-#define QM_REG_WRRWEIGHTS_12_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_13 0x168820
-#define QM_REG_WRRWEIGHTS_13_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_14 0x168824
-#define QM_REG_WRRWEIGHTS_14_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_15 0x168828
-#define QM_REG_WRRWEIGHTS_15_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_16 0x16e000
-#define QM_REG_WRRWEIGHTS_16_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_17 0x16e004
-#define QM_REG_WRRWEIGHTS_17_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_18 0x16e008
-#define QM_REG_WRRWEIGHTS_18_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_19 0x16e00c
-#define QM_REG_WRRWEIGHTS_19_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_10 0x168814
#define QM_REG_WRRWEIGHTS_11 0x168818
#define QM_REG_WRRWEIGHTS_12 0x16881c
#define QM_REG_WRRWEIGHTS_13 0x168820
@@ -3118,36 +2850,6 @@
#define QM_REG_WRRWEIGHTS_19 0x16e00c
#define QM_REG_WRRWEIGHTS_2 0x16882c
#define QM_REG_WRRWEIGHTS_20 0x16e010
-#define QM_REG_WRRWEIGHTS_20_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_21 0x16e014
-#define QM_REG_WRRWEIGHTS_21_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_22 0x16e018
-#define QM_REG_WRRWEIGHTS_22_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_23 0x16e01c
-#define QM_REG_WRRWEIGHTS_23_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_24 0x16e020
-#define QM_REG_WRRWEIGHTS_24_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_25 0x16e024
-#define QM_REG_WRRWEIGHTS_25_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_26 0x16e028
-#define QM_REG_WRRWEIGHTS_26_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_27 0x16e02c
-#define QM_REG_WRRWEIGHTS_27_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_28 0x16e030
-#define QM_REG_WRRWEIGHTS_28_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_29 0x16e034
-#define QM_REG_WRRWEIGHTS_29_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_20 0x16e010
#define QM_REG_WRRWEIGHTS_21 0x16e014
#define QM_REG_WRRWEIGHTS_22 0x16e018
#define QM_REG_WRRWEIGHTS_23 0x16e01c
@@ -3159,12 +2861,6 @@
#define QM_REG_WRRWEIGHTS_29 0x16e034
#define QM_REG_WRRWEIGHTS_3 0x168830
#define QM_REG_WRRWEIGHTS_30 0x16e038
-#define QM_REG_WRRWEIGHTS_30_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_31 0x16e03c
-#define QM_REG_WRRWEIGHTS_31_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_30 0x16e038
#define QM_REG_WRRWEIGHTS_31 0x16e03c
#define QM_REG_WRRWEIGHTS_4 0x168834
#define QM_REG_WRRWEIGHTS_5 0x168838
@@ -3174,362 +2870,6 @@
#define QM_REG_WRRWEIGHTS_9 0x168848
/* [R 6] Keep the fill level of the fifo from write client 1 */
#define QM_REG_XQM_WRC_FIFOLVL 0x168000
-#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
-#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
-#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
-#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
-#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
-#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
-#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
-#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
-#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
-#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
-#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
-#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
-#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
-#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
-#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
-#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
-#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
-#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
-#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
-#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
-#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
-#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
-#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
-#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
-#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
-#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
-#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
-#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
-#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
-#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
-#define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
-#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
-#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
-#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
-#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
-#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
-#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
-#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
-#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
-#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
-#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
-#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
-#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
-#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
-#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
-#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
-#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
-#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
-#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
-#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
-#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
-#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
-#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
-#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
-#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
-#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
-#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
-#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
-#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
-#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
-#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
-#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
-#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
-#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
-#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
-#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
-#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
-#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
-#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
-#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
-#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
-#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
-#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
-#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
-#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
-#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
-/* [R 1] debug only: This bit indicates whether indicates that external
- buffer was wrapped (oldest data was thrown); Relevant only when
- ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
-#define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
-#define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
-/* [R 1] debug only: This bit indicates whether the internal buffer was
- wrapped (oldest data was thrown) Relevant only when
- ~dbg_registers_debug_target=0 (internal buffer) */
-#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
-#define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
-#define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8)
-#define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8
-#define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8)
-#define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8
-#define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8)
-#define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8
-#define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8)
-#define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_0 0x16880c
-#define QM_REG_WRRWEIGHTS_0_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_1 0x168810
-#define QM_REG_WRRWEIGHTS_1_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_10 0x168814
-#define QM_REG_WRRWEIGHTS_10_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_11 0x168818
-#define QM_REG_WRRWEIGHTS_11_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_12 0x16881c
-#define QM_REG_WRRWEIGHTS_12_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_13 0x168820
-#define QM_REG_WRRWEIGHTS_13_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_14 0x168824
-#define QM_REG_WRRWEIGHTS_14_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_15 0x168828
-#define QM_REG_WRRWEIGHTS_15_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_2 0x16882c
-#define QM_REG_WRRWEIGHTS_2_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_3 0x168830
-#define QM_REG_WRRWEIGHTS_3_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_4 0x168834
-#define QM_REG_WRRWEIGHTS_4_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_5 0x168838
-#define QM_REG_WRRWEIGHTS_5_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_6 0x16883c
-#define QM_REG_WRRWEIGHTS_6_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_7 0x168840
-#define QM_REG_WRRWEIGHTS_7_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_8 0x168844
-#define QM_REG_WRRWEIGHTS_8_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_9 0x168848
-#define QM_REG_WRRWEIGHTS_9_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_16 0x16e000
-#define QM_REG_WRRWEIGHTS_16_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_17 0x16e004
-#define QM_REG_WRRWEIGHTS_17_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_18 0x16e008
-#define QM_REG_WRRWEIGHTS_18_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_19 0x16e00c
-#define QM_REG_WRRWEIGHTS_19_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_20 0x16e010
-#define QM_REG_WRRWEIGHTS_20_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_21 0x16e014
-#define QM_REG_WRRWEIGHTS_21_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_22 0x16e018
-#define QM_REG_WRRWEIGHTS_22_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_23 0x16e01c
-#define QM_REG_WRRWEIGHTS_23_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_24 0x16e020
-#define QM_REG_WRRWEIGHTS_24_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_25 0x16e024
-#define QM_REG_WRRWEIGHTS_25_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_26 0x16e028
-#define QM_REG_WRRWEIGHTS_26_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_27 0x16e02c
-#define QM_REG_WRRWEIGHTS_27_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_28 0x16e030
-#define QM_REG_WRRWEIGHTS_28_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_29 0x16e034
-#define QM_REG_WRRWEIGHTS_29_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_30 0x16e038
-#define QM_REG_WRRWEIGHTS_30_SIZE 1
-/* [RW 32] Wrr weights */
-#define QM_REG_WRRWEIGHTS_31 0x16e03c
-#define QM_REG_WRRWEIGHTS_31_SIZE 1
#define SRC_REG_COUNTFREE0 0x40500
/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
ports. If set the searcher support 8 functions. */
@@ -3629,12 +2969,6 @@
type (one of 16). */
#define TCM_REG_N_SM_CTX_LD_0 0x50050
#define TCM_REG_N_SM_CTX_LD_1 0x50054
-#define TCM_REG_N_SM_CTX_LD_10 0x50078
-#define TCM_REG_N_SM_CTX_LD_11 0x5007c
-#define TCM_REG_N_SM_CTX_LD_12 0x50080
-#define TCM_REG_N_SM_CTX_LD_13 0x50084
-#define TCM_REG_N_SM_CTX_LD_14 0x50088
-#define TCM_REG_N_SM_CTX_LD_15 0x5008c
#define TCM_REG_N_SM_CTX_LD_2 0x50058
#define TCM_REG_N_SM_CTX_LD_3 0x5005c
#define TCM_REG_N_SM_CTX_LD_4 0x50060
@@ -3828,6 +3162,7 @@
#define TM_REG_LIN0_PHY_ADDR 0x164270
/* [RW 1] Linear0 physical address valid. */
#define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
+#define TM_REG_LIN0_SCAN_ON 0x1640d0
/* [RW 24] Linear0 array scan timeout. */
#define TM_REG_LIN0_SCAN_TIME 0x16403c
/* [RW 32] Linear1 logic address. */
@@ -3840,8 +3175,6 @@
#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
/* [RW 2] Load value for pci arbiter credit cnt. */
#define TM_REG_PCIARB_CRDCNT_VAL 0x164260
-/* [RW 1] Timer software reset - active high. */
-#define TM_REG_TIMER_SOFT_RST 0x164004
/* [RW 20] The amount of hardware cycles for each timer tick. */
#define TM_REG_TIMER_TICK_SIZE 0x16401c
/* [RW 8] Timers Context region. */
@@ -3853,44 +3186,12 @@
/* [RW 8] The event id for aggregated interrupt 0 */
#define TSDM_REG_AGG_INT_EVENT_0 0x42038
#define TSDM_REG_AGG_INT_EVENT_1 0x4203c
-#define TSDM_REG_AGG_INT_EVENT_10 0x42060
-#define TSDM_REG_AGG_INT_EVENT_11 0x42064
-#define TSDM_REG_AGG_INT_EVENT_12 0x42068
-#define TSDM_REG_AGG_INT_EVENT_13 0x4206c
-#define TSDM_REG_AGG_INT_EVENT_14 0x42070
-#define TSDM_REG_AGG_INT_EVENT_15 0x42074
-#define TSDM_REG_AGG_INT_EVENT_16 0x42078
-#define TSDM_REG_AGG_INT_EVENT_17 0x4207c
-#define TSDM_REG_AGG_INT_EVENT_18 0x42080
-#define TSDM_REG_AGG_INT_EVENT_19 0x42084
#define TSDM_REG_AGG_INT_EVENT_2 0x42040
-#define TSDM_REG_AGG_INT_EVENT_20 0x42088
-#define TSDM_REG_AGG_INT_EVENT_21 0x4208c
-#define TSDM_REG_AGG_INT_EVENT_22 0x42090
-#define TSDM_REG_AGG_INT_EVENT_23 0x42094
-#define TSDM_REG_AGG_INT_EVENT_24 0x42098
-#define TSDM_REG_AGG_INT_EVENT_25 0x4209c
-#define TSDM_REG_AGG_INT_EVENT_26 0x420a0
-#define TSDM_REG_AGG_INT_EVENT_27 0x420a4
-#define TSDM_REG_AGG_INT_EVENT_28 0x420a8
-#define TSDM_REG_AGG_INT_EVENT_29 0x420ac
#define TSDM_REG_AGG_INT_EVENT_3 0x42044
-#define TSDM_REG_AGG_INT_EVENT_30 0x420b0
-#define TSDM_REG_AGG_INT_EVENT_31 0x420b4
#define TSDM_REG_AGG_INT_EVENT_4 0x42048
/* [RW 1] The T bit for aggregated interrupt 0 */
#define TSDM_REG_AGG_INT_T_0 0x420b8
#define TSDM_REG_AGG_INT_T_1 0x420bc
-#define TSDM_REG_AGG_INT_T_10 0x420e0
-#define TSDM_REG_AGG_INT_T_11 0x420e4
-#define TSDM_REG_AGG_INT_T_12 0x420e8
-#define TSDM_REG_AGG_INT_T_13 0x420ec
-#define TSDM_REG_AGG_INT_T_14 0x420f0
-#define TSDM_REG_AGG_INT_T_15 0x420f4
-#define TSDM_REG_AGG_INT_T_16 0x420f8
-#define TSDM_REG_AGG_INT_T_17 0x420fc
-#define TSDM_REG_AGG_INT_T_18 0x42100
-#define TSDM_REG_AGG_INT_T_19 0x42104
/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
#define TSDM_REG_CFC_RSP_START_ADDR 0x42008
/* [RW 16] The maximum value of the competion counter #0 */
@@ -4175,12 +3476,6 @@
connection type (one of 16). */
#define UCM_REG_N_SM_CTX_LD_0 0xe0054
#define UCM_REG_N_SM_CTX_LD_1 0xe0058
-#define UCM_REG_N_SM_CTX_LD_10 0xe007c
-#define UCM_REG_N_SM_CTX_LD_11 0xe0080
-#define UCM_REG_N_SM_CTX_LD_12 0xe0084
-#define UCM_REG_N_SM_CTX_LD_13 0xe0088
-#define UCM_REG_N_SM_CTX_LD_14 0xe008c
-#define UCM_REG_N_SM_CTX_LD_15 0xe0090
#define UCM_REG_N_SM_CTX_LD_2 0xe005c
#define UCM_REG_N_SM_CTX_LD_3 0xe0060
#define UCM_REG_N_SM_CTX_LD_4 0xe0064
@@ -4330,48 +3625,20 @@
/* [RW 8] The event id for aggregated interrupt 0 */
#define USDM_REG_AGG_INT_EVENT_0 0xc4038
#define USDM_REG_AGG_INT_EVENT_1 0xc403c
-#define USDM_REG_AGG_INT_EVENT_10 0xc4060
-#define USDM_REG_AGG_INT_EVENT_11 0xc4064
-#define USDM_REG_AGG_INT_EVENT_12 0xc4068
-#define USDM_REG_AGG_INT_EVENT_13 0xc406c
-#define USDM_REG_AGG_INT_EVENT_14 0xc4070
-#define USDM_REG_AGG_INT_EVENT_15 0xc4074
-#define USDM_REG_AGG_INT_EVENT_16 0xc4078
-#define USDM_REG_AGG_INT_EVENT_17 0xc407c
-#define USDM_REG_AGG_INT_EVENT_18 0xc4080
-#define USDM_REG_AGG_INT_EVENT_19 0xc4084
#define USDM_REG_AGG_INT_EVENT_2 0xc4040
-#define USDM_REG_AGG_INT_EVENT_20 0xc4088
-#define USDM_REG_AGG_INT_EVENT_21 0xc408c
-#define USDM_REG_AGG_INT_EVENT_22 0xc4090
-#define USDM_REG_AGG_INT_EVENT_23 0xc4094
-#define USDM_REG_AGG_INT_EVENT_24 0xc4098
-#define USDM_REG_AGG_INT_EVENT_25 0xc409c
-#define USDM_REG_AGG_INT_EVENT_26 0xc40a0
-#define USDM_REG_AGG_INT_EVENT_27 0xc40a4
-#define USDM_REG_AGG_INT_EVENT_28 0xc40a8
-#define USDM_REG_AGG_INT_EVENT_29 0xc40ac
-#define USDM_REG_AGG_INT_EVENT_3 0xc4044
-#define USDM_REG_AGG_INT_EVENT_30 0xc40b0
-#define USDM_REG_AGG_INT_EVENT_31 0xc40b4
#define USDM_REG_AGG_INT_EVENT_4 0xc4048
#define USDM_REG_AGG_INT_EVENT_5 0xc404c
+#define USDM_REG_AGG_INT_EVENT_6 0xc4050
/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
or auto-mask-mode (1) */
#define USDM_REG_AGG_INT_MODE_0 0xc41b8
#define USDM_REG_AGG_INT_MODE_1 0xc41bc
-#define USDM_REG_AGG_INT_MODE_10 0xc41e0
-#define USDM_REG_AGG_INT_MODE_11 0xc41e4
-#define USDM_REG_AGG_INT_MODE_12 0xc41e8
-#define USDM_REG_AGG_INT_MODE_13 0xc41ec
-#define USDM_REG_AGG_INT_MODE_14 0xc41f0
-#define USDM_REG_AGG_INT_MODE_15 0xc41f4
-#define USDM_REG_AGG_INT_MODE_16 0xc41f8
-#define USDM_REG_AGG_INT_MODE_17 0xc41fc
-#define USDM_REG_AGG_INT_MODE_18 0xc4200
-#define USDM_REG_AGG_INT_MODE_19 0xc4204
#define USDM_REG_AGG_INT_MODE_4 0xc41c8
#define USDM_REG_AGG_INT_MODE_5 0xc41cc
+#define USDM_REG_AGG_INT_MODE_6 0xc41d0
+/* [RW 1] The T bit for aggregated interrupt 5 */
+#define USDM_REG_AGG_INT_T_5 0xc40cc
+#define USDM_REG_AGG_INT_T_6 0xc40d0
/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
#define USDM_REG_CFC_RSP_START_ADDR 0xc4008
/* [RW 16] The maximum value of the competion counter #0 */
@@ -4675,10 +3942,6 @@
/* [RC 1] Set at message length mismatch (relative to last indication) at
the nig1 interface. */
#define XCM_REG_NIG1_LENGTH_MIS 0x2023c
-/* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for
- weight 8 (the most prioritised); 1 stands for weight 1(least
- prioritised); 2 stands for weight 2; tc. */
-#define XCM_REG_NIG1_WEIGHT 0x200d8
/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
sent to STORM; for a specific connection type. The double REG-pairs are
used in order to align to STORM context row size of 128 bits. The offset
@@ -4686,12 +3949,6 @@
connection type (one of 16). */
#define XCM_REG_N_SM_CTX_LD_0 0x20060
#define XCM_REG_N_SM_CTX_LD_1 0x20064
-#define XCM_REG_N_SM_CTX_LD_10 0x20088
-#define XCM_REG_N_SM_CTX_LD_11 0x2008c
-#define XCM_REG_N_SM_CTX_LD_12 0x20090
-#define XCM_REG_N_SM_CTX_LD_13 0x20094
-#define XCM_REG_N_SM_CTX_LD_14 0x20098
-#define XCM_REG_N_SM_CTX_LD_15 0x2009c
#define XCM_REG_N_SM_CTX_LD_2 0x20068
#define XCM_REG_N_SM_CTX_LD_3 0x2006c
#define XCM_REG_N_SM_CTX_LD_4 0x20070
@@ -4868,30 +4125,8 @@
#define XSDM_REG_AGG_INT_EVENT_12 0x166068
#define XSDM_REG_AGG_INT_EVENT_13 0x16606c
#define XSDM_REG_AGG_INT_EVENT_14 0x166070
-#define XSDM_REG_AGG_INT_EVENT_15 0x166074
-#define XSDM_REG_AGG_INT_EVENT_16 0x166078
-#define XSDM_REG_AGG_INT_EVENT_17 0x16607c
-#define XSDM_REG_AGG_INT_EVENT_18 0x166080
-#define XSDM_REG_AGG_INT_EVENT_19 0x166084
-#define XSDM_REG_AGG_INT_EVENT_10 0x166060
-#define XSDM_REG_AGG_INT_EVENT_11 0x166064
-#define XSDM_REG_AGG_INT_EVENT_12 0x166068
-#define XSDM_REG_AGG_INT_EVENT_13 0x16606c
-#define XSDM_REG_AGG_INT_EVENT_14 0x166070
#define XSDM_REG_AGG_INT_EVENT_2 0x166040
-#define XSDM_REG_AGG_INT_EVENT_20 0x166088
-#define XSDM_REG_AGG_INT_EVENT_21 0x16608c
-#define XSDM_REG_AGG_INT_EVENT_22 0x166090
-#define XSDM_REG_AGG_INT_EVENT_23 0x166094
-#define XSDM_REG_AGG_INT_EVENT_24 0x166098
-#define XSDM_REG_AGG_INT_EVENT_25 0x16609c
-#define XSDM_REG_AGG_INT_EVENT_26 0x1660a0
-#define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
-#define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
-#define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
#define XSDM_REG_AGG_INT_EVENT_3 0x166044
-#define XSDM_REG_AGG_INT_EVENT_30 0x1660b0
-#define XSDM_REG_AGG_INT_EVENT_31 0x1660b4
#define XSDM_REG_AGG_INT_EVENT_4 0x166048
#define XSDM_REG_AGG_INT_EVENT_5 0x16604c
#define XSDM_REG_AGG_INT_EVENT_6 0x166050
@@ -4902,16 +4137,6 @@
or auto-mask-mode (1) */
#define XSDM_REG_AGG_INT_MODE_0 0x1661b8
#define XSDM_REG_AGG_INT_MODE_1 0x1661bc
-#define XSDM_REG_AGG_INT_MODE_10 0x1661e0
-#define XSDM_REG_AGG_INT_MODE_11 0x1661e4
-#define XSDM_REG_AGG_INT_MODE_12 0x1661e8
-#define XSDM_REG_AGG_INT_MODE_13 0x1661ec
-#define XSDM_REG_AGG_INT_MODE_14 0x1661f0
-#define XSDM_REG_AGG_INT_MODE_15 0x1661f4
-#define XSDM_REG_AGG_INT_MODE_16 0x1661f8
-#define XSDM_REG_AGG_INT_MODE_17 0x1661fc
-#define XSDM_REG_AGG_INT_MODE_18 0x166200
-#define XSDM_REG_AGG_INT_MODE_19 0x166204
/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
#define XSDM_REG_CFC_RSP_START_ADDR 0x166008
/* [RW 16] The maximum value of the competion counter #0 */
@@ -5119,10 +4344,6 @@
#define MCPR_NVM_COMMAND_FIRST (1L<<7)
#define MCPR_NVM_COMMAND_LAST (1L<<8)
#define MCPR_NVM_COMMAND_WR (1L<<5)
-#define MCPR_NVM_COMMAND_WREN (1L<<16)
-#define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
-#define MCPR_NVM_COMMAND_WRDI (1L<<17)
-#define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
@@ -5223,10 +4444,6 @@
#define MISC_REGISTERS_SPIO_7 7
#define MISC_REGISTERS_SPIO_CLR_POS 16
#define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
-#define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000
-#define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000
-#define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000
-#define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000
#define MISC_REGISTERS_SPIO_FLOAT_POS 24
#define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
@@ -5344,7 +4561,8 @@
#define LATCHED_ATTN_SCPAD_PARITY_MCP 33
#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
-#define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32))
+#define GENERAL_ATTEN_OFFSET(atten_name)\
+ (1UL << ((94 + atten_name) % 32))
/*
* This file defines GRC base address for every block.
* This file is included by chipsim, asm microcode and cpp microcode.
@@ -5568,6 +4786,9 @@
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
#define MDIO_REG_BANK_RX0 0x80b0
+#define MDIO_RX0_RX_STATUS 0x10
+#define MDIO_RX0_RX_STATUS_SIGDET 0x8000
+#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
#define MDIO_RX0_RX_EQ_BOOST 0x1c
#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
@@ -5761,12 +4982,22 @@
#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
#define MDIO_OVER_1G_LP_UP3 0x1E
+#define MDIO_REG_BANK_REMOTE_PHY 0x8330
+#define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
+#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
+#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
+
#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
#define MDIO_REG_BANK_CL73_USERB0 0x8370
+#define MDIO_CL73_USERB0_CL73_UCTRL 0x10
+#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
+#define MDIO_CL73_USERB0_CL73_USTAT1 0x11
+#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
+#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
@@ -5880,6 +5111,13 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_PMA_REG_7101_VER1 0xc026
#define MDIO_PMA_REG_7101_VER2 0xc027
+#define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
+#define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
+#define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
+#define MDIO_PMA_REG_8481_LED3_MASK 0xa832
+#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
+#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
+
#define MDIO_WIS_DEVAD 0x2
/*bcm*/
@@ -5933,6 +5171,12 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_AN_REG_8073_2_5G 0x8329
+#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
+#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
+#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
+#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
+#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
+#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
#define IGU_FUNC_BASE 0x0400
@@ -5965,3 +5209,116 @@ Theotherbitsarereservedandshouldbezero*/
#define COMMAND_REG_SIMD_NOMASK 0x1c
+#define IGU_MEM_BASE 0x0000
+
+#define IGU_MEM_MSIX_BASE 0x0000
+#define IGU_MEM_MSIX_UPPER 0x007f
+#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
+
+#define IGU_MEM_PBA_MSIX_BASE 0x0200
+#define IGU_MEM_PBA_MSIX_UPPER 0x0200
+
+#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
+#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
+
+#define IGU_CMD_INT_ACK_BASE 0x0400
+#define IGU_CMD_INT_ACK_UPPER\
+ (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
+#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
+
+#define IGU_CMD_E2_PROD_UPD_BASE 0x0500
+#define IGU_CMD_E2_PROD_UPD_UPPER\
+ (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
+#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
+
+#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
+#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
+#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
+
+#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
+#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
+#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
+#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
+
+#define IGU_REG_RESERVED_UPPER 0x05ff
+
+
+#define CDU_REGION_NUMBER_XCM_AG 2
+#define CDU_REGION_NUMBER_UCM_AG 4
+
+
+/**
+ * String-to-compress [31:8] = CID (all 24 bits)
+ * String-to-compress [7:4] = Region
+ * String-to-compress [3:0] = Type
+ */
+#define CDU_VALID_DATA(_cid, _region, _type)\
+ (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
+#define CDU_CRC8(_cid, _region, _type)\
+ (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
+#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
+ (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
+#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
+ (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
+#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
+
+/******************************************************************************
+ * Description:
+ * Calculates crc 8 on a word value: polynomial 0-1-2-8
+ * Code was translated from Verilog.
+ * Return:
+ *****************************************************************************/
+static inline u8 calc_crc8(u32 data, u8 crc)
+{
+ u8 D[32];
+ u8 NewCRC[8];
+ u8 C[8];
+ u8 crc_res;
+ u8 i;
+
+ /* split the data into 31 bits */
+ for (i = 0; i < 32; i++) {
+ D[i] = (u8)(data & 1);
+ data = data >> 1;
+ }
+
+ /* split the crc into 8 bits */
+ for (i = 0; i < 8; i++) {
+ C[i] = crc & 1;
+ crc = crc >> 1;
+ }
+
+ NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
+ D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
+ C[6] ^ C[7];
+ NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
+ D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
+ D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^
+ C[6];
+ NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
+ D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
+ C[0] ^ C[1] ^ C[4] ^ C[5];
+ NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
+ D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
+ C[1] ^ C[2] ^ C[5] ^ C[6];
+ NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
+ D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
+ C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
+ NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
+ D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
+ C[3] ^ C[4] ^ C[7];
+ NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
+ D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
+ C[5];
+ NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
+ D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
+ C[6];
+
+ crc_res = 0;
+ for (i = 0; i < 8; i++)
+ crc_res |= (NewCRC[i] << i);
+
+ return crc_res;
+}
+
+
distrib
>
Scientific%20Linux
>
5x
>
x86_64
>
by-pkgid
>
27922b4260f65d317aabda37e42bbbff
>
files
>
2459
