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kernel-2.6.18-238.el5.src.rpm

From: Bhavna Sarathy <bnagendr@redhat.com>
Date: Thu, 2 Sep 2010 17:05:51 -0400
Subject: [misc] amd: unify L3 cache index disable checking
Message-id: <20100902171150.18123.42809.sendpatchset@localhost.localdomain>
Patchwork-id: 28019
O-Subject: [RHEL5.6 PATCH 3/5] Unify AMD L3 cache index disable checking
Bugzilla: 610199
RH-Acked-by: Prarit Bhargava <prarit@redhat.com>
RH-Acked-by: Bob Picco <bpicco@redhat.com>

Resolves BZ 610199, please review and ACK.

>From 90f83269ebbd2c1f59b4265c777aa5dec8ba7eb8 Mon Sep 17 00:00:00 2001
From: Andreas Herrmann <andreas.herrmann3@amd.com>
Date: Wed, 1 Sep 2010 18:29:34 +0200
Subject: [PATCH 3/5] Backport of following mainline commit:

  commit b1ab1b4d9ab9812c77843abec79030292ef0a544
  Author: Borislav Petkov <borislav.petkov@amd.com>
  Date:   Thu Apr 22 16:06:58 2010 +0200

    x86, cacheinfo: Unify AMD L3 cache index disable checking

    All F10h CPUs starting with model 8 resp. 9, stepping 1, support L3
    cache index disable. Concentrate the family, model, stepping checking at
    one place and enable the feature implicitly on upcoming Fam10h models.
    Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
    LKML-Reference: <1271945222-5283-2-git-send-email-bp@amd64.org>
    Signed-off-by: H. Peter Anvin <hpa@zytor.com>

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>

diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c
index 2f3328a..1eb7259 100644
--- a/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -319,16 +319,20 @@ static unsigned int __cpuinit amd_calc_l3_indices(void)
 static void __cpuinit
 amd_check_l3_disable(int index, struct _cpuid4_info *this_leaf)
 {
+	if (boot_cpu_data.x86 != 0x10)
+		return;
+
 	if (index < 3)
 		return;
 
-	if (boot_cpu_data.x86 == 0x11)
+	/* see errata #382 and #388 */
+	if (boot_cpu_data.x86_model < 0x8)
 		return;
 
-	/* see erratum #382 and #388 */
-	if ((boot_cpu_data.x86 == 0x10) &&
-	    ((boot_cpu_data.x86_model < 0x8) ||
-	     (boot_cpu_data.x86_mask  < 0x1)))
+	if ((boot_cpu_data.x86_model == 0x8 ||
+	     boot_cpu_data.x86_model == 0x9)
+		&&
+	    boot_cpu_data.x86_mask < 0x1)
 		return;
 
 	/* not in virtualized environments */
@@ -348,8 +352,7 @@ static int __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_le
 
 	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 		amd_cpuid4(index, &eax, &ebx, &ecx);
-		if (boot_cpu_data.x86 >= 0x10)
-			amd_check_l3_disable(index, this_leaf);
+		amd_check_l3_disable(index, this_leaf);
 	} else {
 		cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
 	}