- Name: verilator
- Version: 3.804
- Release: 1.fc14
- Epoch:
- Group: Applications/Engineering
- License: GPLv2
- Url: http://www.veripool.com/verilator.html
- Summary: A fast simulator for synthesizable Verilog
- Architecture: i686
- Size: 7567103
- Distribution: Fedora Project
- Vendor: Fedora Project
- Packager: Fedora Project
Description:
Verilator is the fastest free Verilog HDL simulator. It compiles
synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis
assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is
especially well suited to create executable models of CPUs for
embedded software design teams.
- OptFlags: -O2 -g -pipe -Wall -Wp,-D_FORTIFY_SOURCE=2 -fexceptions -fstack-protector --param=ssp-buffer-size=4 -m32 -march=i686 -mtune=atom -fasynchronous-unwind-tables
- Cookie:
- Buildhost: x86-20.phx2.fedoraproject.org
Sources packages:
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